6.

976
High Speed Communication Circuits and Systems
Lecture 15
Integer-N Frequency Synthesizers

Michael Perrott
Massachusetts Institute of Technology

Copyright © 2003 by Michael H. Perrott

 Integer-N Frequency Synthesizers in Wireless Systems
Zin
From Antenna PC board Mixer
and Bandpass trace RF in IF out
Filter Zo Package LNA To Filter
Interface

LO signal
VCO
Reference ref(t) Frequency v(t) out(t)
Frequency Synthesizer

ref(t) e(t) Charge v(t) out(t)

Loop
PFD
Pump Filter
VCO

div(t) Divider

ƒ Design Issues: low noise, fast settling time, low power

M.H. Perrott MIT OCW
 Overview of Integer-N Frequency Synthesizer

ref(t) e(t) v(t) out(t)

Loop
PFD
Filter
VCO

div(t) Divider

N
ƒ VCO produces high frequency sine wave

M.H. Perrott MIT OCW

 Overview of Integer-N Frequency Synthesizer

ref(t) e(t) v(t) out(t)

Loop
PFD
Filter
VCO

div(t) Divider

N
ƒ VCO produces high frequency sine wave
ƒ Divider divides down VCO frequency

M.H. Perrott MIT OCW

 Overview of Integer-N Frequency Synthesizer

ref(t) e(t) v(t) out(t)

Loop
PFD
Filter
VCO

div(t) Divider

N
ƒ VCO produces high frequency sine wave
ƒ Divider divides down VCO frequency
ƒ PFD compares phase of ref and div

M.H. Perrott MIT OCW

 Overview of Integer-N Frequency Synthesizer

ref(t) e(t) v(t) out(t)

Loop
PFD
Filter
VCO

div(t) Divider

N
ƒ VCO produces high frequency sine wave
ƒ Divider divides down VCO frequency
ƒ PFD compares phase of ref and div
ƒ Loop filter smooths phase error signal

M.H. Perrott MIT OCW

 Overview of Integer-N Frequency Synthesizer

Fref Fout = N Fref

ref(t) e(t) v(t) out(t)

Loop
PFD
Filter
VCO

div(t) Divider

N
ƒ VCO produces high frequency sine wave
ƒ Divider divides down VCO frequency
ƒ PFD compares phase of ref and div
ƒ Loop filter smooths phase error signal

VCO frequency locks to ref. frequency multiplied by N

M.H. Perrott MIT OCW
 Popular VCO Structures

LC oscillator
VCO Amp
Vout

-Ramp Vin C L Rp

Ring oscillator

Vout

Vin
-1

ƒ LC Oscillator: low phase noise, large area

ƒ Ring Oscillator: easy to integrate, higher phase noise
M.H. Perrott MIT OCW
 Model for Voltage to Frequency Mapping of VCO
LC oscillator
VCO Amp
Vout

-Ramp Vin C L Rp

Fvco

Ring oscillator

Vout
Fout
fc
Vin VCO
Frequency slope=Kv
-1

vin
Vbias
Input Voltage

M.H. Perrott MIT OCW

 Model for Voltage to Phase Mapping of VCO

ƒ Time-domain frequency relationship (from previous

slide)

ƒ Time-domain phase relationship

ƒ Intuition of integral relationship between frequency and

phase:
1/Fvco= α

out(t)

out(t)

1/Fvco= α+ε
M.H. Perrott MIT OCW
 Frequency-Domain Model for VCO

ƒ Time-domain relationship (from previous slide)

ƒ Corresponding frequency-domain model

Laplace-Domain Frequency-Domain

v(t) out(t) v(t) Φout(t) v(t) Φout(t)

2πKv Kv
s jf
VCO VCO VCO

M.H. Perrott MIT OCW

 Divider

ƒ Implementation
Counter
N count value
out div(t)
out(t)

out(t)

div(t)

N=6
ƒ Time-domain model
- Frequency:
- Phase:
M.H. Perrott MIT OCW
 Frequency-Domain Model of Divider

ƒ Time-domain relationship between VCO phase and

divider output phase (from previous slide)

ƒ Corresponding frequency-domain model (same as

Laplace-domain)

out(t) div(t) Φout(t) 1 Φdiv(t)

Divider
N
Divider

M.H. Perrott MIT OCW

 Phase Detector (PD)

ƒ XOR structure
- Average value of error pulses corresponds to phase error
- Loop filter extracts the average value and feeds to VCO
ref(t)

e(t)

div(t)

ref(t)

div(t)

1
e(t)
-1

M.H. Perrott MIT OCW

 Modeling of XOR Phase Detector

ƒ Average value of pulses is extracted by loop filter

- Look at detector output over one cycle:
W

1
e(t)
-1

T/2

ƒ Equation:

M.H. Perrott MIT OCW

 Relate Pulse Width to Phase Error

ƒ Two cases:

−π < Φref − Φdiv < 0 0 < Φref − Φdiv < π

T/2 T/2

ref(t) ref(t)

div(t) div(t)

1 1
e(t) e(t)
-1 -1
W W

Φref − Φdiv Φref − Φdiv

W=- π T/2 W= T/2
π

M.H. Perrott MIT OCW

 Overall XOR Phase Detector Characteristic
−π < Φref − Φdiv < 0 0 < Φref − Φdiv < π
T/2 T/2

ref(t) ref(t)

div(t) div(t)

1 1
e(t) e(t)
-1 -1
W W

Φref − Φdiv Φref − Φdiv

W=- π T/2 W= T/2
π

avg{e(t)}
gain = -2/π 1 gain = 2/π

Φref - Φdiv
−π −π/2 0 π/2 π
-1

phase detector
range = π
M.H. Perrott MIT OCW
 Frequency-Domain Model of XOR Phase Detector

ƒ Assume phase difference confined within 0 to π radians

- Phase detector characteristic looks like a constant gain
element
avg{e(t)}
gain = -2/π 1 gain = 2/π

Φref - Φdiv
−π −π/2 0 π/2 π
-1

ƒ Corresponding frequency-domain model

ref(t) e(t)
PD Φref(t) e(t)
2
π

Φdiv(t) PD gain
div(t)
M.H. Perrott MIT OCW
 Loop Filter

ƒ Consists of a lowpass filter to extract average of

phase detector error pulses
ƒ Frequency-domain model

Laplace-Domain Frequency-Domain

e(t) v(t) e(t) v(t) e(t) v(t)

Loop
H(s) H(f)
Filter
H(s)
VCO VCO

ƒ First order example

e(t) R1 v(t)

C1

M.H. Perrott MIT OCW

 Overall Linearized PLL Frequency-Domain Model

ƒ Combine models of individual components

Laplace-Domain Model
XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Φout(t)
2 2πKv
H(s)
π s

Divider
Φdiv(t)
1
N

Frequency-Domain Model
XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Φout(t)
2 Kv
H(f)
π jf

Divider
Φdiv(t)
1
N

M.H. Perrott MIT OCW

 Open Loop versus Closed Loop Response

ƒ Frequency-domain model
XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Φout(t)
2 Kv
H(f)
π jf

Divider
Φdiv(t)
1
N

ƒ Define A(f) as open loop response

ƒ Define G(f) as a parameterizing function (related to

closed loop response)

M.H. Perrott MIT OCW

 Classical PLL Transfer Function Design Approach

1. Choose an appropriate topology for H(f)

ƒ Usually chosen from a small set of possibilities
2. Choose pole/zero values for H(f) as appropriate for
the required filtering of the phase detector output
ƒ Constraint: set pole/zero locations higher than
desired PLL bandwidth to allow stable dynamics to
be possible
3. Adjust the open-loop gain to achieve the required
bandwidth while maintaining stability
ƒ Plot gain and phase bode plots of A(f)
ƒ Use phase (or gain) margin criterion to infer stability

M.H. Perrott MIT OCW

 Example: First Order Loop Filter

ƒ Overall PLL block diagram

XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Φout(t)
2 Kv
H(f)
π jf

Divider
Φdiv(t)
1
N

ƒ Loop filter

e(t) R1 v(t)

C1

M.H. Perrott MIT OCW

 Closed Loop Poles Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
Open loop 20log|A(f)| C
gain
increased
Dominant
pole pair B

0 dB f
fp
A
C
B
A Re{s}
angle(A(f)) 0
o
-90

A
-120o PM = 59o for A
PM = 45o for B
B
-150o PM = 33o for C

-180o
C

ƒ Higher open loop gain leads to an increase in Q of

closed loop poles
M.H. Perrott MIT OCW
 Corresponding Closed Loop Response

Frequency Response of G(f) Step Response of G(f)

C
5 dB C 1.4
B
0 dB B
A
-5 dB A
1

0.6

f 0 t
fp

ƒ Increase in open loop gain leads to

- Peaking in closed loop frequency response
- Ringing in closed loop step response
M.H. Perrott MIT OCW
 The Impact of Parasitic Poles

ƒ Loop filter and VCO may have additional parasitic

poles and zeros due to their circuit implementation
ƒ We can model such parasitics by including them in
the loop filter transfer function
ƒ Example: add two parasitic poles to first order filter

e(t) R1 v(t)
Parasitics
C1

M.H. Perrott MIT OCW

 Closed Loop Poles Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
20log|A(f)|
Open loop C
gain
increased
Dominant
pole pair
0 dB f
fp fp2fp3
Non-dominant B
poles
C
B A Re{s}
angle(A(f)) A
-90
o
A 0
o
PM = 72 for A
PM = 51o for B
-165
o B
o
-180
PM = -12o for C
o
-240

o
-315 C

M.H. Perrott MIT OCW

 Corresponding Closed Loop Response

Closed Loop Frequency Response Closed Loop Step Response

C

0 dB B
A C

1 B

Frequency Time

ƒ Increase in open loop gain now eventually leads to

instability
- Large peaking in closed loop frequency response
- Increasing amplitude in closed loop step response
M.H. Perrott MIT OCW
 Response of PLL to Divide Value Changes
XOR PD
Loop Filter VCO
Φref(t) e(t) v(t) Φout(t)
2 Kv
H(f)
π jf

Divider
Φdiv(t)
1
N

N+1
N
t

ƒ Change in output frequency achieved by changing the

divide value
ƒ Classical approach provides no direct model of
impact of divide value variations
- Treat divide value variation as a perturbation to a linear
system
ƒ PLL responds according to its closed loop response
M.H. Perrott MIT OCW
 Response of an Actual PLL to Divide Value Change

ƒ Example: Change divide value by one

Synthesizer Response To Divider Step

93
N (Divide Value)

92.8

92.6

92.4

92.2

92

91.8
40 60 80 100 120 140 160 180 200 220 240

1.87
Output Frequency (GHz)

1.86

1.85

1.84

1.83
40 60 80 100 120 140 160 180 200 220 240
Time (microseconds)

M.H. Perrott
- PLL responds according to closed loop response!
MIT OCW
 What Happens with Large Divide Value Variations?
ƒ PLL temporarily loses frequency lock (cycle slipping
occurs)
Synthesizer Response To Divider Step
96
N (Divide Value)
95

94

93

92
40 60 80 100 120 140 160 180 200 220 240
Output Frequency (GHz)

1.92

1.9

1.88

1.86

1.84

40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- Why does this happen?

M.H. Perrott MIT OCW
 Recall Phase Detector Characteristic

avg{e(t)}
gain = -2/π 1 gain = 2/π

Φref - Φdiv
−π −π/2 0 π/2 π
-1

ƒ To simplify modeling, we assumed that we always

operated in a confined phase range (0 to π)
- Led to a simple PD model
ƒ Large perturbations knock us out of that confined
phase range
- PD behavior varies depending on the phase range it
happens to be in

M.H. Perrott MIT OCW

 Cycle Slipping
ƒ Consider the case where there is a frequency offset
between divider output and reference
- We know that phase difference will accumulate
ref(t)

div(t)

ƒ Resulting ramp in phase causes PD characteristic to

be swept across its different regions (cycle slipping)
avg{e(t)}
gain = -2/π 1 gain = 2/π

Φref - Φdiv
−π −π/2 0 π/2 π
-1

M.H. Perrott MIT OCW

 Impact of Cycle Slipping

ƒ Loop filter averages out phase detector output

ƒ Severe cycle slipping causes phase detector to
alternate between regions very quickly
- Average value of XOR characteristic can be close to
zero
- PLL frequency oscillates according to cycle slipping
- In severe cases, PLL will not re-lock
ƒ PLL has finite frequency lock-in range!

XOR DC characteristic
cycle slipping
1

Φref - Φdiv
−π π 3π nπ (n+2)π
-1

M.H. Perrott MIT OCW

 Back to PLL Response Shown Previously
ƒ PLL output frequency indeed oscillates
- Eventually locks when frequency difference is small enough
Synthesizer Response To Divider Step
96
N (Divide Value)

95

94

93

92
40 60 80 100 120 140 160 180 200 220 240
Output Frequency (GHz)

1.92

1.9

1.88

1.86

1.84

40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- How do we extend the frequency lock-in range?

M.H. Perrott MIT OCW
 Phase Frequency Detectors (PFD)

ƒ Example: Tristate PFD

up(t)
1 D Q
ref(t) Q
R
e(t)

R
1 D Q
down(t)
div(t) Q

Ref(t)

Div(t)

Up(t)

Down(t)

1
E(t)
0
-1
M.H. Perrott MIT OCW
 Tristate PFD Characteristic
ƒ Calculate using similar approach as used for XOR
phase detector avg{e(t)}

1
gain = 1/(2π)

−2π
Φref - Φdiv
2π

−1

phase detector
range = 4π

ƒ Note that phase error characteristic is asymmetric

about zero phase
- Key attribute for enabling frequency detection
M.H. Perrott MIT OCW
 PFD Enables PLL to Always Regain Frequency Lock

ƒ Asymmetric phase error characteristic allows positive

frequency differences to be distinguished from
negative frequency differences
- Average value is now positive or negative according to
sign of frequency offset
- PLL will always relock
Tristate DC characteristic
cycle slipping

−2π
Φref - Φdiv
0 2π 4π 2nπ

lock
-1

M.H. Perrott MIT OCW

 Another PFD Structure

ƒ XOR-based PFD
D Q

ref(t) D Q Q
ref/2(t) R
Q e(t)

div(t) D Q div/2(t)
Q D SQ
Q

Divide-by-2 Phase Frequency

Detector Detector

ref(t)

div(t)

ref/2(t)

div/2(t)
1
e(t)
-1

M.H. Perrott MIT OCW

 XOR-based PFD Characteristic

ƒ Calculate using similar approach as used for XOR phase

detector
avg{e(t)}
gain = 1/π
1

−3π
Φref - Φdiv
−2π 0 π 2π 4π 5π

−1

phase detector
range = 2π

ƒ Phase errror characteristic asymmetric about zero phase

- Average value of phase error is positive or negative during
cycle slipping depending on sign of frequency error

M.H. Perrott MIT OCW

 Linearized PLL Model With PFD Structures

ƒ Assume that when PLL in lock, phase variations are

within the linear range of PFD
- Simulate impact of cycle slipping if desired (do not
include its effect in model)
ƒ Same frequency-domain PLL model as before, but
PFD gain depends on topology used

Tristate: α=1
PFD XOR-based: α=2
Loop Filter VCO
Φref(t) α e(t) v(t) Φout(t)
Kv
H(f)
2π jf

Divider
Φdiv(t)
1
N

M.H. Perrott MIT OCW

 Type I versus Type II PLL Implementations

ƒ Type I: one integrator in PLL open loop transfer

function
- VCO adds on integrator
- Loop filter, H(f), has no integrators
ƒ Type II: two integrators in PLL open loop transfer
function
- Loop filter, H(f), has one integrator
Tristate: α=1
PFD XOR-based: α=2
Loop Filter VCO
Φref(t) α e(t) v(t) Φout(t)
Kv
H(f)
2π jf

Divider
Φdiv(t)
1
N

M.H. Perrott MIT OCW

 VCO Input Range Issue for Type I PLL Implementations

ƒ DC output range of gain block versus integrator

Gain Block Integrator
0 0
K
K s

ƒ Issue: DC gain of loop filter often small and PFD

output range is limited
- Loop filter output fails to cover full input range of VCO
VDD
No Output Range
Integrator of Loop Filter
Gnd

ref(t) e(t) Loop v(t) out(t)

PFD Filter
VCO

Divider

N[k]
M.H. Perrott MIT OCW
 Options for Achieving Full Range Span of VCO
ƒ Type I
- Add a D/A converter to provide coarse tuning
ƒ Adds power and complexity
ƒ Steady-state phase error inconsistently set
ƒ Type II
- Integrator automatically provides DC level shifting
ƒ Low power and simple implementation
ƒ Steady-state phase error always set to zero
Type I Type II

Output Range Output Range

Course of Loop Filter of Loop Filter
Tune D/A
VDD VDD
No Contains
Integrator Integrator
Gnd Gnd

e(t) Loop v(t) e(t) v(t)

C.P. Loop
Filter C.P.
Filter
M.H. Perrott MIT OCW
 A Common Loop Filter for Type II PLL Implementation

ƒ Use a charge pump to create the integrator

- Current onto a capacitor forms integrator
- Add extra pole/zero using resistor and capacitor
ƒ Gain of loop filter can be adjusted according to the
value of the charge pump current
ƒ Example: lead/lag network

e(t) i(t) v(t)

Charge
Pump
R1
C1
C2

M.H. Perrott MIT OCW

 Charge Pump Implementations

ƒ Switch currents in and out:

Single-Ended Differential

Icp Icp Icp

up(t)
Iout(t)
Iout(t)

down(t) e(t) e(t)

Icp 2Icp

M.H. Perrott MIT OCW

 Modeling of Loop Filter/Charge Pump

ƒ Charge pump is gain element

ƒ Loop filter forms transfer function

Charge Loop
Pump Filter
e(t) v(t)
Icp H(s)

ƒ Example: lead/lag network from previous slide

M.H. Perrott MIT OCW

 PLL Design with Lead/Lag Filter

ƒ Overall PLL block diagram

Tristate: α=1
PFD XOR-based: α=2 Charge
Pump Loop Filter VCO
Φref(t) α e(t) v(t) Kv Φout(t)
Icp H(f)
2π jf

Divider
Φdiv(t)
1
N

ƒ Loop filter

ƒ Set open loop gain to achieve adequate phase margin

- Set f lower than and f
z p higher than desired PLL bandwidth
M.H. Perrott MIT OCW
 Closed Loop Poles Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
Open loop 20log|A(f)|
gain C
increased

Dominant
B pole pair
0 dB f
fz fp A
Non-dominant
C pole
B
A Re{s}
angle(A(f)) A BC 0
o
120
PM = 54oo for B
PM = 53 for A
PM = 55o for C A
o
-140

o
B
-160

o
-180 C

ƒ Open loop gain cannot be too low or too high if

reasonable phase margin is desired
M.H. Perrott MIT OCW
 Impact of Parasitics When Lead/Lag Filter Used

ƒ We can again model impact of parasitics by including

them in loop filter transfer function

e(t) i(t) v(t)

Charge Parasitics
Pump
R1
C1
C2

ƒ Example: include two parasitic poles with the lead/lag

transfer function

M.H. Perrott MIT OCW

 Closed Loop Poles Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations of G(f)
Im{s}
Open loop 20log|A(f)| C
gain Dominant
increased pole pair

B
0 dB f
fz fp fp2 fp3
Non-dominant
poles A
C
B Re{s}
A
angle(A(f)) A BC 0
o
120
A

o
PM = 46o for A
-140
PM = 38o for B
B
o
-160

o
-180 C
PM = -7o for C

ƒ Closed loop response becomes unstable if open loop

gain is too high
M.H. Perrott MIT OCW
 Negative Issues For Type II PLL Implementations

Peaking caused by Step Responses for a Second Order

|G(f)| undesired pole/zero pair G(f) implemented as a Bessel Filter
1.4

Normalized Amplitude
Type II: fz/fo = 1/3
fcp fz Type II: fz/fo = 1/8

1 1
Type I

0.6

0 f 0
fz fo 1 2 3 4
Frequency (Hz) Normalized time: t*fo

ƒ Parasitic pole/zero pair causes

- Peaking in the closed loop frequency response
ƒ A big issue for CDR systems, but not too bad for wireless
- Extended settling time due to parasitic “tail” response
ƒ Bad for wireless systems demanding fast settling time
M.H. Perrott MIT OCW