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PRACTICAL FILE

NAME ABHINAV UPADHYAY

BRANCH ECE
YEAR 4th YEAR
ENROLLMENT NUMBER 40118007318
SUBJECT ADVANCED VLSI DESIGN

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INDEX
S.No EXPERIMENT DATE PAGE SIGNATUR
NUMBER E

1. Introduction of VLSI Basics and EDA 27/08/20 3-11

Tools such as Mentor Graphics (Eldo
SPICE) and OrCAD PSPTCE

2. To design a CMOS Inverter and study 03/09/20 12-14

its DC response and Transient
response

3. To design 2 input NAND logic gate 10/09/20 15-16

and study its Transient Characteristics.

4. To design 2 input NOR logic gate and 17/09/20 17-18

study its Transient Characteristics.

5. To design a NMOS Source Amplifier 24/09/20 19-20

and study its DC response.

6. To design a Voltage Follower and 01/10/20 21-22

study its DC response.

7. To design and study the characteristics 08/10/20 23-24

of CMOS XOR gate

8. To design and study the characteristics 28/10/20 25-26

of CMOS D Flip Flop

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EXPERIMENT 1
AIM: Introduction of VLSI Basics and EDA Tools such as Mentor Graphics (Eldo SPICE) and OrCAD
PSPTCE

Requirements: EDA Tools- Mentor Graphics (Eldo SPICE) and OrCAD PSPICE

Background:
Very-large-scale integration (VLSI) is a process of combining thousands of transistors into a single chip. It
started in the l970s with the development of complex semiconductor and communication technologies.
The increase in density happens through multiple developments. Number of devices Greater than 10000
gate/chip or 1 million transistors/chip. Ex: 16-bit, 32- bit, 64-bit microprocessor. Some of which would be a
reduction in size, management in power consumption among others,

• Reduces the size of circuits

• Reduces the effective cost of the devices

• Increases the operating speed of circuits

• Requires less power than discrete components

• Higher reliability

• Occupies a relatively smaller area

The design of a VLSI LC consists broadly of 2 parts. Front end design includes digital design using HDLs
such as Verilog, VHDL, SystemVerilog and the like. It includes design verification through simulaton and
other verification techniques. The process includes designing, starting from gates to design for testability.
Backend design comprises of CMOS library design audits characterization. It also covers physical design
and fault simulation. The entire design procedure follows a step by step approach.

EDA Tools Basics:

1) Mentor Graphics (Eldo Spice)

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The Eldo™ analog simulator is the core component of a comprehensive suite of analog and mixed-signal
simulation tools. Eldo offers a unique partitioning scheme allowing the use of different algorithms on
differing portions of design. It allows the user a flexible control of simulation accuracy using a wide range
of device model libraries, and gives a high accuracy yield in combination with high speed and high
performance.

The following is a list of the major product features of Eldo:

• Eldo is the core technology allowing to address RF simulation (Eldo RF) and mixed signal (ADVance
MS and ADVance MS Mach)

• Simulation of very large circuits (up to around 300,000 transistors) in time and frequency domains

• 3x to 1Ox gain in simulation speed over other commercial SPICE simulators, while maintaining same
accuracy

• Three complementary transient simulation algorithms (OSR, Newton, IBM)

• Flexible user control of simulation accuracy

• Unique transient noise algorithm

• Advanced analysis options such as pole-zero, enhanced Monte-Carlo analysis

• S and Z-domain generalized transfer functions

• Reliability simulation

• Extensive device model libraries including leading MOS, bipolar and MESFET transistor models such as
the BSIM3v3.x, BSIM 4, MM9, Mextram and HICUM

• IBIS (I/0 Buffer Information Specification) model support

• Integration into Mentor Graphics IC flow, consisting of Design Architect IC for schematic capture, IC
station for the layout side, and Caliber/Caliber xRC for DRC/L VS and extraction. This flow provides a
complete, front-to-back design and verification environment for analog, mixed-signal and RF.

• Integration into Cadence's Analog Artist environment (Artist Link)

Eldo Input and Output Files

The following flowchart shows the input files that must be provided for an Eldo simulation run and the
output files that Eldo produces:

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The figure above shows the main tiles used by Eldo. A brief description of each is given below:
<file>.cir The main Eldo control file, containing circuit netlist, stimulus and simulation control commands.
This file is SPTCE compatible, the Eldo control language being a superset of the Berkeley SPTCE syntax.

<file>.chi SPTCE compatible output log file containing ASCTT data, including results and error messages.

<file>.wdb A binary output file for mixed-signal JWDB format files. Viewed with the EZwave waveform
viewer. The resulting output file is smaller than files based on the cou format files.

<.file>.swd A saved windows file used by the EZwave waveform viewer. This file contains information on
waveforms and their display and cursor settings, window format settings and complex waveform transition
settings.

<file>.cou A binary output file containing Eldo analog simulation results data. A special interface is
provided to access this data from your own post-processor software if required. MGC postprocessors also
read and write to this file. Please refer to Eldo cou Library User's Manual for more details.

<file>.ext A file containing extraction or waveform information, created when using a .EXTRACT
command in the net list. This file will not always be output, it depends on the type of simulation and the
specification of the .EXTRACT command.

Getting Started
How to Run Eldo

To run an Eldo simulation, a .cir control file must be supplied to the simulator. As can be seen in the
previous example, this file must include the following:

• Circuit connectivity, i.e. a netlist.

• Model parameter values defining the specific device models to be used.

• Electrical stimuli (sources).

• Simulation options and commands.

Schematic Example

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This example consists of a simple cascade of three inverters. The figures below show the circuit diagram
for the cascade together with the inverter subcircuit. In order to create the Eldo netlist, node names must
be assigned to the circuit. The complete netlist is shown on the following page.

Sample circuit .cir control file

• MOS model definitions
.model m1 nmos level =3 vto=1v uo=550 vmax =2.0e5

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Running a Simulation

use the following command: eldo cir_ file name.cir

After the simulation has been completed, Eldo writes simulator information to the .chi file. This file will
contain details of the simulation including any warning or error messages, which may have been
encountered during simulation. A binary .wdb file is also generated by default as an output of simulation.

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The user can view the results written to the .wdb file, with the EZwave viewer. The .wdb file can be
opened in the EZwave viewer the using the following command:
ezwave cir_file_name.wdb

EZwave output (.wdb)

2) PSPICE OrCAD (PC Simulation Program for Integrated Circuit Engineering)

i) Resistors Capacitors and Inductors:

Syntax:

NAME NODE A NODE B VALUE

with NAME Rxxx = resistor, Lxxx = inductor, Cxxx = capacitor

Example:

CS 3 4 l.0uF

ii) BJT Parameters

Syntax:

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Qxxx collector node base node emitter node Modelname

Example:

Q1 3 2 1 NPN

.MODEL NPN NPN(BF=200 CJC=20pf CJE=20pf)

iii) MOSFET Parameters

Syntax:

Mname drain gate source bulk/substrate NMOS

Example:

M1 10 20 0 0 NFET

.MODEL NFET NMOS(LEVEL=O VT0=2 K.P=0.l)

TYPES OF ANALYSES

.DC (Large-Signal Transfer Characteristic)

Syntax

.DC SOURCE START STOP INCR

SOURCE is the voltage or current source
Transfer characteristics are obtained by incrementing the SOURCE from START to STOP in steps of
INCR

Example:

.DC VIN -5 5 0.1

.AC (Sinusoidal Steady-State Frequency Response)

Syntax:

.AC SCALE-TYPE NPOINTS FSTART FSTOP

SCALE-TYPE:

LTN linear increments

NPOINTS specifies the number of frequencies between FSTART And FSTOP

DEC logarithmic increments

NPOINTS defines the number of points per decade

OCT octaves of frequency

NPOINTS defines the number of points per octave

Example:

.AC DEC 50 lK IMEG

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Performs a sinusoidal steady-state analysis over 3 decades of frequency from lkHz to l Mhz, computing
the response at 50 points within each decade

If an analysis at a single frequency is desired, NPOINTS should be set to one and FST ART= FSTOP

.TRAN (Transient Analysis)

To compute the output of the circuit as a function of time

Syntax:

.TRAN TSTEP TSTOP TSTART TINCR UIC(optional)

Analysis begins at t = 0 and ends at t = TSTOP seconds
output is printed at every increment TSTEP
if TSTART is nonzero it only plots starting at TSTART
if TINCR is omitted the default TINCR value is (TSTOP - TSTART)/50

UIC user initial condition ... the initial conditions specified in capacitor and inductor element statements
are used instead

NOTE: .IC control line can be used to set an initial condition for any node in the circuit

.TF (Small-Signal Transfer Function)

Syntax:

.TF OUTPUT_ VARIABLE INPUT VARIABLE

To perform a small signal analysis using small-signal linear models for nonlinear devices

INPUT_ VARIABLE voltage or current source

Example:
.TF V(l,2) VIN

Finds small-signal voltage gain between nodes 1 and 2 as the output variable

.TF I(V1) VS

Finds the small-signal transconductance using the current through the

source V 1 as the output variable and VS as the input variable

General Format :

.PROBE

.PROBE {|output variable ... |}

.PROBE tells PSpice to write the results of the DC, AC or transient simulation in a format that the Probe
graphics post-processor can read. If .PROBE is followed by the optional [output variable! then only those
signals will be saved .. PROBE alone means save all signal data thus the file created (PROBE.DAT) may
become huge.

Examples:

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.PROBE

te11s PSpice to save all signal data into PROBE.DAT .

. PROBE V(2)

te11s PSpice to save only the signal voltage data for node 2 into PROBE.DAT

.OP - Bias Point Analysis

General Format:

.OP

The .OP command tells PSpice to print detailed information about the bias point in the .OUT tile.

Example:

.OP

.PRINT – print

General formats:

.PRINT[DC,AC,NOISE,TRAN]|output variable…|

The .PRINT tells Pspice to create a table of the output variable signal in the .OUT file for either a
DC,AC,TRAN or NOISE analysis

Examples:

.PRINNT TRAN V(5) V(9)

Tells Pspice to make a table of the results of a transient analysis run for the voltages at nodes 5 and 9

.PRINT TRAN V(2,3)

Tells Pspice to make a table of the results of a transient analysis run for the voltages differences between
nodes 5 and 9

General

Title line must always be first

Use “+” to continue statement on next line

Use “*” to comment out an entire line

Use “;” to comment out characters following semicolon

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EXPERIMENT 2

AIM: To design a CMOS Inverter and study its DC response and Transient response

REQUIREMENTS: Mentor- Graphics Tool

CIRCUIT ANALYSIS:

OBSERVATIONS:
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1>DC response

2>Transient Response

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RESULT:CMOS inverter has been designed using Mentor Graphics Tool and DC
response and Transient response has been observed.

PRECAUTIONS AND SOURCES OF ERRORS:

▪ Follow the Mentor Graphics instructions and steps strictly

▪ Observe the result carefully
▪ Resolve any error shown in check report window before saving the schematic.

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EXPERIMENT 3

AIM: To design 2 input NAND logic gate and study its Transient Characteristics.

REQUIREMENTS: Mentor- Graphics Tool

CIRCUIT ANALYSIS:

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OBSERVATIONS:

RESULT:2 input NAND logic gate has been designed using Mentor Graphics Tool and
Transient response has been observed.

PRECAUTIONS AND SOURCES OF ERRORS:

▪ Follow the Mentor Graphics instructions and steps strictly

▪ Observe the result carefully
▪ Resolve any error shown in check report window before saving the schematic.

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EXPERIMENT 4

AIM: To design 2 input NOR logic gate and study its Transient Characteristics.

REQUIREMENTS: Mentor- Graphics Tool

CIRCUIT ANALYSIS:

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OBSERVATIONS:

RESULT:2 input NOR logic gate has been designed using Mentor Graphics Tool and
Transient response has been observed.

PRECAUTIONS AND SOURCES OF ERRORS:

▪ Follow the Mentor Graphics instructions and steps strictly

▪ Observe the result carefully
▪ Resolve any error shown in check report window before saving the schematic.

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EXPERIMENT 5

AIM: To design a NMOS Source Amplifier and study its DC response.

REQUIREMENTS: Mentor- Graphics Tool

CIRCUIT ANALYSIS:

OBSERVATIONS:

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RESULT: NMOS Common Source Amplifier gate has been designed using Mentor
Graphics Tool and DC response has been observed.

PRECAUTIONS AND SOURCES OF ERRORS:

▪ Follow the Mentor Graphics instructions and steps strictly

▪ Observe the result carefully
▪ Do not forget to apply DC source for biasing
▪ Resolve any error shown in check report window before saving the schematic.

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EXPERIMENT 6

AIM: To design a Voltage Follower and study its DC response.

REQUIREMENTS: Mentor- Graphics Tool

CIRCUIT ANALYSIS:

OBSERVATIONS:

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RESULT: NMOS Common Source Amplifier gate has been designed using Mentor
Graphics Tool and DC response has been observed.

PRECAUTIONS AND SOURCES OF ERRORS:

▪ Follow the Mentor Graphics instructions and steps strictly

▪ Observe the result carefully
▪ Do not forget to apply DC source for biasing
▪ Resolve any error shown in check report window before saving the schematic.

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EXPERIMENT 7

AIM: To design and study the characterstic of CMOS XOR gate

Software Required: Mentor graphics

Mathematical Diagram

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OUTPUT

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EXPERIMENT 8

AIM:To design and study the characterstic of CMOS D flip flop.

Software Required: Mentor Graphics

SCHEMATIC DIAGRAM

SIMULATION

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OUTPUT

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