56 Chapter 1 Introduction

sizes below 180 nm, transistors also leak a significant amount of current even when they
should be OFF. Thus, chips now draw static power even when they are idle. One of the
central challenges of VLSI design is making good trade-offs between performance and
power for a particular application. The cost of a chip includes nonrecurring engineering
(NRE) expenses for the design and masks, along with per-chip manufacturing costs
related to the size of the chip. In processes with smaller feature sizes, the per-unit cost
goes down because more transistors can be packed into a given area, but the NRE
increases. The latest manufacturing processes are only cost-effective for chips that will sell
in huge volumes. Nevertheless, plenty of interesting markets exist for chips in mature,
inexpensive manufacturing processes.
To quantify how a chip meets these objectives, we must develop and analyze more
complete models. The remainder of this book will expand on the material introduced in
this chapter. Of course, transistors are not simply switches. Chapter 2 examines the cur-
rent and capacitance of transistors, which are essential for estimating delay and power. A
more detailed description of CMOS processing technology and layout rules is presented
in Chapter 3. The next four chapters address the fundamental concerns of circuit design-
ers. The models from Chapter 2 are too detailed to apply by hand to large systems, yet not
detailed enough to fully capture the complexity of modern transistors. Chapter 4 develops
simplified models to estimate the delay of circuits. If modern chips were designed to
squeeze out the ultimate possible performance without regard to power, they would burn
up. Thus, it is essential to estimate and trade off the power consumption against perfor-
mance. Moreover, low power consumption is crucial to mobile battery-operated systems.
Power is considered in Chapter 5. Wires are as important as transistors in their contribu-
tion to overall performance and power, and are discussed in Chapter 6. Chapter 7
addresses design of robust circuits with a high yield and low failure rate.
Simulation is discussed in Chapter 8 and is used to obtain more accurate performance
and power predictions as well as to verify the correctness of circuits and logic. Chapter 9
considers combinational circuit design. A whole kit of circuit families are available with
different trade-offs in speed, power, complexity, and robustness. Chapter 10 continues
with sequential circuit design, including clocking and latching techniques.
The next three chapters delve into CMOS subsystems. Chapter 11 catalogs designs
for a host of datapath subsystems including adders, shifters, multipliers, and counters.
Chapter 12 similarly describes memory subsystems including SRAMs, DRAMs, CAMs,
ROMs, and PLAs. Chapter 13 addresses special-purpose subsystems including power dis-
tribution, clocking, and I/O.
The final chapters address practicalities of CMOS system design. Chapter 14 focuses
on a range of current design methods, identifying the issues peculiar to CMOS. Testing,
design-for-test, and debugging techniques are discussed in Chapter 15. Hardware
description languages (HDLs) are used in the design of nearly all digital integrated cir-
cuits today. Appendix A provides side-by-side tutorials for Verilog and VHDL, the two
dominant HDLs.
A number of sections are marked with an “optional” icon. These sections describe par-
ticular subjects in greater detail. You may skip over these sections on a first reading and
return to them when they are of practical relevance. To keep the length of this book under
control, some optional topics have been published on the Internet rather than in print.
These sections can be found at www.cmosvlsi.com and are labeled with a “Web
Enhanced” icon. A companion text, Digital VLSI Chip Design with Cadence and Synopsys
CAD Tools [Brunvand09], covers practical details of using the leading industrial CAD
tools to build chips.