120 Chapter 3 CMOS Processing Technology

n-transistor p-transistor contribute to large gate leakage currents. Many processes offer a second,
thicker oxide for the I/O transistors (see Section 13.6). For example, 3.3 V
I/O circuits commonly use 0.35 Rm channel lengths and 7 nm gate oxides.
When gate leakage is a problem and high-k dielectrics are unavailable, an
n+ p n+ p+ n p+ intermediate oxide thickness may also be provided to reduce leakage. Again,
multiple masks are used to define the different oxides.
Sapphire
3.4.1.2 Silicon on Insulator A variant of CMOS that has been available for
many years is Silicon on Insulator (SOI). As the name suggests, this is a pro-
(a)
cess where the transistors are fabricated on an insulator. SOI stands in con-
n-transistor p-transistor trast to conventional bulk processes in which the transistors are fabricated on
a conductive substrate. Two main insulators are used: SiO2 and sapphire. One
major advantage of an insulating substrate is the elimination of the capaci-
tance between the source/drain regions and body, leading to higher-speed
n+ p n+ p+ n p+ devices. Another major advantage is lower subthreshold leakage due to
Buried Silicon Oxide (BOX) steeper subthreshold slope resulting from a smaller n in EQ (2.44). The draw-
backs are time-dependent threshold variations caused by the floating body.
Substrate
Figure 3.17 shows two common types of SOI. Figure 3.17(a) illustrates
a sapphire substrate. In this technology (for example, Peregrine Semicon-
(b)
ductor’s UltraCMOS), a thin layer of silicon is formed on the sapphire sur-
FIGURE 3.17 SOI types face. The thin layer of silicon is selectively doped to define different
threshold transistors. Gate oxide is grown on top of this and then polysilicon
gates are defined. Following this, the nMOS and pMOS transistors are formed by implan-
tation. Figure 3.17(b) shows a silicon-based SOI process. Here, a silicon substrate is used
and a buried oxide (BOX) is grown on top of the silicon substrate. A thin silicon layer is
then grown on top of the buried oxide and this is selectively implanted to form nMOS and
pMOS transistor regions. Gate, source, and drain regions are then defined in a similar
fashion to a bulk process. Sapphire is optically and RF transparent. As such, it can be of
use in optoelectronic areas when merged with III-V based light emitters.
SOI devices and circuits are discussed further in Section 9.5.

3.4.1.3 High-k Gate Dielectrics MOS transistors need high gate capacitance to attract
charge to the channel. This leads to very thin SiO2 gate dielectrics (e.g., 10.5–12 Å,
merely four atomic layers, in a 65 nm process). Gate leakage increases unacceptably below
these thicknesses, which brings an end to classical scaling [Bai04]. Simple SiO2 has a
dielectric constant of k = 3.9. As shown in EQ (2.2), gates could use thicker dielectrics and
hence leak less if a material with a higher dielectric constant were available.
A first step in this direction was the introduction of nitrogen to form oxynitride gate
dielectrics, called SiON, around the 130 nm generation, providing k of about 4.1–4.2.
High-k dielectrics entered commercial manufacturing in 2007, first with a hafnium-based
material in Intel’s 45 nm process [Auth08]. Hafnium oxide (HfO2) has k = 20.
A depletion region forms at the interface of polysilicon and the gate dielectric. This
effectively increases tox, which is undesirable for performance. Moreover, polysilicon gates
can be incompatible with high-k dielectrics because of effects such as threshold voltage pin-
ning and phonon scattering, which make it difficult to obtain low thresholds and reduce the
mobility. The Intel 45 nm process returned to metal gates to solve these problems and also
to reduce gate resistance, as shown in Figure 3.18 [Mistry07]. Thus, the term MOS is