DLD LABS:

Name
Syed Muhammad Ali

CIIT/FA19-BCE-011/ISB
Registration Number

BCE-2A
Class

Instructor’s Name Mam Asma Ramay

 DLD Lab NO 6
Task no 1:
K-Map simplification:
By Hand:
By K-Map Tool:
For W:

For X:
For Y:

For Z:
Implementation By using Proteus:
Gate Level Xilinx:
Code:

Test Bench:
Output:

Behavioral Code:
Code:

Test Bench:
Output:
Post Lab :
Analysis:
Inlab Task1:
Inlab Task 2:
Critical Analysis:
After doing this lab we are now able to use Fpga by using Xilinx.
By using gate level or behavioral we create a Verilog description
of binary to gray converter. And also implement these all task
on Fpga.

DLD LAB NO 7:
IN lab TASKS:

Part 1:

Code:

HALF ADDER:

FULL ADDER:
RCA:

TEST BenCH:
Output when we have to do addition:
Output when we have to do subtraction:

Part 2:

Code:
Test bench:
Output:
 Post Lab:
For Parameter = 4:
Code:-

Test Bench:
Output when m = 1:
Output when m = 0:

For Parameter = 6:
Code:
Test Bench:
Output when m = 0:

Output when m = 1:

Part 2:
 Analysis Of critical path delay

Analysis of resource utilization:

Critical Analysis:
After doing this lab we are now able to create an adder which
can add different bits. In this lab we also come to know about
the parameters.By using parameter we make a module
parameterized in Verilog. Parameterized method will allow us to
make n-bit binary adder

DLD LAB NO 8:
Pre lab TASK:
Code:

Test Bench:
OUTPUT:
 INLAB TASK 1:
PROTEUS SIMULATION OF 4 bit by 2 bit Multiplier:
 INLAB TASK 2:

CODE:
TEST BENCH:
OUTPUT:

Post Lab:
Task 1:
Code:
When parameter = 3:
Test Bench:

Output:

When parameter = 5:
Code:
Test Bench:

Output:
Part 2:
Analysis:
By using Behavioural:
By using Structural level:
Critical Analysis:
In this lab we learned about how we can create a
multiplier.Firstly we create 4 bit by 2 bit binary multiplier on
proteus then create a 4 bit by 3 bit multiplier on Verilog. Then
we also create a behavioural model of parameterized multiplier
for n-bit.

DLD LAB NO 9;
In lab Task 1:
Table of BCD to 7-Segment Decoder:
In Lab Task 2:
Code:
Test Bench:
Output:

Post Lab:
Critical Analysis:
In this lab we have learned how to design and implement a BCD
to 7-segment decoder.By using proteus we able to understand
the structure of bcd to 7-segment decoder and then by using
Xilinx we create a code to convert BCD to 7 segment
decoder.Then we also analyse the criticsl path delay.