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Certificate: This Is To Certify That
Certificate: This Is To Certify That
CERTIFICATE
Mr./Miss. ___________________________________
Date: __________
(Semester-02)
BRANCH: ID No.
Figure:-
Figure:1 CRO
THEORY :-
Amplitude:
o What you are actually seeing are waves with different amplitudes.
o They might have the exact same frequency and wavelength, but the
amplitudes of the waves can be very different.
Figure: 2
When you measure the amplitude of a wave, you are really looking at the energy of the wave.
is, just think of a home stereo’s amplifier… it
makes the amplitude of the waves bigger by using more electrical energy.
Frequency:
When we first started looking at SHM we defined period as the amount of time it takes for
one cycle to complete... seconds per cycle
Frequency is the same sort of idea, except we‟re just going to flip things around.
Frequency is a measurement of how many cycles can happen in a certain amount of
time… cycles per second.
Since frequency and period are exact inverses of each other, there is a very
basic pair of formulas you can use to calculate one if you know the other…
Procedure:
Observation Table:-
Conclusion:-
EXPERIMENT:-2
AIM: - To study the V-I characteristics of p-n junction diode (Silicon & Germanium Diode)
and LED.
APPARATUS: - p-n junction diodes (Si, Ge),LED, Digital Multi-meter, variable resistance,
power supply, bread board, connecting wires, etc.
FIGURE:-
THEORY :-
The contact surface between the layers of p-type and n-type semiconductor pieces placed
together so as to from a p-n junction is called the P-N Junction.
When an external field with p-region connected to the +ve terminal & n-region connected to
the -ve terminal of the battery is applied across the junction , the junction is said to be
forward biased. The voltage at which current flows is called knee voltages.
When an external bias voltage is applied with positive terminal to n-side and the negative
terminal to the p-side of a p-n-junction , the junction is said to be reverse biased. It has one
limitation of breakdown voltage, at which diode has very high current.
Procedure:-
P-N junction diode (Forward bias):
(1) Take a p-n junction diode (Si, Ge) and connect the positive terminal of p-n junction diode
with the positive terminal of the battery (10V) vice versa.
(2) Connect a voltmeter in parallel with the p-n junction diode and an ammeter in series with
the same, also resistance in series.
(3) Increase slowly and steadily a voltage of a source and note down the voltmeter and
ammeter readings.
(4) Plot the graph of Voltage Vs Current for Silicon & Germanium diode with a single graph
paper. Mark the cut-in voltage for both.
LED: Connect LED as same as P-N junction diode in F.B. and measure threshold voltage.
Observation Table:
(i) Forward bias
Observation Table for Silicon Diode: Observation Table for Germanium Diode:
Conclusion:-
EXPERIMENT:- 3
APPARATUS: - Zener diode, Digital Multi-meter, variable resistance, power supply, bread
board, connecting wires, etc.
FIGURE:-
THEORY :-
Zener doide is a special diode with increased amounts of doping. This is to compensate for the
damage that occurs in the case of a pn junction diode when the reverse bias exceeds the
breakdown voltage and thereby current increases at a rapid rate. Applying a positive potential to
the anode and a negative potential to the cathode of the zener diode establishes a forward bias
condition. The forward characteristic of the zener diode is same as that of a pn junction diode i.e.
as the applied potential increases the current increases exponentially. Applying a negative
potential to the anode and positive potential to the cathode reverse biases the zener diode.
As the reverse bias increases the current increases rapidly in a direction opposite to that of the
positive voltage region. Thus under reverse bias condition breakdown occurs. It occurs because
there is a strong electric filed in the region of the junction that can disrupt the bonding forces
within the atom and generate carriers. The breakdown voltage depends upon the amount of
doping. For a heavily doped diode depletion layer will be thin and breakdown occurs at low
reverse voltage and the breakdown voltage is sharp. Whereas a lightly doped diode has a higher
breakdown voltage. This explains the zener diode characteristics in the reverse bias region. The
maximum reverse bias potential that can be applied before entering the zener region is called the
Peak Inverse Voltage referred to as PIV rating or the Peak Reverse Voltage Rating (PRV rating).
Zener diode is same as a simple P-N junction diode in forward bias condition, with adequate
power dissipation capabilities in reverse bias condition. Zener diode will regulate the variation in
load current and load voltages in the break down region. An increase in temperature increases the
energies of the valence electrons and hence makes easier for electrons to escape from their
positions in covalent bond. So, Zener break down voltages decreases with temperature.
Procedure:-
Observation Table:
Conclusion:-
EXPERIMENT:-4
Apparatus :- Probes, steps down transformer, DMM, CRO, resister, connecting wires, power
supply, p-n junction diode, etc.
Figure:
Theory:
A device which converts the ‘AC’ wave form (sinusoidal waveform) into a unidirectional
waveform (DC) is called a ‘RECTIFIER’.
In a rectifier circuit, the input vi = vm+sinωt has a peck value vm, which is very large
compare to cut-in voltage vn of the diode.
With the diode idealized to be a resistance Rf in the ON state and an open circuit in the OFF
state. The current in the diode Rl given by I =Im+sinωt, o<=α<=π, i=0, if π<=α<=2π (α=ωt).
Im=
IDC=
IDC=
Here reading of a DC voltmeter reads average voltage, diode has 2 values of resistence, Rf in
ON and α in the OFF state.
Average value of voltage,
VDC= +
= (ImRf-Vm)
VDC = =
Ripple factor:
The rectifier output consist of AC as well as DC components the ripple factor measures
percentage of AC component in rectifier output.
It indicates how close the rectified output is to the pure ideal DC voltage waveform. Small
value of ‘ripple factor’ indicates how close the rectified output wave form is, and should be
small (≈0) as possible.
Ripple factor=
r=
r=
=1.21 %
Voltage regulation:
Observation table:
1. 1
2. 2
3. 3
4. 4
5. 5
B. half-wave rectifier with filter
6. 1
7. 2
8. 3
9. 4
10. 5
Procedure:
Conclusion:
EXPERIMENT:-5-A
Aim: - To study about full-wave center tap rectifier without filter and find ripple factor
Apparatus: - Center taped transfer, probes, connecting wires, p-n junction diodes, resistance,
DMM, CRO, etc
Figure:
D1
TX1
Ls1 RL
Lp
Vin= 230V AC 50 Hz
Ls2 RL = 1k - 5k
D2
Vo/p
Theory:
Full wave rectifier consists of a step down center taped transformer T1 & purely resistive
load.
In half wave rectifier, load current flows in only one half cycles but in the full wave
rectifier, it flows in both half cycles of AC supply.
Operation in positive half cycle (0-π):
In +ve half cycle of AC supply, polarities are VA0 (+ve) & VB0 (-ve).
Due to center tapped, secondary VA0 & VB0 are equal and opposite of each other.
D1 in forward bias and D2in reverse biased the load current starts from a through D1, load
resistance RL back to the point O.
The resistance load voltage is positive & equal to VA0.
Operation in –ve half cycle(π-2π):
In –ve half cycle of the AC supply, polarities of the secondary induced voltages are shown
in fig. VA0 (-ve) & VB0 (+ve).
Hence, D2 will be forward biased & D1 is reverse biased. D2 carries the entire load current.
The direction of load current is as same as that in +ve.
The instantaneous voltage ≈ VB0.
Average load current (ILDC):
= = 2 ILDC (HWR)
= x RL
RMS voltage:
Vrms = Im / √2 x RL
= Vm / √2
Ripple factor:
= 0.48
Here, the Rf of FWR is less than HWR, so quality is much better than that of HWR.
The voltage is regulation is same as the regulation of HWR.
Procedure:
Take the center tapped transformer; connect the primary coil of the transformer to the
battery.
Connect the secondary coil with 2 diodes, D1 & D2 & load resistance RL.
Change the load resistance from 1K to 5K ohms and note the corresponding AC volts and
DC volts using DMM
Find and examine the characteristic of wave form in full wave rectifier.
Find ripple factor from each reading.
Find % of voltage variation in the rectifier.
Draw the graph of Vop→Vip.
Observation table:
1. 1
2. 2
3. 3
4. 4
5. 5
Calculation:
Conclusion:
EXPERIMENT: 5B
Aim: To study about full wave center tap rectifier with capacitor filter. Find ripple factor and
voltage regulation.
Apparatus: Full wave center tapped rectifier capacitance load resistance, battery, two diodes,
connecting wires probes, DMM etc.
Figure:
D1
C1
TX1
10uF
Ls1 RL
Lp
Vin= 230V AC 50 Hz
Ls2 RL = 1k - 5k
D2
Vo/p
Theory:
Filters are the electronic circuits used along with rectifiers in order to get a pure ripple for
DC voltage.
The filter circuits use resistors, capacitors and inductors. Therefore they are called passive
filters. Depending upon the types filters are classified as:
Capacitive I/P filter
Choke I/P filter
Lc filter
Π type filter
In the circuit of full wave rectifier with capacitor filter, capacitance ‘c’ is very large i.e. few
hundred microfarad in order to reduce ripple.
Operation of EWR with a capacitor filter
In I interval (0-A) :
The initial voltage of capacitor ‘C’=0. In 1st positive half cycle of the supply, D1 is
forward biased and start conducting D2 is reverse biased and act as open switch. D1
supplies charging current of capacitor.
Capacitor starts charging through D1 and at interval at ‘n’ charges to peak value of
secondary voltage Vm.
After point ‘A’ the secondary voltage starts reducing as shown by the dotted
waveform of rectifier O/P in fig. This will reverse bias the diode D1, hence at A,
diode D1 turn off.
Interval A to B:
During this interval voltage on the capacitor is higher than rectifier O/P. Hence D 1
and D2 both remain off. The capacitor discharges exponentially through load
resistance R1.
As the value of R1 is much higher than Rf, the capacitor discharges slowly.
Discharging time constant is ‘RLC’.C is very large in order to make discharging
constant as large as possible. This will reduce ripple content in the output voltage.
Interval B to C:
At ‘B’ the instantaneous rectified voltage is equal to the voltage or capacitor and
after ‘B’ it is greater than Vc.
Therefore, diode D2 starts conducting at instant B. the capacitor charges through D2
and at the end of the interval at point C the voltage on capacitor is against equal to
+Vm.
Due to this, D2 is reverse biased and stops conduction at point C as shown in fig.
Ripple factor:
Take the full wave rectifier (center tapped) with capacitor filter.
Arrange Rl and C parallel to each other
Apply 230 AC voltage to the circuit
Change the load resistance from 1k to 5k and examine the output characteristics voltage
from C.R.O and note that AC and DC using DMM.
Find different ripple factor for corresponding reading by Rf = VLDC / VRMS
Test the charging discharging of capacitor and the effect of capacitor filter to the O/P
characteristic of full wave rectifier
Draw the characteristic graph for FWR with a capacitor filter
Observation table:
Sr. No. R(kΩ) Vac (I/P)(V) VDC (V) Ripple Factor (2900/RLC)
1. 1 Practical Theoretical
2. 2
3. 3
4. 4
5. 5
Conclusion:
EXPERIMENT: 6
Aim: Study of the diode applications in a clipping and clamping circuits.
Apparatus: p-n junction diode (silicon), resistor, capacitor, CRO, function generator, power
supply, probes, DMM, connecting wires, etc.
Figure:
Theory:
This experiment studies the applications of the diode in the clipping & clamping operations.
1. Clipping Circuits:
The Figure (3) shows a biased clipper, for the diode to turn in the input voltage must be greater
+V, when Vm is greater than +V , the diode acts like a closed switch (ideally) & the voltage
across the output equals +V , this output stays at +V as long as the input voltage exceeds +V.
when the input voltage is less than +V , the diode opens and the circuit acts as a voltage
divider, as usual , RL should be much greater than R, in this way , most of input voltage
appears across the output. The output waveforms of Figure (3) summarize the circuit action.
The biased clipper removes all signals above the (+V) level.
2. Clamping Circuits:
A clamper does is adding a DC component to the signal. In Figure (4) the input signal is a
sinewave, the clamper pushes the signal upward, so that the negative peaks fall on the 0V level.
As can see, the shape of the original signal is preserved, all that happen is a vertical shift of the
signal. We described an output signal for a positive dampen- On the Figure (4) shown
represents a positive clamper ideally here how it is works. On the first negative half cycle of
input voltage, the diode turns on. At the negative peak, the capacitor must charge to Vp with
polarity shown. Slightly beyond the negative peak, the diode shunts off.
Procedure:
Connect the circuit as shown in fig. for each circuit, observe the output waveform.
Fix the reference voltage of 2V.
Give the input in sinusoidal waveform, having peak to peak voltage of 10 V, F=1Khz.
Sketch the input and output waveforms.
Conclusion:
EXPERIMENT: 7
Aim: To study about input & output characteristic of N-P-N transistor in Common Emitter
(CE) configuration.
Apparatus: N-P-N transistor kit with C-E configuration, connecting wires, 2 batteries etc.
Figure:
RC = 3.3K
Q1
RB=100K C
B V2
E 0-12Vdc
VCE
V1
0-12Vdc VBE IE = IB + IC
0 Emitter is common
Theory:
It is a graph of input current IBE versus input voltage VBE at a constant output voltage.
For C-E configuration, IB is the input current and VBE is the input voltage.
At constant output voltage, VCE the input characteristics of a N-P-N transistor is shown in
fig-a. The input characteristic also shows the effect of VCE.
The input characteristic resembles the forward characteristics of p-n junction diode. The
reason that BE junction is forward biased p-n junction that BE junction is forward biased
p-n junction.
The base current increases rapidly as the emitter voltage crosses the cut in voltage of the
B-E p-n junction. The dynamic input resistance is defined as
RI=∆VBE/∆IB/VCE constant
Its value can be obtained from the input characteristic because ‘R I’ is equal to the
reciprocal of slope of the input characteristic.
RI is low for C-E configuration.
Effect of change in VCE on the input characteristic:
Fig. a shows that at a constant VBE, if we increase VCE from 5v to 15v then the base
current decreases from 60µA to 20A
Thus IB decreases with increases VCE we can explain this as follows:
As VCE increases CB junction is more reverse biased
The depletion region at CB junction penetrates more into base
This reduces the electrical width of bias
The chances of recombination in the base region reduce
Hence the base current will reduce
This is a graph of output current (IC) versus output voltage (VCE) for various fixed values
of the input current (IB). The typical output characteristics of a n-p-n transistor operating
in the CE configuration are as shown in fig. b.
As shown in fig. b. there are three regions of operations namely the cut off region, active
region & saturation region.
Cut off region:
Both the BE & CB junction are reverse biased to operate the transistor in cut
off region, the base current IB=0 and the collector current is equal to the
reverse leakage current ICE the region below the characteristic for IB=0 is cut-
off region
Active region:
The B-E junction is forward biased and C-B junction is reverse biased to
operate the transistor in the active region
The collector current IC increases slightly with increase in the voltage VCE.
However the collector current is largely dependent on the base current IB
The collector current IC increases slightly with increase in the voltage VCE.
However the collector current is dependent on IB
At a fixed value of VCE, if IB is increased, then it will cause IC to increase
substantially.
Saturation region:
The B-E junction as well as the collector junction must be forward biased to
operate the transistor in its saturation region.
The collector base junction can be forward biased if and only if VCE drops
down to about 0-2 volts because VBE=0.1 v will forward bias the CB junction.
The collector current increases rapidly with increase in VCE.
The collector current increases rapidly with increase in VCE.
The transistor is operated as a switch in this region.
Dynamic output resistance(R):-
Observation Table:
1) Input Characteristics:
Vcc = 10 V RB = _____________
2) Output Characteristics:
IB = 0 IB = 40µA
VCE VRC IC = VBE VCE VRC IC = VBE
VRC/RC VRC/RC
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
1.5
Procedure:
Figure:
+VCC 12V
RL = 33k
R2
Q1
R3
Theory:
The circuit used to establish a stable operating point is the self biasing (voltage divider)
ckt.
As shown in fig. R1 &R2 are potential divider to apply a fixed voltage Vg to base.
The current in Rc in the emitter lead causes a voltage drop which is in the direction to
reverse bias the emitter junction.
The junction must be forward biased .The biased voltage is obtained from the supply
voltage.
Here Ic tends to increase because IC0 has risen in Rc increases, so voltage drop across
Rc increase , which increases voltage drop across Rc the base current decreases .Thus
tends to decrease in Ic & compensation For in Ic achieved.
Analysis using Thevenin’s equivalent Circuit:
RC
Q1
RB=R1/R2
RE
VTH
0 0
RB=(R1*R2) / (R1+R2)
Vth=(R2*Vcc) / (R1+R2)
Obtain Expression for Ib:
Q1
RB
RE
VTH
Vth-IB.RB-VBE-IE.RE=0
Vth-IB.RB-VBE-(Hβdc).IBRE=0.
IB=(Vth-VBE)/RB+(Hβdc)RE
IC=βdc*IB
=βdc(Vth-VBE)/RB+(1+βdc).RE
RC
Q1 VDC
RE
VCC=ICRC+VCE+IERE
Procedure:
As shown in fig take n-p-n junction diode and connect 2 diodes (R1=variables and
R2=1kΩ) in base emitter circuit junction.
Connect Rc=3.3kΩ collector emitter junction.
Apply biasing voltage Vcc=12v.
Here, output voltage VCE is measured.
For setting quiescent point in the middle we assume that VCE=VCC/2, so very R1 and
find VCE.
Continue above procedure until output is VCE=Vcc/2.
Conclusion:
EXPERIMENT: 9
Aim: To study the frequency response of the C-E amplifier and find its bandwidth.
Apparatus: C-E amplifier, NPN (BJT), CRO, connecting wires , probes , DMM etc.
Figure:
Theory:
C-E amplifier:
Av = 1 / (1 + j(f/f2))
For common emitter, high frequency equivalent model for the network is appeared. By
Thervenin equivalent circuit for the input and output networks of fig. results in the
configuration.
fth = 1/(2 * π * Rth * Ci)
Rth = Rs || R1 || R2 || R
Ci = Cwi + Cbe + Cmi
= Cw + Cbe + (1 - Av) Cp
At a very high frequency, Ci`s effect is reduced to total impedance of the parallel
combination R1, R2, Ri and Ci.
fTH0= 1/ (2 * π * Rth0 * C0)
Rth0 = Rc || RL || R0
C0= Cw0+ Ccl + Cmo
Observation table:
Vin = 20 mV = VP
Procedure:
Circuit Diagram:
Theory:
In the RC Oscillator tutorial we saw that a number of resistors and capacitors can be
connected together with an inverting amplifier to produce an oscillating circuit.
One of the simplest sine wave oscillators which use a RC network in place of the
conventional LC tuned tank circuit to produce a sinusoidal output waveform is called a Wien
Bridge Oscillator.
The Wien Bridge Oscillator is so called because the circuit is based on a frequency-selective
form of the Wheatstone bridge circuit. The Wien Bridge oscillator is a two-stage RC coupled
amplifier circuit that has good stability at its resonant frequency, low distortion and is very
easy to tune making it a popular circuit as an audio frequency oscillator but the phase shift of
the output signal is considerably different from the previous phase shift RC Oscillator.
The Wien Bridge Oscillator uses a feedback circuit consisting of a series RC circuit
connected with a parallel RC of the same component values producing a phase delay or phase
advance circuit depending upon the frequency. At the resonant frequency ƒr the phase shift is
0o. Consider the circuit below.
RC Phase Shift Network
Procedure:
Observation Table:
Sr. No
Capacitance (nF) Theoretical Practical frequency
frequency (Khz) (Khz)
1
2
3
Calculation:
Conclusion:
EXPERIMENT: 11
Aim: To study op-amp as a Inverting and Non-Inverting amplifier circuit.
Circuit Diagram:
Non-inverting Amplifier :
Theory:
Procedure:
Observation Table:
1
2
3
1
2
3
Calculation:
Theoretically:
Vo= Av*Vin
Vo= (1+Rf/R2) Vin (Non-inverting Amplifier)
Vo= (- Rf/Rin) Vin (Inverting Amplifier)
Practically:
Conclusion: