REPUBLIC OF THE PHILIPPINES

DON MARIANO MARCOS MEMORIAL STATE UNIVERSITY

MID – LA UNION CAMPUS
CITY OF SAN FERNANDO, LA UNION

COLLEGE OF ENGINEERING
DEPARTMENT OF ELECTRICAL ENGINEERING

LOGIC CIRCUIT & SWITCHING THEORY

SEQUENCIAL LOGIC CIRCUITS

PRESENTED TO THE FACULTY OF THE COLLEGE OF ENGINEERING

BACHELOR OF SCIENCE IN ELECTRICAL ENGINEERING

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR LOGIC CIRCUITS & SWITCHING THEORY (ECE142)

MIKEE B. DOCTOLERO (#11) MARVIN L. JAVIER (#18)

APRILYN MAE L. DUMO (#12)
RINO S. FREGILLANA (#14)
JAY-AR G. GACAYAN (#15)
RENZ PETERSON G. GAPUSAN (#16)
SHERRYLY V. GATCHALIAN (#17)
ROLDAN D. JIMINO (#19)
CHRISTIAN JAY R. LIM (#21)
BRYAN JUSTIN A. MALINAO (#22)
PETER PAUL N. MARQUEZ (#23)

MAY 29, 2020

Sequential Logic Circuits
A sequential circuit is the assimilation of a combinational logic circuit and a storage
element. With the applied inputs to the combinational logic, the circuit outputs are derived.
These sequential circuits deliver the output based on both the current and previously stored
input variables. The derived output is passed on to the next clock cycle. Sequential circuits
consist of memory devices to store binary data. This binary information describes the current
state of the sequential circuit. As sequential circuits work along with the combinational circuit,
there are two types of combinational logic inputs where those are.
Types of Sequential Circuits
Here comes the discussion on the types of sequential circuits. These are of mainly two types
and are discussed below:
1. Synchronous Sequential Circuits
2. Asynchronous Sequential Circuits
1). Synchronous Sequential Circuits
Synchronous sequential circuits use level inputs and clock signals as the circuit inputs
having limitations on the circuit propagation time and pulse width to generate the output. The
duration of the output pulse is like the clock pulse of the clocked circuits. Level output modified
its state at the beginning of an input pulse and continues in that until the next clock pulse
arrives. Until the arrival of the next pulse, these circuits perform no activity and so the
operation is a bit slower than that of asynchronous circuits. Again, synchronous circuits are of
two types clocked and un-clocked.

Synchronous Sequential Circuit

A). Clocked Sequential Circuit

Clocked circuits use flip-flops and gated latches as the memory elements. The operation
of the circuit is operated by the periodic clock pulses where these are connected to the clock
inputs to synchronize all the internal modifications of the state.

Clocked Sequential Circuit

b). Unclocked Sequential Circuit

 These circuits do not require any clock. The internal changes of the state are based on
the pulse transitions between 0-pulse and 1 -pulse. This is designed to act in response to the
pulses of specific time; the periodic signals in between the null and spacer signals.

Unclocke
d Sequential Circuit

Applications
Synchronous sequential circuits are implemented in the design of flip-flops, counters
and to develop MOORE-MEALY state-controlled machines.
2). Asynchronous Sequential Circuits
Asynchronous sequential circuits perform their operation without depending on the
clock signal but use the input pulses and generate the output. As there is no clock pulse
dependency, these circuits can switch to the next state quickly when the input signal is
changed. So, there is a faster operation with asynchronous sequential circuits.

Asynchronous Sequential Circuit

Applications
Asynchronous sequential circuits are cost-effective to be used in small independent
systems that need only a few elements. The communication between two elements, each hold
its own independent clock, and this will be achieved by these circuits.
The defining characteristic of a combinational circuit is that its output depends only on
the current inputs applied to the circuit. The output of a sequential circuit, on the other hand,
depends both on the current input values as well as the past inputs. This dependence on past
inputs gives the property of “memory” for sequential circuits.
In general, the sequence of past inputs is encoded into a set of state variables. There is a
feedback path that feeds these variables to the input of a combinational circuit as shown in
Figure 4.1. Sometimes, this feedback consists of a simple interconnection of some outputs of
the combinational circuit to its inputs. For the most part, however, the feedback circuit consists
of elements such as flip-flops that we discuss later in this chapter. These elements themselves
are sequential circuits that can remember or store the state information. Once we introduce
feedback, we also introduce potential instability into the system. As a simple example, consider
the circuit shown in Figure 4.2. This circuit is stable in the sense that the output of each inverter
can stay at a particular level. However, this circuit is in deterministic as we cannot say what the
output level of each inverter is. Outputs of the first and second inverters could be 0 and 1,
respectively. The outputs could also be 1 and 0, instead. In contrast, you can verify that the
circuit in Figure 4.2 is unstable.
In combinational logic circuits the output levels at any instant are dependent purely on
the levels present at the input at that time. In sequential logic circuits the output levels are
dependent also on the previous states, and include some form of memory elements. The
most widely used memory element is the flip-flop.
The RS Flip-flop A simple RS bi stable may not be constructed using two NOR gates
interconnected as shown in Fig. 14.1. As may be seen from the truth table, when both inputs
are low, the Q-output is stable in whichever state it was at previously. Pulsing the Sin put high
sets the Q output low and the Q output high. Pulsing the R input has just the opposite effect.
However, when both inputs go from high to low together then the output state is
unpredictable.

Fig. 14.1 A simple RS flip-flop

The simple RS flip-flop has two disadvantages for certain applications: (a) its operation
out of the 1, 1 state is unpredictable. (b) It is transparent (i.e. when enabled, the output
changes whenever the input changes).
The JK Flip-flop as shown in Fig. 14.2 overcomes both of these difficulties. As well as
having I and K inputs, it has the addition of a clock. As may be seen from the truth table, the 1,
1 state, rather than being unpredictable, causes the flip-flop to toggle, such that, on receipt of a
clock input, the output changes to the opposite state. JK flip-flops are available with preset and
clear inputs. This provides a means of setting the flip-flop into a known condition independent
of the clock and the JK inputs. There are two ways in which the clock input may be arranged to
control the transitions. These are described in (c) and (d).
 Edge-triggered Flip-flops In this case, one edge is used to define the time at which the
output changes. Either the rising or the falling edge may be used, depending on the device. The
JK inputs must be present for a minimum time (the set-up time) before the clock edge occurs,
and remain for a minimum time (the hold time) after the clock edge. The output will be delayed
for a period of time after the clock edge (the propagation delay).
Pulse-triggered Flip-flops In this case the device is pulse-triggered. It is referred to as the
master-slave flip flop. Its operation may be understood by considering the two edge-triggered
flip-flops in series as shown in Fig. 14.3, although it is not necessarily made in this way. On the
rising edge of the clock, data enters the first flip-flop. On the falling edge, data is transferred to
the output. At no time is the input connected through to the output, and feedback oscillations
are impossible. The edge-triggered and master-slave flip-flops operate by clock levels, and are
not dependent on the clock edge speed.

SR Flip-flop circuit:
A flip-flop is a sequential circuit which samples the input and changes the output at a
particular instance of time. It has two stable states and can be used to store the state
information. Signals are applied to one or more control inputs to change the state of the circuit
and will have one or two outputs.
It is the basic storage element in sequential logic and fundamental building blocks of
digital electronic systems. They can be used to keep a record of the value of a variable. Flip-flop
is also used to control the functionality of a circuit.

Master-slave JK flip-flop:
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected
together in a series configuration. Out of these, one acts as the “master” and the other as a
“slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop
whose output is fed back to inputs of the master flip flop.
 In addition to these two flip-flops, the circuit also includes an inverter. The inverter is
connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-
flop. In other words, if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for
master flip flop then it becomes 0 for slave flip flop.
Prerequisite – Flip-flop types and their Conversion
Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a long period
of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race around condition in J-K flip-flop. This problem
(Race around Condition) can be avoided by ensuring that the clock input is at logic “1” only for a
very short time. This introduced the concept of Master Slave JK flip flop.
Master Slave flip flop are the cascaded combination of two flip-flops among which the
first is designated as master flip-flop while the next is called slave flip-flop (Figure 1). Here the
master flip-flop is triggered by the external clock pulse train while the slave is activated at its
inversion i.e. if the master is positive edge-triggered, then the slave is negative-edge triggered
and vice-versa. This means that the data enters into the flip-flop at leading/trailing edge of the
clock pulse while it is obtained at the output pins during trailing/leading edge of the clock pulse.
Hence a master-slave flip-flop completes its operation only after the appearance of one full
cloclock pulse for which they are also known pulse-triggered flip-flops.
 The internal structure of a master-slave JK flip-flop in terms of NAND gates and an inverter (to
complement the clock signal) is shown in Figure 2. Here it is seen that the NAND gate 1 (N1) has three
inputs viz., external clock pulse (Clock), input J and output Q̅ ; while the NAND gate 2 (N 2) has external
clock pulse (Clock), input K and output Q as its inputs.
Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross
connected gates N3 and N4. These four gates together (N1, N2, N3 and N4) form the master-part
of the flip-flop while a similar arrangement of the other four gates N 5, N6, N7 and N8 form the
slave-part of it.

From figure it is also evident that the slave is driven by the outputs of the master (M 1
and M2), which is in accordance with its name master-slave flip-flop. Further the master is
active during the positive edge of the clock due to which M 1 and M2 change their states;
depending on the values of J and K. However at this instant the outputs of the overall system
(master-slave JK flip-flop) remains unchanged as the slave will be inactive due to positive-edge
of the clock pulse. Similar to this, the slave decides on its outputs Q and Q̅ depending on its
inputs M1 and M2, during the negative edge of the clock during which the master will be
inactive.
The truth table corresponding to the working of the flip-flop shown in Figure 2 is given
by Table I. Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in
red boxes) appear during the positive-edge of the clock (red arrow). However at this instant the
slave-outputs remain latched or unchanged. The same data is transferred to the output pins of
the master-slave flip-flop (data enclosed in blue boxes) by the slave during the negative edge of
the clock pulse (blue arrow). The same principle is further emphasized in the timing diagram of
master-slave flip-flop shown by Figure 3. Here the green arrows are used to indicate that the
slave-output is nothing but the master-output delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave flip-flop is
analogous to that of the master slave JK flip-flop explained here.
Delay Flip-flop:
We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and one to
“RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and “RESET”
the flip-flop using just one input as now the two input signals are complements of each other. This
complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since that state is
no longer possible.
Thus this single input is called the “DATA” input. If this data input is held HIGH the flip
flop would be “SET” and when it is LOW the flip flop would change and become “RESET”.
However, this would be rather pointless since the output of the flip flop would always change
on every pulse applied to this data input.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate
the data input from the flip flop’s latching circuitry after the desired data has been stored. The
effect is that D input condition is only copied to the output Q when the clock input is active.
This then forms the basis of another sequential device called D Flip Flop.
The “D flip flop” will store and output whatever logic level is applied to its data terminal
so long as the clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs
of the flip-flop are both held at logic level “1” so it will not change state and store whatever
data was present on its output before the clock transition occurred. In other words the output
is “latched” at either logic “0” or logic “1”.
 D-type Flip-Flop Circuit

Truth Table for the D-type Flip Flop

Clock Circuits:
Clock and Timing Signals
Most sequential logic circuits are driven by a clock oscillator. This usually consists of an
as table circuit producing regular pulses that should ideally:

1. be constant in frequency
Many clock oscillators use a crystal to control the frequency. Because crystal oscillators
generate normally high frequencies, where lower frequencies are required the original
oscillator frequency is divided down from a very high frequency to a lower one using counter
circuits.
2. Have fast rising and falling edges to its pulses.
It is the edges of the pulses that are important in timing the operation of many
sequential circuits, the rise and fall times are usually be less than 100ns. The outputs of clock
circuits will typically have to drive more gate than any other output in a given system. To
prevent this load distorting the clock signal, it is usual for clock oscillator outputs to be fed via a
buffer amplifier.
3. Have the correct logic levels
The signals produced by the clock circuits must have appropriate the logic levels for the
circuits being supplied.

Simple Clock oscillator

 Fig 5.1.1 is probably the simplest oscillator possible, having only three components.
Notice that the gate is a Schmitt inverter. This device has an extremely fast change over
between logic states. Also the level at which it responds to an input change from 0 to 1 (Vt+) is
higher than the level at which it changes from 1 to 0 (Vt-). The operation of the circuit is as
follows.

Fig. 5.1.1 Simple Schmitt Inverter Clock Oscillator

Suppose the gate input is at logic 0, because the gate is an inverter, the output must be
at logic 1, and C will therefore charge up via R from the output. This will happen with the
normal CR charging curve. Once Vt+ is reached at the gate input, the gate output will rapidly
switch to 0. The resistor is now connected effectively between the positive plate of C and zero
volts. Thus the capacitor now discharges via R until the gate input voltage reduces to Vt- when
the output will change to logic 1 once more, starting the charging and discharging cycle over
again.
This Schmitt RC oscillator can produce a pulse waveform with an excellent wave shape
and very fast rise and fall times. The mark to space ratio, as shown in Fig 5.1.2 is approximately
1:3.
The frequency of oscillation depends on the time constant of R and C, but is also
affected by the characteristics of the logic family used. For the 74HC14 the frequency (ƒ) is
calculated by:
1
f=
0.8 RC

Fig. 5.1.2 Typical Basic Schmitt Oscillator Output

 When using the 74HCT14 the 0.8 correction factor is replaced by 0.67, however either of
these formulae will give an approximate frequency. Whichever logic family is used, the
frequency will vary with changes in supply voltage. Although this basic oscillator gives an
excellent performance in many simple applications, if a stable frequency is an important factor
in the choice of clock oscillator, there are of course better options.

Crystal Controlled Clock Oscillator

Fig. 5.1.3 uses three gates from a 74HCT04 IC, and a crystal to provide an accurate
frequency of oscillation. Here, the oscillator is running at 3.276MHz but this can be reduced by
dividing the output frequency down to a lower value by dividing it by 2 a number of times using
a series of flip-flops.
The top waveform in Fig 5.1.4 shows the clock signal generated by Fig 5.1.3, and
beneath it is the clock signal frequency divided by 4 after passing it through two flip-flops.
Notice that after passing the signal through flip-flops, as well as being reduced in frequency, the
wave shape is considerably squarer and now has a 1:1 mark to space ratio.

Fig. 5.1.3 Crystal Controlled Clock Oscillator

Fig. 5.1.4 Clock Frequency Divided by 4

CMOS Flip Flops:
CMOS Transmissions Gates
The flip-flops described so far in this module have been based on TTL technology,
however many modern devices such as the 74HC and 74HCT series are CMOS ICs, which have
radically different internal structures. The flip flops in CMOS ICs depend on a different type of
gate, called a ‘Transmission Gate’ or ‘Bi-lateral Switch’, which make it possible to construct bi-
stable flip-flops using less space within the IC, and have simpler structures than those used in
TTL ICs.
Fig. 5.5.1(a) illustrates the basic structure of a transmission gate, which in some ways
operates in a similar way to an electro-mechanical relay switch, except that it is much faster
and very much smaller.
Like a relay, once it is energized, information can flow through the switch in either
direction, therefore the signal terminals are dual purpose and can be labeled in/out and out/in.
In a transmission gate this is because the signal path is via two metal oxide silicon (MOS)
transistors, one of which is PMOS and the other is NMOS, connected in parallel. Signals, either
digital or analogue, can pass between source and drain of these transistors in either direction
when they are made to conduct by placing an appropriate voltage on the gate terminal of each
transistor.
The switching signal in digital circuits is provided by the clock pulses CK and CK. When
the CK pulse is applied to the gate of the NMOS transistor and the CK to the PMOS transistor
gate, the signal channel between the input and output terminal will conduct, and have a typical
resistance of about 125O. In the absence of these pulse voltages however, or if they are
reversed, with CK applied to the PMOS gate and CK applied to the NMOS gate, the conduction
channel will exhibit an extremely high impedance (1 x 1012Ω), virtually open circuit.

Fig. 5.5.1 The CMOS Transmission Gate

CMOS Flip-Flop
Fig 5.5.2 shows a basic circuit for a single flip-flop, which operates as a level triggered D
Type flip-flop. Apart from the NOT gate (N1) and the buffer (B1) controlling the CK input, the
basic flip-flop uses only two NOT gates (N2 and N3) and two transmission gates (TG1 and TG2).
 Fig. 5.5.2 Basic CMOS Flip-flop Circuit

CMOS Flip-flop Operation

The inverter N1 and the Buffer B1 create clock pulses CK and inverted clock pulses, CK
which (because N1 and B1 have identical propagation delays), will exactly coincide in time when
applied to the transmission gates of the flip-flop circuit.
Initially, assuming that the CK and D are both at logic 0, CK will be at logic 1, so
transmission gate TG1 will be in its high impedance state, preventing D from having any effect
upon the flip-flop.
When CK is logic 1 and CK is logic 0, TG1 will conduct and the logic 0 from D will be
inverted by N2, so the output Q will become logic 1. The logic 1 at Q will be inverted by N3 to
become logic 0 at the Q output.
The logic 1 at Q will not affect the logic 0 at the input to N2 as TG2, connected in
opposite polarity to the CK and CK clock signals will be turned off. This condition will remain
stable irrespective of any further clock pulses being applied, as whenever TG1 is turned on, TG2
is turned off.
If input D is now changed to logic 1 between the occurrence of clock pulses, the rising
edge of the first clock pulse after the change at D will turn on TG1, transmitting the logic 1 from
D to the input of N2, causing Q to change to logic 1 and (via N3) Q to change to logic 0.
Whilst the CK input is high, any changes at D will be transmitted via TG1 and N2 to the
outputs, indicating that the flip-flop is level triggered, but the moment the falling edge of the
clock pulse occurs, TG1 will turn off and TG2 will turn on, isolating N1 and N2 from any further
changes at the D input and leaving the output of N3 connected via TG2 to the input of N1.
As both these points will be at the same logic state (the logic state existing at D before
the falling edge of the CK pulse) the flip-flop outputs will remain in a stable mode until the next
clock pulse, when Q will take up the same state as input D once more.

CMOS D Type Flip-flop with SET and RESET

Fig. 5.5.4 shows how a CMOS D Type master slave flip-flop may be modified to
include Sand R inputs. In this version, NAND gates have replaced the inverters used in the
master and slave flip-flops in Fig 5.5.3.
When logic 0 is applied to the S input, G3 output (and Q) is set to logic 1, (as a NAND
gate output can only be logic 0 when all of its inputs are at logic 1).
Making S logic 0 also disables both the master and slave flip-flops by forcing both G3
and G2 outputs to logic 1. Therefore neither the clock nor the D inputs will have any effect on
the Q and Q outputs whilst S is low.The RESET input (R) works in the same way, by forcing the
NAND gates G1 and G4 to have logic 1 outputs.
 Fig. 5.5.4 CMOS Positive Edge Triggered D Type Flip-flop with SET and RESET

The CMOS JK Flip-flop

Converting the D Type flip-flop shown in Fig. 5.5.4 into the fully featured JK Flip-flop
shown in Fig 5.5.5 is a simple matter of adding positive feedback lines from the Q and Q outputs
to the two J and K input gates of the feedback steering circuit, which is simply a modified
version of the basic data select circuit.

Fig. 5.5.5 CMOS Positive Edge Triggered JK Flip-flop with SET and RESET

Counters:
Asynchronous Counters
Counters, consisting of a number of flip-flops, count a stream of pulses applied to the
counter’s CK input. The output is a binary value whose value is equal to the number of pulses
received at the CK input.
Each output represents one bit of the output word, which, in 74 series counter ICs is
usually 4 bits long, and the size of the output word depends on the number of flip-flops that
make up the counter. The output lines of a 4-bit counter represent the values 2 0, 21, 22 and 23,
or 1, 2, 4 and 8 respectively. They are normally shown in schematic diagrams in reverse order,
with the least significant bit at the left, this is to enable the schematic diagram to show the
circuit following the convention that signals flow from left to right, therefore in this case the CK
input is at the left.

Four Bit Asynchronous Up Counter

Fig. 5.6.1 shows a 4 bit asynchronous up counter built from four positive edge triggered
D type flip-flops connected in toggle mode. Clock pulses are fed into the CK input of FF0 whose
output, Q0 provides the 20 output for FF1 after one CK pulse.
The rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half
the frequency of the CK pulses applied to its input.
The Q outputs then represent a four-bit binary count with Q 0 to Q3 representing 20 (1) to
23 (8) respectively.
Assuming that the four Q outputs are initially at 0000, the rising edge of the first CK
pulse applied will cause the output Q0 to go to logic 1, and the next CK pulse will make
Q0 output return to logic 0, and at the same time Q0 will go from 0 to 1.
As Q0 (and the CK input of FF1 goes high) this will now make Q 1 high, indicating a value of
21 (210) on the Q outputs.
The next (third) CK pulse will cause Q 0 to go to logic 1 again, so both Q 0 and Q1 will now
be high, making the 4-bit output 11002 (310 remembering that Q0 is the least significant bit).
The fourth CK pulse will make both Q 0 and Q1 return to 0 and as Q1 will go high at this time, this
will toggle FF2, making Q2 high and indicating 00102 (410) at the outputs.
Reading the output word from right to left, the Q outputs therefore continue to
represent a binary number equaling the number of input pulses received at the CK input of FF0.
As this is a four-stage counter the flip-flops will continue to toggle in sequence and the four Q
outputs will output a sequence of binary values from 0000 2 to 11112 (0 to 1510) before the
output returns to 00002 and begins to count up again as illustrated by the waveforms in Fig
5.6.2.

Four Bit Asynchronous Down Center

To convert the up counter in Fig. 5.6.1 to count DOWN instead, is simply a matter of
modifying the connections between the flip-flops. By taking both the output lines and the CK
pulse for the next flip-flop in sequence from the Q output as shown in Fig. 5.6.3, a positive edge
triggered counter will count down from 11112 to 00002.
Although both up and down counters can be built, using the asynchronous method for
propagating the clock, they are not widely used as counters as they become unreliable at high
clock speeds, or when a large number of flip-flops are connected together to give larger counts,
due to the clock ripple effect.

Clock Ripple
The effect of clock ripple in asynchronous counters is illustrated in Fig. 5.6.4, which is a
magnified section (pulse 8) of Fig. 5.6.2.
Fig. 5.6.4 shows how the propagation delays created by the gates in each flip-flop
(indicated by the blue vertical lines) add, over a number of flip-flops, to form a significant
amount of delay between the time at which the output changes at the first flip flop (the least
significant bit), and the last flip flop (the most significant bit).
As the Q0 to Q3 outputs each change at different times, a number of different output
states occur as any particular clock pulse causes a new value to appear at the outputs.At CK
pulse 8 for example, the outputs Q0 to Q3 should change from 11102 (710) to 00012 (810),
however what really happens (reading the vertical columns of 1s and 0s in Fig. 5.6.4) is that the
outputs change, over a period of around 400 to 700ns, in the following sequence:

 11102 = 710
 01102 = 610
 00102 = 410
 00002 = 010
 00012 = 810

At CK pulses other that pulse 8 of course, different sequences will occur, therefore there
will be periods, as a change of value ripples through the chain of flip-flops, when unexpected
values appear at the Q outputs for a very short time. However this can cause problems when a
particular binary value is to be selected, as in the case of a decade counter, which must count
from 00002 to 10012 (910) and then reset to 00002 on a count of 10102 (1010).
These short-lived logic values will also because a series of very short spikes on the Q
outputs, as the propagation delay of a single flip-flop is only about 100 to 150ns. These spikes
are called ‘runt spikes’ and although they may not all reach to full logic 1 value every time, as
well as possibly causing false counter triggering, they must also be considered as a possible
cause of interference to other parts of the circuit.
Although this problem prevents the circuit being used as a reliable counter, it is still
valuable as a simple and effective frequency divider, where a high frequency oscillator provides
the input and each flip-flop in the chain divides the frequency by two.

Fig. 5.6.1 Four-bit Asynchronous Up Counter

 Fig. 5.6.2 Four-bit Asynchronous Up Counter Waveforms

Fig. 5.6.3 Four-bit Asynchronous Down Counter

Fig.5.6.4 Timing Diagram Detail Showing Clock Ripple

Registers:
Parallel In - Parallel Out (PIPO) Registers
An electronic register is a form of memory that uses a series of flip-flops to store the
individual bits of a binary word, such as a byte (8 bits) of data. The length of the stored binary
word depends on the number of flip-flops that make up the register. A simple 4-bit register is
illustrated in Fig. 5.7.1 and consists of four D Type flip-flops, sharing a common clock input,
providing synchronous operation ensuring all bits are stored at exactly the same time.
The binary word to be stored is applied to the four D inputs and is remembered by the
flip-flops at the rising edge of the next clock (CK) pulse. The stored data can then be read from
the Q outputs at any time, as long as power is maintained, or until a change of data on the D
inputs is stored by a further clock pulse, which overwrites the previous data.
 Fig. 5.7.1 Parallel In/Parallel Out (PIPO) Register
Shift Registers
Shift registers have a similar structure to the PIPO register but have the added ability to
shift the stored binary word left or right, one bit at a time. This makes them extremely useful
for many applications. They are used in handling serial data and converting it to parallel form or
back again to serial form, and therefore are an essential component in communication systems.
Shift registers are also essential in arithmetic circuits where binary numbers may be shifted
right (and so divided by two), or left (multiplied by two) as part of a calculation. Shift registers
can be used to delay the passage of data at a particular point in a circuit. As the data is shifted
one bit at a time from input to output, the amount of delay will depend on the number of flip-
flops in the register and the frequency of the clock pulses driving the shift register. Because a
number of serial bits of data are stored as they enter the input, and are then recovered from
the output at some later time, this action can also be described as a serial memory, or as a
digital delay line.
The simple storage register shown in Fig. 5.7.1 can be modified to a shift register by
connecting the output of one flip-flop into the input of the next, as shown in Fig. 5.7.2. The
basis of shift register circuits is the D-type flip-flop, but the clocked SR or the JK flip-flop may
also be converted to D-types by the inclusion of an inverter between S and R or between J and
K. In all cases the clock input is in synchronous mode.
The serial input of the shift register in Fig. 5.7.2 is the D input of the first flip-flop, and
the serial output is the Q output of the last flip-flop in the chain. The logic state at the serial
input appears at the output, a number of clock pulses (equal to the number of flip flops) later.

Fig. 5.7.2 Serial In/Serial Out (SISO) Shift Register

SIPO
In Fig. 5.7.4 the shift register is modified to include additional Q outputs from each flip-
flop, so allowing the register to input serial data, and output it in both serial and parallel form.
The register could therefore now be called a ‘Serial In/Serial Out and Serial In/Parallel Out’
(SISO/SIPO) register. This format is the basis for converting serial data to parallel data.

Fig. 5.7.4 Serial In/Parallel out (SISO/SIPO) Shift Register

PISO
If use is also made of the Q output, and the additional pre-set (PR) and clear (CLR) inputs
available on many flip-flops, the shift register could be made more versatile still.
Fig. 5.7.5 shows a shift register modified to enable it to be loaded with a 4-bit parallel
number, which may then be shifted right to appear at the serial output one bit at a time. As the
‘Parallel In/Serial Out’ or PISO register also has a serial input, it can also be used as a SISO
register, and if extra outputs from each Q output were also included, the register would also
have Serial In/Parallel out (SIPO) operation.

Fig. 5.7.5 Multiple Mode (SISO, SIPO, PISO, PIPO) Shift Register

Loading Parallel Data

If the LOAD input is taken to logic 0, the LOAD control line connected to the four pairs of
NAND gates associated with the four flip-flops will be at logic 1, and all four pairs of NAND gates
will be enabled. Therefore a logic 1 appearing on any of the D inputs will be inverted by the
NOT gate connected to the D input, making the inputs to the left hand NAND gate of the
relevant pair of gates, logic 1 and logic 0. This will cause logic 1 to be applied to the CLR input of
the flip-flop.
 The right hand NAND gate of the pair will have both inputs at logic 1, due to the logic 1
on LOAD line and logic 1 on the D input, and so will output logic 0 (NAND gate rules) to
the PR input of the flip-flop, setting the Q output to logic 1.
If the D input is at logic 0, the left hand gate of the NAND gate pair will output logic 0
and the right hand NAND gate will output logic 1, causing the CLR input to clear the Q output of
the relevant flip-flop to logic 0.
Notice that as JK flip-flops are being used in this design, a NOT gate is connected
between J and K of the first flip-flop of the chain to make the JK flip-flop mimic a D Type. The
remaining flip-flops of the shift register have J and K connected to the previous Q and Q outputs
so will also be at opposite logic states.

A 4-bit reversible shift registers

The shift register in Fig 5.7.5 could be operated as:
 A parallel in/parallel out register. (PIPO)
 A Serial in/serial out register. (SISO)
 A serial in/parallel out register. (SIPO)
 A parallel in/serial out register. (PISO)
However Fig 5.7.5 can only shift data in one direction i.e. left to right. To be truly
versatile it could be an advantage to be able to shift data in both directions and in any of the
four shift register operating modes. Fig. 5.7.6 achieves this by adding data steering circuitry.
The gating arrangement at the bottom of Fig 5.7.6 (gates G1 to G13) is exactly the same as that
described above in Fig. 5.7.5 and these gates control the loading of parallel data.
Gates G14 to G28 in Fig 5.7.6 control the direction of data flow through the register. The
JK flip-flops use the inverter gates G29 to G32 to ensure that J and K are at opposite logic states,
so the flip-flops are mimicking D Type operation, with J being used as the data input. Notice
also that the clock is connected in the familiar synchronous mode.

Fig. 5.7.6 4-Bit Reversible PIPO/PISO/SISO/SIPO Shift Register

Operation
In any of the modes involving serial operation, data may be shifted left or shifted right by the
application of a suitable logic level at the shift control (R/L) input.
With a logic 1 at this input the register is in the shift right mode, and data is taken into the
‘Serial in R’ input to be shifted right by application of successive clock pulses, appearing as
parallel data, changing with each clock pulse, on the flip flop Q outputs. After four clock pulses
the data begins to appear in serial form on the Q3 output, which is also the ‘Serial Out R’ output.
The logic 1 on the shift control (R/L) enables gates G18, 20, 22 & 24, but because the
logic 1 is inverted by G27, gates G19, 21, 23 & 25 is disabled.
The path of serial data (e.g. logic 1) from left to right is as follows; the logic 1 appearing at the
input to G26 is inverted and passes through G18 which re-inverts it to logic 1 and, as G19 is
disabled its output must also be at logic 1. Both inputs to the AND gate G14 are at logic 1 and
therefore so is its output, (AND gate rules) making the J input of FF0 logic 1.
On the arrival of a clock pulse, the logic 1 input to FF0 will appear on the output Q 0. Its
inverse (logic 0) will also appear on the Q output of FF0. This logic 0 forms the input to the next
multiplexer arrangement, gates G20, 21 & 15. As G20 is enabled (and G21 disabled) the logic 0
becomes logic 1 at G15 output and so is fed to the J input of FF1. This method is used to
transfer data to each flip-flop in the chain.
To achieve shift left operation, the shift control (R/L) is set to logic 0 and so enables
gates G19, 21, 23 & 25 while disabling gates G18, 20, 22 & 24. Therefore the Q output of FF3 is
connected via G23 and G16 to the D input of FF2, the Q output of FF2 is connected to the J
input of FF1 via G21 and G15 (remember that G24 is disabled, so FF3 is isolated from this path).
Finally, the Q output of FF1 is connected via G19 and G14 to the J input of FF0, the Q 0 output of
which is also the ‘Serial Out L’ output. The ability to shift data in either direction, together with
the parallel input and output facilities make this register a very versatile device.

A Simple ALU:
Connecting Digital Circuits Together
Digital Electronics Modules 2 to 5 have described how basic logic gates may be
combined, not only to perform standard logic functions, but to build circuits that can perform
complex logic tasks. Both small scale integrated (SSI) and medium scale integrated (MSI) chips
are available in many forms, that can be directly connected together to make very complex
circuits. It is this inter-connectivity that makes digital electronics so powerful and so versatile.
The standard circuits described in modules 2 to 5, both combinational and sequential, can be
used to perform arithmetic operations such as addition, subtraction and counting, as well as
logical operations such as combining data sources (multiplexing) and shifting bits left or right
within a binary word.

The Arithmetic and Logic Unit

A simplified ALU is illustrated in Fig 5.8.1, which uses an arrangement of both
combinational and sequential circuits from those described in modules 2 to 5. Their purpose is
to perform the basic (though still complex) binary arithmetic.
Data passing through the ALU circuit does a system of buses, shown by the broad arrows in Fig.
5.8.1. These buses consist of groups of wires (usually as 8 parallel bits in simple systems) each
carrying a single byte of binary data. In this system, data word A is the primary data source, and
data word B is the secondary data source that may be added to, or subtracted from word A.
 The ALU can also perform other operations. It can increment, add 1 to word A, or
decrement, and subtract 1 from it. By complementing (inverting) the logic value of individual
bits of the data word A and adding 1 to the result, it is possible to use twos complement
arithmetic to perform subtractions.
The shift register at the ALU output can also perform a ‘logical shift-left’ on word A by
shifting the 8 bits consecutively into the carry bit, alternatively the shift register can create a
rotating pattern of bits, rotating left, and using the carry bit as a ninth bit in the sequence, or
rotate the 8 bits right ignoring the carry bit. Any of these functions can be selected by the
control block, using various combinations of the eight control lines shown in Fig. 5.8.1.
Putting the correct pattern of 1s and 0s (the control word) on the control lines will cause
the ALU to perform the required arithmetic or logical operation on the data being input at A
and B. With a control word of 8-bits, this could potentially allow up to 256 different
combinations, or control words, which would be more than ample, even for very complex
microprocessors or micro controllers. However this basic ALU needs only eight control words to
control the different operations available.
To see the ALU operate as described below, you can download our free, fully interactive
Logisim ALU circuit (assuming you have the free Logisim Digital Simulator installed on your
desktop or laptop computer), see our extra Logisim page for details.

Fig. 5.8.1 ALU Block Diagram

The Component Parts

Any of the component parts of the Logisim design can be examined in detail by double
clicking on the component (in simulation mode). To return to the main document, click ‘main’
in the component menu at the left of the screen.

Multiplexers
MUX 1 and MUX 3 are identical 8 bit multiplexers that select either the input data word
A (MUX 1) or data word B (MUX 3) or their internally generated complement, as shown in Fig.
5.8.3.
MUX 2 is a similar design but selects either the data word B or the zero value 00 HEX , as
shown in Fig. 5.8.4.
8-Bit Adder
The adder component is an 8-bit ripple carry adder; real ALUs would normally feature a
‘carry-look-ahead’ adder, allowing for high-speed operation. However for this example the
much simpler ripple carry adder is adequate, as the operation is totally manual.
The adder component is illustrated in Fig. 5.8.5 and consists of eight full-adder circuits
with additional logic consisting of an XOR gate to neither detect over flow errors, and an 8-input
NOR gate to detect a zero result.
Negative results are indicated by sampling the most significant bit of the ‘sum’ output,
and a ‘carry’ is indicated by sampling the carry output of the most significant full adder.
Four D type flip-flops are used as ‘flag’ outputs to indicate the current state of the ALU after
each operation.

The shift Registers

This component uses two 4-bit shift registers (from Module 5.7) connected in cascade as
shown in Fig. 5.8.6. Inputs are provided for clock pulses, (CK), a right/left shift control (R/~L) and
an input to control whether the shift register is in shift, or load-enable modes (SHIFT/~LE).
If ~LE is chosen temporarily during shift operations, the shift register can be reloaded from the
data placed on the 8-bit ‘Data A’ and ‘carry-in’ (C IN) inputs. This action is synchronized to the CK
pulse by the external NAND and NOT gates connecting the SHIFT/~LE input to the two ~LOADS
inputs of the 4-bit shift registers.
An additional JK flip-flop (mimicking a D type flip-flop) is placed between the ‘serial-
right’ output of the shift register and COUT to allow the ‘clear carry’ input (~CLC) to clear the
carry flag.

Carry Logic and Rotate Select

The carry logic circuit shown in Fig. 5.8.7 prevents the carry flag being set in rotate right
mode, as bits rotate from bit 0 and re-enter the shift register at bit 7, therefore allowing correct
carry flag operation in both left and right rotate modes. When the ROTATE input is at logic 1,
the Rotate Select circuit in Fig 5.8.7 allows C OUT from the shift register to be fed back to the shift
register CIN input for continuous bit rotation.

Fig. 5.8.2 Basic Arithmetic and Logic Unit - Logisim Simulation

 Fig. 5.8.3 MUX 1 and MUX 3

Fig.5.8.4 MUX 2

Fig. 5.8.5 The ALU Adder Component

 Fig. 5.8.6 The ALU Shift Register Component

Fig.5.8.7 ALU Carry Logic

ALU Operation
Addition
To perform an addition, input data B is added to A. This is achieved by putting logic 1 on
the control inputs of multiplexers 1, 2 and 3. This causes data A and B to be applied to the
adder inputs. Also, to allow any carry bit from the C IN input to be included in the addition, the 1
bit carry multiplexer must have logic 0 on its control input. The shift register is only used as a
PIPO register in addition mode, so its input lines R/~L and ROTATE must be at logic 0. SHIFT/~LE
must also be at logic 0 to enable parallel loading of the shift register, which will hold the result
of the addition (A plus B) after the application of a single CK pulse.

The Status Flags

The Flag flip-flops are special outputs from the adder circuit. They consist of four
separate D type flip-flops, each of which can be set to 1 or cleared to 0. They are set or cleared
by the result in the adder. They signal, or ‘flag’ to the user, that a particular event has occurred.

The Carry Flag (C)

The carry flag will be set if the result of any arithmetic or logic event causes a logic 1 to
be carried over from bit 7 into the ‘carry bit’, (which is the carry flag). The carry flag can be
cleared at any time by making the ‘clear carry’ input (~CLC) logic 0.

The Overflow Flag (V)

 When carrying out twos complement arithmetic, errors can occur if large numbers are
involved. For example if two positive numbers less than 127 10 are added and produce a
negative result (any value greater than 12710). This would cause the sign of the result (indicated
by bit 7) to be wrong. The overflow flag gives an indication that an error has occurred by being
set to 1 to indicate an ‘overflow error’. An error is sensed and the overflow flag is set when
either of two conditions occurs.
There is a carry of logic 1 from bit 6 to bit 7 of the result, but the carry flip-flop is not at
logic 1.
There is no carry from bit 6 to bit 7 of the result, but the carry flip-flop is at logic 1.
By using the carry-out from bit 6 and the carry-out from bit 7 of the result as inputs to an XOR
gate, the output of the gate will be set to logic 1 for either of the above error conditions,
signaling an overflow error at the overflow (V) flag.

The Zero flag (Z)

This flip-flop is set when every bit of the result is zero.
The Negative flag (N)
A negative result, i.e. bit 7 = 1 sets this flip-flop to logic 1.

The Flag Register

The statuses flags are individual bits of a register called the Flag Register, and are
operative not only when the ALU is in addition mode, but also in all other arithmetic modes, the
C flag is also operative in shift and rotate left modes. In microprocessors the flag register not
only indicates ALU results, but can also be used in decision-making. For example the ALU can be
used to compare (by subtracting) two values and take various actions depending on the state of
particular flags; e.g. after comparing two values, A and B, an action may be taken if A = B,
indicated by the zero flag being set to 1, otherwise (if the zero flag is set to 0) take no action.

Subtraction
Subtraction is performed using twos complement arithmetic. That is, to subtract B from
A, input B is complemented and 1 added to the complemented value to form the twos
complement. Then the twos complement of B is added to A in the adder to find the result. To
achieve this action with data A and data B present at the inputs, logic 1 is applied to the control
inputs of MUX 1 and MUX 2. MUX 3 has logic 0 applied to its control input to complement data
B, while the CARRY MUX has a logic 1 applied to its control line so that the carry-in (C IN) to the
adder is forced to logic 1. This adds 1 to the result so that the twos complement of data B is
added to data A. The result at the adder output is a two complement number representing A -
B. The flags are again set by the result as in the addition operation.

Counting with the ALU

Although the ALU does not include a binary counter circuit, it can also be used to count,
by INCREMENTING or DECREMENTING, i.e. to add 1 to data A (incrementing), or subtract 1
from data A (decrementing). To count using this method would normally be carried out using
(machine code or assembly language) software. A typical use could be to initiate a time delay by
loading the ALU with some number, and then execute a looping routine to count down to zero
by repeatedly decrementing data A. The zero result would be detected from the zero flag being
set. However this would not be a common method, as the ALU (and therefore the CPU) would
be occupied during the delay and therefore not usable for other purposes. Most computer
systems would also have dedicated counters for implementing similar time delays.

Incrementing
Data A can be incremented if logic 1 is applied to the control inputs of MUX 1 and MUX
3. This will add B to A, with data B made zero by applying logic 0 to the control input of MUX 2.
The 1 that must be added to data A is supplied by making the control input of the CARRY
SELECT block logic 1, causing the carry input to the adder to be logic 1. The result at the adder
output is therefore A + 1, again the flags are set by the result.

Decrementing
To decrement data A, 1 must be subtracted from A. Because the ALU uses twos
complement arithmetic, the twos complement of 1 added to A will in effect subtract 1 from A.
The twos complement of 1 is minus 1, which in 8-bit twos complement notation is 11111111 2.
Therefore to subtract 1 from data A, data B must equal minus 1 (all bits = 1). To do this, and to
make sure that the correct result is not changed by any data appearing on the data B input,
logic 0 is applied to the control input of MUX 2 to make sure all data B bits = 0.
Logic 0 is also applied to the control input of MUX 3. This inverts data B, (which is
000000002) to give 111111112 at the adder input.
MUX 1 must have logic 1 on its control line, to apply data A to the other adder input.
The adder’s carry input is set to 1 by applying logic 0 to the control line of the CARRY MUX. This
ensures that, provided there is no carry-in on the C IN input, the correct result at the adder
output will be A − 1.

Negation
Negation is simply the inverse of a value; therefore any value and its inverse will add to
produce zero. In binary arithmetic the additive inverse of a value is its twos complement. The
ALU can be used to negate (find the twos complement of) data A by complementing data A and
then adding 1. This involves a similar process to decrementing, except that data B is treated
differently, as follows:
The control input of MUX 1 is set to logic 0, which complements data A, also data B is
made zero by putting logic 0 on MUX 2 control, and logic 1 on MUX 3. The Carry Select control
input is set at logic 1, to add 1 to data A in the adder.
The shift register is used as a simple PIPO register by applying logic 0 to the three shift
controls and logic 1 to the ~CLC input to make sure the carry is not cleared. This gives a final
result of A+1, which is the twos complement of A.

The Shift Operations

Shift operations are controlled by the four lower order control lines, R/~L controls the
direction of shift or rotation, SHIFT/~LE has the dual purpose of enabling the shift operations if
logic 1 is applied, or acting as a LOAD ENABLE when at logic 0, allowing the shift register to be
loaded or reloaded with appropriate data. Each action of the shift register (shift, rotate or load)
is actuated by a single CK pulse. Also note that the shift register in this design does not affect
the V, N or Z flags.

Shift Left (with Carry)

 In this mode (with control word 10100101) input data B is kept at zero and, after the
shift register is loaded by temporarily making SHIFT/~LE logic 0 to move data from input A into
the shift register, shift is enabled by returning SHIFT/~LE to logic 1, and both ROTATE and ~CLC
are disabled. The data in the shift register will now shift one bit to the left with each CK pulse
applied. This appears to multiply the value of the data by two for each shift left, but it is a very
limited multiplication operation, because the result is reduced each time the left most bit is lost
as it passes through the carry bit. This action is therefore considered a logical, rather than an
arithmetic shift.

Rotate Left (with Carry)

If rotate is activated by applying logic 1 to the ROTATE control input with SHIFT/~LE and
~CLC also at logic 1, the data being shifted left from bit 7 and through the carry flag, is returned
via the CIN input of the shift register to re-enter at bit 0 by the action of the ROTATE MODE
SELECT data selector.

Rotate right
When data in the shift register is rotated right, it leaves the register via bit 0 and is
returned directly to bit 7 via an internal link, without passing through the carry flag.
There are a number of other operations, such as performing 8 bit logic functions, commonly
found on microprocessors that this ALU is not designed to do. The purpose of this design is to
illustrate how the circuits described in Digital Electronics Modules 1 to 5 are really just part of a
bigger picture; they can be inter-connected in many ways to make many different circuits. This
ALU design is one example.

IMPORTANT FORMULAS:

SR Flip-flop

Block Diagram

Circuit Diagram
Master slave JK flip-flop

The circuit diagram and truth-table of a J-K flip flop is shown below.

Delay Flip-flop
TRUTH TABLE:

CLOCK INPUT OUTPUT

D Q Q

LOW X 0 1

HIGH 0 0 1

HIGH 1 1 0

The D(Data) is the input state for the D flip-flop. The Q and Q’ represents the output
states of the flip-flop. According to the table, based on the inputs the output changes its state.
But, the important thing to consider is all these can occur only in the presence of the clock
signal. This, works exactly like SR flip-flop for the complimentary inputs alone.

Representation of D Flip-Flop using Logic Gates:

TRUTH TABLE:

INPUT OUTPUT

INPUT 1 INPUT 2 OUTPUT 3

0 0 1

0 1 1

1 0 1

1 1 0
 Thus, comparing the NAND gate truth table and applying the inputs as given in D flip-
flop truth table the output can be analyzed. Analyzing the above assembly as a three stage
structure considering previous state (Q’) to be 0

D-type Flip-Flop Circuit:

Truth Table for the D-type Flip Flop:

Clk D Q Description

↓»0 X Q Q Memory
no change

↑»1 0 0 1 Reset Q » 0

Toggle Flip Flop

The truth table of a T flip – flop is shown below.

As mentioned earlier, T flip – flop is an edge triggered device. For example, consider a T
flip – flop made of NAND SR latch as shown below.
 If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in
disable condition. This allows the trigger to pass the S inputs to make the flip – flop in SET state
i.e. Q = 1.
If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in
enable condition. This allows the trigger to pass the R inputs to make the flip – flop in RESET
state i.e. Q =0.
In simple terms, the operation of the T flip – flop is
When the T input is low, then the next sate of the T flip flop is same as the present state.
 T = 0 and present state = 0 then the next state = 0
 T = 1 and present state = 1 then the next state = 1
When the T input is high and during the positive transition of the clock signal, the next
state of the T flip – flop is the inverse of present state.
 T = 1 and present state = 0 then the next state = 1
 T = 1 and present state = 1 then the next state = 0
As each incoming trigger alternately changes the set and reset inputs, the flip – flop
toggles. So to complete one full cycle of output wave form it need two triggers. This means that
the T flip flop produces the output at exactly half of the frequency of input frequency. So a T flip
– flops will act as “Frequency Divider Circuit”.
The main disadvantage of T flip – flop is that the state of the flip – flop at an applied
trigger pulse is known only when the previous state is known.
Generally, T flip flops are not available as ICs. So they can be constructed by using JK flip –
flop and SR flip – flop and D flip – flop. The symbol of T flip – flop made from JK flip – flop is
shown below.
PROBLEMS:

SR Flip-flop

(Easy)

1). (SR latch) Draw the output and timing diagram of a (a) NOR and (b) NAND implementation of
an SR latch for the input signals depicted in Figure P6.2.

Figure P6.2

Answer:

2). Explain how the addition of a propagation-delay-based one-shot circuit to the enable input
of an S-R latch changes its behavior:
Specifically, reference your answer to a truth table for this circuit.

Answer:
The outputs of this device are allowed to change state only when the “clock” signal (C)
is transitioning from low to high:

3).

(Moderate)

1.) Determine the output states for this S-R flip-flop, given the pulse inputs shown:

SOLUTION:
Answer:

2.) If the clock frequency driving this flip-flop is 240 Hz, what is the
Frequency of the flip-flop’s output signals (either Q or Q)?

VDD

240 HZ

SOLUTION:

FOUT = 240/2
FOUT = 120 HZ

Answer:

Fout = 120 Hz

3.) SR latch, Derive an implementation of a clocked SR latch using only:

a. NOR gates
b. NAND gates
c. AND, OR and INVERT gates

Answer:

a.

Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

Use NOR to express the above equations.

Q(next) = ((R' + C')' + (Q'))'

Q'(next) = ((S' + C') + Q)'

Draw the logic schematic.

b.

Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'
 Use NAND to express the above equations.

Q(next) = ((RC)'(Q')')''

Q'(next) = ((SC)'Q')''

Draw the logic schematic.

c.

Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

Use AND, OR and NOT to express

the above equations.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

Draw the logic schematic.

4.) Complete the excitation table for the following storage element:

SOLUTION:

QN QN+1 A B
0 0
0 1
1 0
1 1

Answer:

QN QN+1
0 0
0 1
1 0
1 1
A B
----- 0
0 1
1 0
0 ---------

5.) The following characteristic table describes a storage element A-B

Write the characteristics equation for the storage element A-B. Qn+1=.
solution and answer:

Qn+1= AB Qn + B Qn

(Difficult)
1.) Plain S-R latch circuits are “set” by activating the S input and de-activating the R input.
Conversely, they are “reset” by activating the R input and de-activating the S input. Gated
latches and flip-flops, however, are a little more complex:

Describe what input conditions have to be present to force each of these multi vibrator circuits
to set and to reset.
For the S-R gated latch:
Set by . . .
Reset by . . .
For the S-R flip-flop:
Set by . . .
Reset by . . .

Answer:
For the S-R gated latch:
Set by making S high, R low, and E high.
Reset by making R high, S low, and E high.
For the S-R flip-flop:
Set by making S high, R low, and C transition from low to high.
Reset by making R high, S low, and C transition from low to high.

2.) The flip-flop circuit shown here is classified as synchronous because both flip-flops receive
clock pulses at the exact same time:

Define the following parameters:

Set-up time
Hold time
Propagation delay time
Minimum clock pulse duration
Then, explain how each of these parameters is relevant in the circuit shown.

Answer:
The clock frequency must be slow enough that there is adequate set-up time before the next
clock pulse. The propagation delay time of FF1 must also be larger than the hold time of FF2.
And, of course, the pulse width of the clock signal must be long enough for both flip-flops to
reliably “clock.”

3.) Explain how the addition of a propagation-delay-based one-shot circuit to the enable input
of an S-R latch changes its behavior:

Specifically, reference your answer to a truth table for this circuit.

Answer:
The outputs of this device are allowed to change state only when the “clock” signal (C) is
transitioning from low to high:
4.) Identify at least one component fault that would cause the flip-flop to indicate “clockwise”
all the time, regardless of encoder motion:

For each of your proposed faults, explain why it causes the described problem.

Answer:
Phototransistor Q1 failed shorted
Resistor R2 failed open
Flip flop U1 output failed high

5.) Determine the output states for this S-R flip-flop, given the pulse inputs shown:

Answer:
Master-slave JK flip-flop

(Easy)

1). (JK flip-flops) Derive the output waveforms of a master-slave JK flip-flop for the input
waveforms depicted in Figure P6.6.
 Figure P6.6

Answer:

1. Develop characteristic table for JK flip-flop.

J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q'

2. According to the characteristic table and the J, K and Clk waveform, draw the Q
waveform
3. Indicate delays on the timing diagram.

2). A student has an idea to make a J-K flip-flop toggle: why not just connect the J, K, and Clock
inputs together and drive them all with the same square-wave pulse? If the inputs are active-
high and the clock is positive edge-triggered, the J and K inputs should both go “high” at the
same moment the clock signal transitions from low to high, thus establishing the necessary
conditions for a toggle (J=1, K=1, clock transition)

Unfortunately, the J-K flip-flop refuses to toggle when this circuit is built. No matter how many
clock pulses it receives, the Q and [Q] outputs remain in their original states - the flip-flop
remains “latched.” Explain the practical reason why the student’s flip-flop circuit idea will not
work.

Answer:

With all inputs tied together, there is zero setup time on the J and K inputs before the clock
pulse rises.
3). Determine the output states for this J-K flip-flop, given the pulse inputs shown:

Answer:

4). Flip - Flops can be used to build counters, JK-FF are the ideal elements for that purpose .
What is the truth table for the circuit above?

Answer:

CLK J K Q
X 0 0 Last state
0 1 0
1 0 1
1 1 toggle

5)

(Moderate)

1.) Determine what input conditions are necessary to set, reset, and toggle these two J-K flip-
flops:

For the J-K flip-flop with active-high inputs:

Set by . . .
Reset by . . .
Toggle by . . .
For the J-K flip-flop with active-low inputs:
Set by . . .
Reset by . . .
Toggle by . . .

Answer:
Set by activating J, deactivating K, and clocking C.
Reset by activating K, deactivating J, and clocking C.
Toggle by activating J and K simultaneously, and clocking C.
For the J-K flip-flop with active-high inputs:
Set by making J high, K low, and C transition from low to high.
Reset by making K high, J low, and C transition from low to high.
Toggle by making J high, K high and C transition from low to high.
For the J-K flip-flop with active-low inputs:
Set by making K high, J low, and C transition from high to low.
Reset by making J high, K low, and C transition from high to low.
Toggle by making J low, K low, and C transition from high to low.

2.) Determine the output states for this J-K flip-flop, given the pulse inputs shown:

Solution and answers:

3.) Flip-flops often come equipped with asynchronous input lines as well as synchronous input
lines. This J-K flip-flop, for example, has both “preset” and “clear” asynchronous inputs:
Describe the functions of these inputs. Why would we ever want to use them in a circuit?
Explain what the “synchronous” inputs are, and why they are designated by that term.
Also, note that both of the asynchronous inputs are active-low. As a rule, asynchronous inputs
are almost always active-low rather than active-high, even if all the other inputs on the flip-flop
are active-high. Why do you suppose this is?

Solution and answers:

“Asynchronous” inputs force the outputs to either the “set” or “reset” state independent of
the clock. “Synchronous” inputs have control over the flip-flop’s outputs only when the clock
pulse allows.
As for why the asynchronous inputs are active-low, I won’t directly give you the answer. But I
will give you a hint: consider a TTL implementation of this flip-flop.

4.) An extremely popular variation on the theme of an S-R flip-flop is the so-called J-K flip-flop
circuit shown here:

Note that an S-R flip-flop becomes a J-K flip-flop by adding another layer of feedback from the
outputs back to the enabling NAND gates (which are now three-input, instead of two-input).
What does this added feedback accomplish? Express your answer in the form of a truth table.

Solution and answers:

5.) (JK flip-flops) derive the output waveforms of a master-slave JK flip-flop for the input waveforms
depicted in Figure P6.6.

Figure P6.6

Solutions and Answer:

1. Develop characteristic table for JK flip-flop.

J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q'

2. According to the characteristic table and the J, K and Clk waveform, draw the Q
waveform
3. Indicate delays on the timing diagram.

(Difficult)
1.) (Sequential Synthesis) Design a simplified traffic-light controller that switches traffic lights on
a crossing where a north-south (NS) street intersects an east-west (EW) street. The input to the
controller is the WALK button pushed by pedestrians who want to cross the street. The outputs
are two signals NS and EW that control the traffic lights in NS and EW directions. When NS or
EW is 0, the red light is on and when they are 1, the green light is on. When there are no
pedestrians, NS=0 and EW=1 for 1 minute, followed by NS=1 and EW=0 for 1 minute and so on.
When a WALK button is pushed, NS and EW both come 1 for a minute when the present minute
expires. After that the NS and EW signals continue alternating. For the traffic-light controller:

a. Develop a state diagram and state/output table.

b. Minimize the number of states.
c. Encode the states.
d. Draw a schematic diagram.

Solution and answer:

1. Define the states as the following:

S0: (NS = 0, EW = 1)
S1: (NS = 1, EW = 0)
S2: (NS = 1, EW = 1)

The state diagram is:

2. The state/output table is:

PRESENT NEXT STATE

STATE
Walk Walk
=0 =1

S0 S1/01 S2/01
S1 S0/10 S2/10

S2 S0/11 S2/11

3. Using minimum-bit-change strategy, get the minimizing state encoding as following:

S0 = 00
S1 = 01
S2 = 10

4. After state encoding, the state/output stable will be:

PRESENT STATE NEXT STATE

Walk = 0 Walk = 1

00 01/01 10/01

01 00/10 10/10

11 XX/XX XX/XX

10 00/11 10/11

5. The equations defining the implementation can be describe as:

D0 = Q1'Q0'Walk'
D1 = Walk
NS = Q0 + Q1
EW = Q0'

6. Draw logic schematic from the equations using D flip-flops:

2.) Design a mod-10 binary up-counter using negative edge JK flip-flops with active-LOW clear.

Solution and answer:

Four flip-flops are required, and decimal state 10 must be decoded and used to reset all flip-
flops to give a repeated count from 0 to 9 (0000 to 1001). State 10 is given
by Q3Q¯2Q1Q¯0 (1010) so a four-input NAND gate (as the clear is active-LOW) could be used to
decode this count and clear all flip-flops. However, since states 11 to 15 will never be entered
they can be considered as ‘don't care’ conditions and used to simplify the logic. From the
Karnaugh map in Fig. 7.2 it can be seen that the count state Q3, Q1 can be used to perform the
reset with the subsequent circuit also shown.

3.) Consider the following sequential logic circuit containing a JK flip-flop and a D flip-flop (not
all connections are shown to keep the schematic simple):
Solution and answer:

The D flip-flop has output X. Its input has no name, so let's call its input DX. The JK flip-flop has
output Y. Its inputs also have no names so let's call them JY, and KY. We can then give formulas
for the combinational logic inputs of each flip-flop input as follows:

 DX = A nand B
 JY = X or Y
 KY = A nand B

4.) (JK flip-flops) derive the output waveforms of a master-slave JK flip-flop for the input
waveforms depicted in Figure P6.6.

Figure P6.6

Solution and answer:

1.) Develop characteristic table for JK flip-flop.

 J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q'

2. According to the characteristic table and the J, K and Clk waveform, draw the Q waveform

3. Indicate delays on the timing diagram.

5.) (Sequential Synthesis) Design a counter that counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,

0... Using natural binary encoding and D-type flip-flops.

Solution:
1. In order to implement this modulo-10 counter, we will need four flip-flops labeled: Q 3, Q2,
Q1, and Q0. Using natural binary encoding, we can derive a state transitions table:
2. from the transitions table, write transitions equations.
Q3 (next) = Q2Q1Q0 + Q3Q1'Q0'
Q2 (next) = Q2'Q1Q0 + Q2Q1' + Q2Q0'
Q1 (next) = Q3'Q1'Q0 +Q1Q0'
Q0 (next) = Q0'

3. Derive logic schematic:

Answer:

Delay Flip-flop

(easy)

1). In PROBLEM 1 learners are tasked to investigate the function and operation of the D type
flip flop and to consider:
• How does the flip flop operate and what is its purpose?
• What are each of the inputs and outputs?
• In what type of applications are flip flops used?

Solutions
• The D type flip flop is a latching device with outputs that have two stable states. This means
that the output can be switched from logic 0 to logic 1, or logic 1 to logic 0 when required. Once
set into either of these states it will remain there indefinitely so long as power is maintained to
the device. For this reason it is often termed a ‘bistable’.
 • The purpose of a D type flip flop is to act as a latch or memory or storage device. It can store
the information present on its inputs.
• The terminals are as follows:

• Typical applications of the D type flip flop are: Latches, Counters, Memory Devices, Shift
Registers.

Answer:

2). In PROBLEM 2, learners are asked to complete timing diagrams for a positive edge triggered
D type flip flop. Solutions to Activity 2 are given below. Note that input signal D is captured on
positive transitions of CK only. Learners are tasked to complete Q and Q.

Answer :
3). In PROBLEM 3, learners are asked to complete timing diagrams for a negative edge triggered
D type flip flop. Solutions to Activity 3 are given below. Note that input signal D is captured on
negative transitions of CK only. Learners are tasked to complete Q and Q.

Answer:

4). Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter.
Answer:

5). Determine the final output states over time for the following circuit, built from D-type gated
latches:

At what specific times in the pulse diagram does the final output assume the input’s state? How
does this behavior differ from the normal response of a D-type latch?

Answer :
The final output assumes the same logic state as the input only when the enable input signal (B)
transitions from “high” to “low”.

(Moderate)
1.) Determine the final output states over time for the following circuit, built from D-type gated
latches:

At what specific times in the pulse diagram does the final output assume the input’s state? How
does this behavior differ from the normal response of a D-type latch?

Solution:

Answer:

The final output assumes the same logic state as the input only when the enable input signal (B)
transition from “high” to “low”.

2.)
Now, suppose we add a propagation-delay-based one-shot circuit to the Enable line of this D-
type gated latch. Re-analyze the output of the circuit, given the same input conditions:

Comment on the differences between these two circuits’ responses, especially with reference
to the enabling input signal (B).

Answer:

3.) Determine the output states for this D flip-flop, given the pulse inputs shown:
Answer:

4.) A scientist is using a microprocessor system to monitor the Boolean (“high” or “low”) status
of a particle sensor in her high-speed nuclear experiment. The problem is, the nuclear events
detected by the sensor come and go much faster than the microprocessor is able to sample
them. Simply put, the pulses output by the sensor are too brief to be “caught” by the
microprocessor every time:

She asks several technicians to try and fix the problem. One tries altering the microprocessor’s
program to achieve a faster sampling rater, to no avail. Another recalibrates the particle sensor
to react slower, but this only results in missed data (because the real world data does not slow
down accordingly!). No solution tried so far works, because the fundamental problem is that
the microprocessor is just too slow to “catch” the extremely short pulse events coming from
the particle sensor. What is required is some kind of external circuit to “read” the sensor’s state
at the leading edge of a sample pulse, and then hold that digital state long enough for the
microprocessor to reliably register it.
Finally, another electronics technician comes along and proposes this solution, but then goes
on vacation, leaving you to implement it:
Explain how this D-type flip-flop works to solve the problem, and what action the
microprocessor has to take on the output pin to make the flip-flop function as a detector for
multiple pulses.

Answer:
The flip-flop becomes “set” every time a pulse comes from the sensor. The microprocessor
must clear the flip-flop after reading the captured pulse, so the flip-flop will be ready to capture
and hold a new pulse.
5.) (Sequential Synthesis) Design a counter that counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
0... by using natural binary encoding and D-type flip-flops.

Answer:
In order to implement this modulo-10 counter, we will need four flip-flops labeled: Q3, Q2, Q1,
and Q0. Using natural binary encoding, we can derive a state transitions table:

(Difficult)
1.) (Sequential Synthesis) Design a counter that counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
0,..., using natural binary encoding and D-type flip-flops.
SOLUTION:
1. In order to implement this modulo-10 counter, we will need four flip-flops labeled: Q3, Q2,
Q1, and Q0. Using natural binary encoding, we can derive a state transitions table:

2. from the transitions table, write transitions equations

Q3 (next) = Q2Q1Q0 + Q3Q1'Q0'
Q2 (next) = Q2'Q1Q0 + Q2Q1' + Q2Q0'
Q1 (next) = Q3'Q1'Q0 +Q1Q0'
Q0 (next) = Q0'
ANSWER:

2.) Design a recognizer that recognizes an input sequence that has at least three 1's. The
recognizer has a single input X, and a single output Y, in addition to an asynchronous Reset
signal. The recognizer sets the output Y to 1 if the input signal X was equal to 1 in at least 3
clock cycles after the Reset was disserted. For the above recognizer described above:
a. Devise the state diagram.
b. Minimize the number of states.
c. Encode the states to minimize the combinatorial logic.
d. Draw a schematic diagram using D flip-flops

SOLUTION:
1. Define the states as the following:
S0: 0 ones received,
S1: 1 ones received,
S2: 2 ones received,
S3: 3 or more ones received.
The state diagram is:

2. The state/output table is:

PRESENT STATE NEXT STATE
Walk = 0 Walk = 1
S0 S0/0 S1/0
S1 S1/0 S2/0
S2 S2/0 S3/0
S3 S3/1 S3/1
From the state/output table, we can minimize the state number by using implication table.
3. The equations defining the implementation can be described as:
D1 = Q1 + Q0X
D0 = Q0X' + Q1'X
Y = Q1Q0'
ANSWER:

3.) Determine the output states for this D flip-flop, given the pulse inputs shown:

ANSWER:
4.) Given the input waveforms shown below, sketch the output, Q, of a:
a) D latch
b) Positive-edge triggered D flip-flop
SOLUTION:
Digital Logic Design Worked Example:

D Latch Explanation:
D latch output behavior can be most simply described as mirroring that of the input Q
while CLK is high and retaining its most recent value while CLK is low. Thus, the output Q of a D
latch should simply reflect D while CLK is high and hold whatever value it had every time CLK
transitions from high to low for the duration of the low value for CLK. This behavior is illustrated
in the given solutions.
In this module, the value of Q could be either high or low at the very beginning,
so both states are shown. As soon as CLK goes high, the output Q conforms to the value of the
input D. Thereafter, Q follows the D latch behavior described above, mirroring D when CLK is
high and retaining its stored value when CLK is low, ignoring D during these intervals.

D Flip-Flop Explanation:
D flip-flop behavior is similar to that of D latches, except that instead of mirroring the
behavior of the input D whenever CLK is high, the output Q of a positive-edge triggered D flip-
flop will only accept a new value whenever the CLK transitions from low to high. This value will
be retained throughout the rest of the CLK cycle until a new value is read, whereupon a new
value (which may be the same as the old value) will be copied to the output.

In this module, the behavior of the D flip-flop is unexciting. As it is not stated whether
the output was high or low at the beginning of the period examined in this problem, both
possible

States are shown. On the first positive edge of the clock, the value for D is low, so the
value for the output Q of the D flip-flop will become low. On the two subsequent positive edges
of the clock, the value of the input D happens to be low, so the output Q remains low. It is only
on the final positive edge that the value of D happens to be high, so the output Q becomes
high.

Answer:
There is no particular relationship between CLK and the input D. CLK is varying periodically and
D is some input signal not directly related to CLK.
CLK is portrayed behaving periodically, as is generally the case, but the described behavior for D
latches and D flip-flops would hold even if it were not. D latches would copy the input D to the
output Q whenever CLK was high and D flip-flops would do the same on every low-to-high
transition.
The solution displayed has some delay between the transition of CLK or D and any change in Q;
as delay is not the point of this problem, submitted answers would not need to include this
delay.

5.) Determine the Q and [Q] output states of this D-type gated latch, given the following input
conditions:

Now, suppose we add a propagation-delay-based one-shot circuit to the Enable line of this D-
type gated latch. Re-analyze the output of the circuit, given the same input conditions:
ANSWER:

REFERENCES:

Work Out Electronics

Author: G. Waterworth

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