D FLIPFLOP

EASY PROBLEM (MARVIN JAVIER)

1). In PROBLEM 1 learners are tasked to investigate the function and operation of the D type
flip flop and to consider:
• How does the flip flop operate and what is its purpose?
• What are each of the inputs and outputs?
• In what type of applications are flip flops used?

Solutions
• The D type flip flop is a latching device with outputs that have two stable states. This means
that the output can be switched from logic 0 to logic 1, or logic 1 to logic 0 when required. Once
set into either of these states it will remain there indefinitely so long as power is maintained to
the device. For this reason it is often termed a ‘bistable’.
• The purpose of a D type flip flop is to act as a latch or memory or storage device. It can store
the information present on its inputs.
• The terminals are as follows:

• Typical applications of the D type flip flop are: Latches, Counters, Memory Devices, Shift
Registers.
Answer:

2). In PROBLEM 2, learners are asked to complete timing diagrams for a positive edge triggered
D type flip flop. Solutions to Activity 2 are given below. Note that input signal D is captured on
positive transitions of CK only. Learners are tasked to complete Q and Q.

Answer :
3). In PROBLEM 3, learners are asked to complete timing diagrams for a negative edge triggered
D type flip flop. Solutions to Activity 3 are given below. Note that input signal D is captured on
negative transitions of CK only. Learners are tasked to complete Q and Q.

Answer :

4). Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter.

Answer:
5). Building a quadrature direction detector circuit is easy, if you use a D-type flip-flop:

Analyze this circuit, and explain how it works.

Answer:

The operation of this circuit is quite easy to understand if you draw a pulse diagram for it and
analyze the flip-flop’s output over time. When the encoder disk spins clockwise, the Q output
goes high; when counterclockwise, the Q goes low.

Jk

1). (JK flip-flops) Derive the output waveforms of a master-slave JK flip-flop for the input waveforms
depicted in Figure P6.6.
 Figure P6.6

Solution

1. Develop characteristic table for JK flip-flop.

J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q'

2. According to the characteristic table and the J, K and Clk waveform, draw the Q waveform
3. Indicate delays on the timing diagram.
 SR

1). (SR latch) Draw the output and timing diagram of a (a) NOR and (b) NAND implementation of an
SR latch for the input signals depicted in Figure P6.2.

Figure P6.2
Answer:

2). (SR latch) Derive an implementation of a clocked SR latch using only:

a. NOR gates
b. NAND gates
c. AND, OR and INVERT gates

Answer:

a. Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

 Q'(next) = (SC + Q)'

b. Use NOR to express the above equations.

Q(next) = ((R' + C')' + (Q'))'

Q'(next) = ((S' + C') + Q)'

c. Draw the logic schematic.

b.
a. Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

b. Use NAND to express the above equations.

Q(next) = ((RC)'(Q')')''
Q'(next) = ((SC)'Q')''

c. Draw the logic schematic.

c.
a. Write Boolean equations for Q and Q' of clocked SR latch.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

b. Use AND, OR and NOT to express the above equations.

Q(next) = (RC + (Q'))'

Q'(next) = (SC + Q)'

c. Draw the logic schematic.