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CD4051B, CD4052B, CD4053B: Features
CD4051B, CD4052B, CD4053B: Features
Data sheet acquired from Harris Semiconductor August 1998 - Revised October 2003
SCHS047G
Logic Temperature Range, 100nA at 18V and 25oC CD4051BE, CD4052BE, -55 to 125 16 Ld PDIP
CD4053BE
Level • Break-Before-Make Switching Eliminates Channel
Overlap CD4051BM, CD4051BMT, -55 to 125 16 Ld SOIC
Conver- CD4051BM96
sion) CD4052BM, CD4052BMT,
/Author Applications CD4052BM96
CD4053BM, CD4053BMT,
() • Analog and Digital Multiplexing and Demultiplexing CD4053BM96
/Key- • A/D and D/A Conversion CD4051BNSR, CD4052BNSR, -55 to 125 16 Ld SOP
words • Signal Gating
CD4053BNSR
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD4051B, CD4052B, CD4053B
Pinouts
CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) CD4052B (PDIP, CDIP, SOP, TSSOP)
TOP VIEW TOP VIEW
VEE 7 10 B VEE 7 10 A
VSS 8 9 C VSS 8 9 B
by 1 16 VDD
IN/OUT bx 2 15 OUT/IN bx OR by
cy 3 14 OUT/IN ax OR ay
OUT/IN CX OR CY 4 13 ay
IN/OUT
IN/OUT CX 5 12 ax
INH 6 11 A
VEE 7 10 B
VSS 8 9 C
7 6 5 4 3 2 1 0
16 VDD 4 2 5 1 12 15 14 13
TG
TG
A † 11
TG
COMMON
TG OUT/IN
B † 10 BINARY
LOGIC TO 3
1 OF 8
LEVEL TG
DECODER
CONVERSION WITH
C † 9 INHIBIT TG
TG
INH † 6
TG
8 VSS 7 VEE
2
CD4051B, CD4052B, CD4053B
X CHANNELS IN/OUT
3 2 1 0
11 15 14 12
TG
16 VDD
TG
TG COMMON X
OUT/IN
TG 13
A † 10
BINARY
TG 3
LOGIC TO
B † 9 1 OF 4 COMMON Y
LEVEL
DECODER OUT/IN
CONVERSION TG
WITH
INH † 6 INHIBIT
TG
TG
1 5 2 4
0 1 2 3
8 VSS 7 VEE
Y CHANNELS IN/OUT
CD4053B
BINARY TO
1 OF 2 IN/OUT
LOGIC DECODERS
LEVEL 16 VDD WITH
CONVERSION INHIBIT cy cx by bx ay ax
3 5 1 2 13 12
COMMON
OUT/IN
TG ax OR ay
14
A † 11 TG
COMMON
OUT/IN
TG bx OR by
15
B † 10
TG
COMMON
OUT/IN
TG cx OR cy
C † 9
4
TG
INH † 6
VDD
8 VSS 7 VEE
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES
INPUT STATES
CD4051B
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 X X X None
CD4052B
INHIBIT B A
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
INHIBIT A OR B OR C
0 0 ax or bx or cx
0 1 ay or by or cy
1 X None
X = Don’t Care
4
CD4051B, CD4052B, CD4053B
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Note 3)
PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS
Change in ON - 0 0 5 - - - - - 15 - Ω
Resistance (Between
- 0 0 10 - - - - - 10 - Ω
Any Two Channels),
∆rON - 0 0 15 - - - - - 5 - Ω
Capacitance: - -5 5- 5
Input, CIS - - - - - 5 - pF
Output, COS
CD4051 - - - - - 30 - pF
CD4052 - - - - - 18 - pF
CD4053 - - - - - 9 - pF
Feedthrough
CIOS - - - - - 0.2 - pF
5
CD4051B, CD4052B, CD4053B
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)
PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS
Input Low Voltage, VIL , VIL = VDD VEE = VSS , 5 1.5 1.5 1.5 1.5 - - 1.5 V
Max through RL = 1kΩ to VSS ,
10 3 3 3 3 - - 3 V
1kΩ; IIS < 2µA on All
VIH = VDD OFF Channels 15 4 4 4 4 - - 4 V
through
Input High Voltage, VIH , 1kΩ 5 3.5 3.5 3.5 3.5 3.5 - - V
Min
10 7 7 7 7 7 - - V
15 11 11 11 11 11 - - V
-5 0 5 - - - - - 225 450 ns
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specifications
TEST CONDITIONS LIMITS
Cutoff (-3dB) Frequency Chan- 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz
nel ON (Sine Wave Input)
VEE = VSS , CD4052 25 MHz
V OS CD4051 20 MHz
20Log ------------ = – 3dB
V IS
VOS at Any Channel 60 MHz
6
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS LIMITS
3 (Note 3) 10 0.2 %
5 (Note 3) 15 0.12 %
Address-or-Inhibit-to-Signal - 10 10 65 mVPEAK
Crosstalk (Note 4)
NOTES:
3. Peak-to-Peak voltage symmetrical about V DD – V EE
-----------------------------
2
4. Both ends of channel.
500 250
200 TA = 125oC
400
0 0
-4 -3 -2 -1 0 1 2 3 4 5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V) VIS , INPUT SIGNAL VOLTAGE (V)
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)
7
CD4051B, CD4052B, CD4053B
600 250
TA = 25oC VDD - VEE = 15V
VDD - VEE = 5V
500
200
TA = 125oC
400
150
300
100 TA = 25oC
200
TA = -55oC
10V
50
100 15V
0 0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS , INPUT SIGNAL VOLTAGE (V) VIS , INPUT SIGNAL VOLTAGE (V)
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)
6 105
VDD = 5V TA = 25oC TEST CIRCUIT
6 VDD = 5V 11 15
11
102 6 14
102 VDD = 5V 7 7
CL = 15pF 8 8
Ι
CL = 15pF Ι
10
10
1 10 102 103 104 105 1 10 102 103 104 105
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B) FREQUENCY (CD4053B)
8
CD4051B, CD4052B, CD4053B
7.5V 5V 5V
16 16 16 16
VSS = 0V VSS = 0V
VSS = 0V
VEE = 0V
7 7 7 7
8 VEE = -7.5V 8 VEE = -10V 8 VEE = -5V 8
VSS = 0V
(A) (B) (C) (D)
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(RL = 1kΩ) (RL = 1kΩ)
1 16 1 16 1 16
2 15 2 15 2 15
3 14 IDD 3 14 IDD 3 14
4 13 4 13 4 13 IDD
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9
9
CD4051B, CD4052B, CD4053B
1 16 1 16 1 16
2 15 2 15 2 15 IDD
IDD 3 14 IDD 3 14 3 14
4 13 4 13 4 13
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9
VDD VDD
OUTPUT
OUTPUT OUTPUT
1 16 1 16 VDD 1 16
VDD 2 15 RL CL 2 15 2 15 RL CL
CL RL
3 14 3 14 3 14
4 13 VEE VDD 4 13
4 13
5 12 VDD 5 12 VEE
5 12 VDD
VEE 6 11 VEE 6 11 VEE 6 11
VSS CLOCK VEE VDD VSS CLOCK
7 10 7 10 7 10
IN VSS CLOCK IN
8 9 8 9 8 9
VSS VSS IN VSS
CD4051 VSS CD4052 VSS CD4053 VSS
VDD VDD
OUTPUT OUTPUT
OUTPUT
1 16 1 16 1 16 VDD
RL 50pF 2 15 RL 50pF 2 15 RL 2 15
50pF
3 14 3 14 3 14
VEE 4 13 VEE 4 13 4 13
VEE
VDD VDD 5 12 VDD 5 12 VDD 5 12
6 11 VDD 6 11 VDD 6 11
VSS VSS
CLOCK VEE 7 10 CLOCK VEE 7 10 VSS CLOCK VEE 7 10
IN VSS 8 9 IN VSS 8 9 IN VSS 8 9
VDD
VDD VDD
µA VIH
1K 1 16
1 16 1 16 1K 1K 2 15 µA
2 15 2 15 µA 1K
3 14
3 14 3 14 4 13
1K 4 13 VIH 4 13 VIH
VIH 5 12
5 12 5 12 1K
VIL 6 11 VIH
6 11 6 11 7 10
VIL 7 10 VIL 7 10 VIL
VIH 8 9
8 9 8 9
CD4053B
CD4051B CD4052B
VIL VIL
MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6) “OFF” CHANNELS (e.g., CHANNEL 2x) “OFF” CHANNELS (e.g., CHANNEL by)
10
CD4051B, CD4052B, CD4053B
FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
CIRCUIT
VDD VDD
1 16 1 16
2 15 2 15
3 14 3 14
4 13 4 13
5 12 VDD 5 12 VDD
6 11 6 11
7 10 Ι 7 10 Ι
8 9 8 9
VSS VSS
VSS CD4051 VSS CD4052
CD4053 NOTE: Measure inputs sequentially, NOTE: Measure inputs sequentially,
to both VDD and VSS connect all to both VDD and VSS connect all
unused inputs to either VDD or VSS . unused inputs to either VDD or VSS .
5VP-P
CHANNEL CHANNEL
ON OFF
RF
VM
5VP-P RF COMMON RL
OFF VM
CHANNEL
1K
VDD RL
CHANNEL RF CHANNEL
6 OFF VM ON
7 RL
RL
8
FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
5VP-P
CHANNEL IN X CHANNEL IN Y RF
ON OR OFF ON OR OFF VM
RL RL
11
CD4051B, CD4052B, CD4053B
COMMUNICATIONS
LINK
DIFF. DIFF.
AMPLIFIER/ RECEIVER
LINE DRIVER
DIFF. DEMULTIPLEXING
MULTIPLEXING
Special Considerations
In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load). This
provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the
CD4051B, CD4052B or CD4053B.
A A
B B
CD4051B
C C
INH
Q0 COMMON
D A A
Q1 B OUTPUT
1/2
E B CD4051B
CD4556 Q2 C
E INH
A
B
CD4051B
C
INH
12
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
7901502EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
8101801EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4051BE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4051BEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4051BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4051BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4051BM ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BME4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BMTE4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4051BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4052BEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4052BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4052BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4052BM ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BM96 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
CD4052BME4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BMT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BMTE4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BNSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4053BEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4053BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4053BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD4053BM ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BM96 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BME4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BMT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BMTE4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BNSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BPW ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
no Sb/Br)
CD4053BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
0,30
0,65 0,10 M
0,19
14 8
0,15 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
1 7
0°– 8°
A 0,75
0,50
Seating Plane
PINS **
8 14 16 20 24 28
DIM
4040064/F 01/97
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