Digital System Design LAB 3

IMPLEMENTATION OF BARREL SHIFTER

OBJECTIVES

• To write Verilog module for Barrel Shifter at behavioral level

• To write Verilog module for Barrel Shifter at gate level
• To use Arithmetic modules in Verilog HDL.

INTRODUCTION

A barrel shifter is a combinational logic circuit with n data inputs, n data outputs, and a set
of control inputs that specify how to shift the data between input and output. A barrel
shifter that is part of a microprocessor CPU can typically specify the direction of shift (left or
right), the type of shift (circular, arithmetic, or logical), and the amount of shift (typically 0
to n–1 bits, but sometimes 1 to n bits).

A typical barrel shifter has n data inputs, n data outputs and control inputs. Control inputs
specify ,direction, type (arithmetic, logical, circular) , number of positions to rotate or shift
data inputs for example: n = 16 , DIN[15:0], DOUT[15:0], S[3:0] (shift amount) then to
this problem there are many possible solutions, all based on multiplexers.

Barrel Shifter at gate level in Verilog HDL

Table below shows pin description for ALU

Signal I/O Number of Bits

Data ; Input 4

type Input 2

amount Input 2

out Output 4

Modules below implement a barrel shifter at gate level

1. Module barrel_shifter
Module barrel_shifter(data, type, amount, out);

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Digital System Design LAB 3
Input [3:0] data;

Input [1:0] type;

Input [1:0] amount;

Output [3:0] out;

mux16x1 m3(data[3], data[2], data[1], data[0],

data[3], 1'b0 , 1'b0 , 1'b0 ,

data[3], data[2], data[1], data[0],

data[3], data[0], data[1], data[2],

amount[0], amount[1], type[0], type[1], out[3]);

mux16x1 m2(data[2], data[1], data[0], 1'b0 ,

data[2], data[3], 1'b0 , 1'b0 ,

data[2], data[1], data[0], data[3],

data[2], data[3], data[0], data[1],

amount[0], amount[1], type[0], type[1], out[2]);

mux16x1 m1(data[1], data[0], 1'b0 , 1'b0 ,

data[1], data[2], data[3], 1'b0 ,

data[1], data[0], data[3], data[2],

data[1], data[2], data[3], data[0],

amount[0], amount[1], type[0], type[1], out[1]);

mux16x1 m0(data[0], 1'b0 , 1'b0 , 1'b0 ,

data[0], data[1], data[2], data[3],

data[0], data[3], data[2], data[1],

data[0], data[1], data[2], data[3],

amount[0], amount[1], type[0], type[1], out[0]);

endmodule

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Digital System Design LAB 3
2. module mux16x1
module mux16x1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, s0, s1, s2, s3, out);

input a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, s0, s1, s2, s3;

output out;

wire w1, w2;

mux8x1 m1(a, b, c, d, e, f, g, h, s0, s1, s2, w1);

mux8x1 m2(i, j, k, l, m, n, o, p, s0, s1, s2, w2);

mux2x1 m3(w1, w2, s3, out);

endmodule

3. module mux8x1
module mux8x1(a, b, c, d, e, f, g, h, s0, s1, s2, out);

input a, b, c, d, e, f, g , h, s0, s1, s2;

output out;

wire w1, w2;

mux4x1 m1(a, b, c, d, s0, s1, w1);

mux4x1 m2(e, f, g, h, s0, s1, w2);

mux2x1 m3(w1, w2, s2, out);

endmodule

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Digital System Design LAB 3
4. module mux4x1
module mux4x1(a, b, c, d, s0, s1, out);

input a, b, c, d, s0, s1;

output out;

wire w1, w2;

mux2x1 m1(a, b, s0, w1);

mux2x1 m2(c, d, s0, w2);

mux2x1 m3(w1, w2, s1, out);

endmodule

5. module mux2x1
module mux2x1(a, b, s, out);

input a, b, s;

output out;

wire w1, w2;

and (w2, b, s);

and (w1, a, ~s);

or (out, w1, w2);

endmodule

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Digital System Design LAB 3
Draw a figure which is representative of the hierarchy of Verilog codes provided?

Task1
Create a project in Xilinx ISE .Add all of the modules written above to the project. Now
simulate this file using ISE Simulator. Next synthesize this file using XST.

Now Answer following Questions

Explain and record results for above Verilog module?

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Draw results from Test bench for barrel shifter? Indicate Input & Output signals?

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Digital System Design LAB 3
Barrel Shifter at behavioral level Verilog HDL
A Verilog module for barrel shifter at behavioral level is written below.

module barrel_shifter_behavioral(data, type, amount, out);

input [3:0] data;

input [1:0] type;

input [1:0] amount;

output reg [3:0] out;

always @ (data or type or amount)

begin

case({type, amount})

//cases for shift left

4'b0000: out = data;

4'b0001: out = {data[2:0], 1'b0 };

4'b0010: out = {data[1:0], 2'b00 };

4'b0011: out = {data[0] , 3'b000};

//cases for shift right

4'b0100: out = data;

4'b0101: out = {1'b0 , data[3:1]};

4'b0110: out = {2'b00 , data[3:2]};

4'b0111: out = {3'b000, data[3] };

//cases for rotate left

4'b1000: out = data;

4'b1001: out = {data[2:0], data[3] };

4'b1010: out = {data[1:0], data[3:2]};

4'b1011: out = {data[0] , data[3:1]};

//cases for rotate right

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Digital System Design LAB 3
4'b1100: out = data;

4'b1101: out = {data[0] , data[3:1]};

4'b1110: out = {data[1:0], data[3:2]};

4'b1111: out = {data[2:0], data[3] };

endcase

end

endmodule

Task2

Create a project in Xilinx ISE .Add this file to the project .Now simulate this file using ISE
Simulator. Now Answer following Questions

Explain following statement?

out = {data[2:0], data[3] };

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How you are shifting data in barrel shifter at behavioral level as compared to
module written at gate level?

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Draw results from Test bench for barrel shifter at behavioral level?

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Digital System Design LAB 3
Arithmetic Operations
Adders, Subtractors, Adders/Subtractors

Task3
Create a project in Xilinx ISE .Add this file to the project .For each file create test bench and
generate output waveforms. Then answer Questions given at the end of modules.

Unsigned 8-Bit Adder

The following module describes Unsigned 8-bit Adder.

module v_adders_1(A, B, SUM);

input [7:0] A;

input [7:0] B;

output [7:0] SUM;

assign SUM = A + B;

endmodule

Explain following statement?

assign SUM = A + B;

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Draw wave form results from Test bench for Unsigned 8-bit Adder?

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Digital System Design LAB 3
Unsigned 8-Bit Adder with Carry In
The following module describes Unsigned 8-bit Adder with Carry.

module v_adders_2(A, B, CI, SUM);

input [7:0] A;

input [7:0] B;

input CI;

output [7:0] SUM;

assign SUM = A + B + CI;

endmodule

Draw wave form results from Test bench for Unsigned 8-bit Adder with Carry In?

Unsigned 8-Bit Adder with Carry Out

The following module describes Unsigned 8-bit Adder with Carry Out.

module v_adders_3(A, B, SUM, CO);

input [7:0] A;

input [7:0] B;

output [7:0] SUM;

output CO;

wire [8:0] tmp;

assign tmp = A + B;

assign SUM = tmp [7:0];

assign CO = tmp [8];

endmodule

Draw wave form results from Test bench for Unsigned 8-bit Adder with Carry In?

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Digital System Design LAB 3
Unsigned 8-Bit Adder with Carry In and Carry Out
The following module describes Unsigned 8-bit Adder with Carry In and Carry Out.

module v_adders_4(A, B, CI, SUM, CO);

input CI;

input [7:0] A;

input [7:0] B;

output [7:0] SUM;

output CO;

wire [8:0] tmp;

assign tmp = A + B + CI;

assign SUM = tmp [7:0];

assign CO = tmp [8];

endmodule

Draw wave form results from Test bench for Unsigned 8-bit Adder with Carry In
and carry out?

Unsigned 8-Bit Subtractor

module v_adders_6(A, B, RES);

input [7:0] A;

input [7:0] B;

output [7:0] RES;

assign RES = A - B;

endmodule

Draw wave form results from Test bench for Unsigned 8-bit Subtractor ?

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Digital System Design LAB 3
Unsigned 8-Bit Adder/Subtractor
module v_adders_7(A, B, OPER, RES);

input OPER;

input [7:0] A;

input [7:0] B;

output [7:0] RES;

reg [7:0] RES;

always @(A or B or OPER)

begin

if (OPER==1'b0) RES = A + B;

else RES = A - B;

end

end module

Explain following statements?

if (OPER==1'b0) RES = A + B;

else RES = A - B;

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Draw wave form results from Test bench for unsigned 8-bit Adder/Subtractor?

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Observations/Comments/Explanation of Results