Experiment 1 1, Alm: Te analyze und implement Hoolenn Express) i ” 1 ANOT,NOR, NAND and XOR ates, pressions using Basic Logic Gates (AND, Apparatus Required: 1C 7408, 7432, 7404, IC 7486, 7400, 7402, 7486 and Digital Training Kit. 2, Learaing Objectives: This experiment cnables a student to learn + How to analyze logic gates + How to express Boolean expression using logic gates + How to check equivalence of two Boolean expressions using logic gates * How tw check equivalence of two logic circuits eons F muttipte gates 3. Theory: Analysis of Logic gates using 7408, 7432, 7404 Power Supply. Di , chip are shown in figures jupply. Diagrams of cach tio Figure 3 Fig: | .7408(quad 2 input AND gates) Fig: 3. 7432 (quad 2 input OR gates) Fig: 3. 7404(HEX inverter)SE Tty Figure 6 Fig: 4.7432(quad 2 input NOR gates) Fig: 5. 7400 (quad 2 input NAND gates) Fig’ 6 74864 quad 2 input XOR gates) (a) AB+A'C+BC=ABtA'C According lo comensus theorem, the Boolean identity holds. Inthe above picture both circuits are equivalent. (b) Verify cquivatence of OR-AND atid NOR-NOR structurein the above picture both circuiis are equivalent, Student muy be asked to wire up ihe meyers of gates shown in the above figures. They can next verify tit the output of the (we circuits, y zi and 22. 4. Procedure: Fallow these sieps (o do the experiment. 1. At first go through the structure of 7404 Hex inverter, 7408 quad 2-inpuil AND yates), 7432(quad 2-input OR gales). 2. Next, apply o high level voltage to all the inputs A, B,C. 3. Next, check that both LEDs glow. This is because bath the outputs x1 and 22 attain the sar value, 4. Thus, AB+A’C+BC=AB+A’C holds for the condition A=1-C="1". 5, For all the combinations of the variables A, B, and C verify that bath the 1.5 are glowing not glowing. If the LED glows, it indicates that the corresponding output has reached logic | level. Similarly, a dark LED indicates low level output voliage.6. Preeautions: 1. Do not press the IC on breadboard until pins are aligned with pours. 2. Make connection properly. 3. There should not any short circuit in the circuit. 4. Avoid the heating of IC 7. 7. Learaing Outcomes: Studenis will beable to understand the analysis and syathesis of expressions,“pak -tdag © POD) gt Coe <0) 4 « ; @ \ € a0 4 gan @ : czDate of Performance ‘Worksheet of the student feetenaaten Shomer: Alen: ? Onsarvation Table: For sodving ihe Lenonng axes ABTA CHIC=ABLAC ° 0 ° 0 \ \ \ | CH eumr we — Leaning Outcomes what have ea: S| 8 enn Muon Le ABLMC +BG = AB* Re. tebeteadinnr Foam Understanding of the student about the pi il [com of experiment, Discipline and tessFXOR (Pe Ag) B {old A | | i) 0 | 0 oO) | 0 | 0 ‘| 7 eoCin is a bit carried in from the next less significant stage. The full-adder is usually a componecst ina caseade of adders, which add 8, 16, 32. etc. binary numbers. The circuit produces & two-be output sum typically represented by the xignally Count and §, In this implementation, the final OR gate befure the carry-out output mey be replaced by an XOK yale without altcring the resulting logic. Using only two types of gates is. conveniens if the it is being implementea using simple IC chips which contain only ore gate type per ezip. In this light, Cout can be implemented as. A full adder cun be constructed frum tmo half adders by connecting A and B to the input of one half adder, connecting the sum from that tw an inpan 1 the second adder, connecting Ci to the other input and OR the two carry outputs. Equivelently, S could be made the three-bit XOR of A, B and Ci, and Cout could be made the three-bit majorizy function of A, B, and Ci, Full Adkder using lialf adders: 5 e fa sing X— OR and Basic Gates to implement Full Subsractor:As M0 ine case OT Ine addition using logic Se racatincnee ‘gates, a full subsractor is made by comovery my isi . ra an additional OR-gate. A full subtrctor as the boro in capability (denoted as pti sJagram below.) and $9 allows cascading which nsuls in the possibilty of mui subtraction. The circuit diagram for a full suberactor is yiven below. eo testa Sclaractor Sataracer 3. Procedure: 1. Verify the gates. 2. Make the connections as per the circuit diagram 5 Switch on VCC and apply various combinations of input according to the truth table, 4. Note down the output readings for half full adder sum and the cary bit for different. combinations of inputs. 6, Cautions: {Tha not press the IC on breadboard until pins are aligned with pours. 2. Make connection properly. 3. There should not any short circuit in the circuit. 4. Avoid the heating of IC. =) -easlt ha able tn uiniterstand the implementation of adders withayia eurnenneys we sine eee . Aim to cLsig we @ Crcait for pull adcish Observation Tal o ° \ \ ° ° 17? | | = $s o,-—| = nals aa , ~~ _ ART ACiat B H a 2 oP 3 223 4es apes, » Sub RRS ay rt % a ais rst * awl anal oxilfal ou ont “ifn amt SN a es at \S s 4 . : \S zs | a Lapel NN st | vy CoO oF : Tp hBO - sy par el Hee us @aauloooo-- — mn L ee \Zio —o orn a ©Experiment-3 1. Aim: To design a circuit to Implement Boolean fanetions using Multiplexers. ‘Apparatus required: Multiplexer ICs (dual 4:1 mux 74153),7404, Chords. 2. Learning objectives: 8) How to realize fmctionality of Dual 4 Line to | Line Multiplexer using 74153 IC. >) How Dual 4 Line to | Line Multiplexer select the particular input to be sent to the output 3. Theory: In quite often happens, in the design of large-scale digital systems, that Hine is required to carry two or more different digital signals, Of course, only one signal nt a time can be placed on the one line. What is required is a device that will allow us to select, at different instants, the ‘signal we wish to place on this common line. Such a circuit is referred to.as a Multiplexer. ‘A multiplexer performs the function of selecting the input om any one of ‘n' input lines and feeding this input to one output line, Muhiplexers are used as one method of reducing the number of integrated circuit packages required by a particular circuit design. This in tum reduces the cost of the system. Assume that we have four lines, CO, C1, C2 and C3, which are to be multiplexed on a single line, Output (¥}. The four input lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs is to appear at the output. Call these select lines A and B. The gate implememation of a 4-line to 1-line multiplexer is shown below: 263 207 201 1c1 100to be the data variaore der the faction: In this example we could have picked any variable the data variable. The Consi ‘Gite other two as selet variables, Suppote one were to take A as fexresponding Kamaugh map is then: 9 BC 4 BC F A 3c 1 BC B c Alternate method: 4:1 mux: F(A,B,C)* 2135.6) itcan be implemented using a multiplexer with the given function as shown Implementation of a following function using ‘The given function has throe variables. Hence, eo selet inputs and four data inputs, The implementation table of in table below: Do Dy D; Dy ee 0 a) 2 ey A 4 6) @ 74, Procedure 4) At first go through the structure of 74153.Then apply high level voltage to. Vec and low level voltage to GND. If Vee and ground are not connected properly then errac message will be shown and no output will be generated. b) Next, apply high level voltage to StrobelG or strobe 2G. If STROBE 1G is low, Ist Multiplexer is activated. If STROBE 2G is low, then 2nd Multiplexer is activated. c) Next, apply low level voltage to the select inputs A and B (A Most Significant Bit, B Less significant bit). Then apply a high level voltage to 2C0. Now check that how Dual 4 Line to | Line Multiplexer select the particular input to be multiplexed and to be applied to the output TY (t= 1,2). 4) For all the combinations of the select inputs A, B verify that both the LEDs are glowing or not glowing, If the LED glows, it indicates that the corresponding outpul has resched logic | level. Similarly, a dark LED indicates low level output voltage. ¢) If both the Strobe inputs are low then both Multiplexers are activated. 5. Cautions: a 1. Do not press the IC on breadboard until pins are aligned with pours. 2. Make connection properly. . 3. There should not any short circuit in the circuit. 4. Avoid the heating of IC. Bay3s = £U904,9), te Gis. “él 3569 2 = 3 (ABEa MogTOPLEXER MiMpoxorg cao ICs vod 6 5 Qundien Q adatling a dent M Ing, RS nbSpice ene Beck Bena iclabanone rr 949 Maheet of the student Registration Number. BUY wow wm Yo ate a Gizounil K 1S nen STEEN in Lmytifhone embQermaml beleas oo} yr ucvop-O x|--;+-go009 KOO GOPOr 0 ws more heondog ou CGOGA Leaming Outcomes (whatthave tant: 2ocrmy YO vf Pans Te coritiaud) - adda Tobe filied in by Facuit) Understanding of the student about the procedure/apparaius. Observations and analysis including leaning: Outcomes Signature of Faculty Completion® of experiment, Discipline and Cleanliness rflow to realize functionality of a 3. the two-avtive low and one active hi be low. The eight active low in puts (YO to Y7) cor z . ; rTespond to ei we sons component of tle corresponding min terns moar Moonen of CBA=C+Bt+A, . For example, YO = componentG2A GIR Gg 2BGicR LoL Hog so Loc weeee 1| Y2Y3 Yays v6 y7 Ltnueseioipi its LL O10 1 tay i? Loe Now, 1 Voy, iia Lt Hoo, : toin i) Lo. Noi. | ' borda L Hlioy ii Pioud Hid, by Ci taa litide 4.Procedure 1. At first 20 through the structure of 74138, ion evel vollage to GND aan also apply ee a voltage to VCC and apply 2. Next, apply low level voltage to all the three jw sate Other outpuls are at high state, Select inputs (C B A), Now check that YO is a 4, Apply low level voltage to C and B and appl i Jowstate. Other outpuls are at high state. y high level voltage to A. Now check that Y1 is at 4. Apply low Ievel voltage to C and A and apply high level voltage to B. Now check that Y2 is at {ow state. Other outputs are at high state. 5. Apply low level voliage to Cand apply high level voltage to B and A, Now check that Y3 is at Jow state, Other outputs are at high state, 6, Next, apply high level voltage to C and apply low level voltage to B and A. Now check that Y4is at low state, Other outputs are at high state, 7LApply high level voltage to C and A and apply low level voltage to B. Now check that Y5is at Jow state. Other outputs arc: at high state. {Next apply high level voltage to C and B high and apply low level voltage to A. Now check that Y6 is at low state, Other outputs are at high stale. 9. Nex|, upply high level voltage to all the select inputs sate, Other outputs are at high state. (CBA). Now check that Y7 is at low $.Cantions: 1, Do not press the IC on breadboard unt 2. Make connection properly. 3. There should not any short eH 4, Avoid the heating of| Ic. {ll be able to ‘understand i pins ae aligned with pours. reuit in the circuit. the analysis and synthesis of logic 6. Leaming Outcomes: Studeats W' fimetions with the help of devoders-erecta Loarming Outcomes fwhat | have learnt): A dotedin of FC uml F4VGI. {4 is 3: & (Frpd Cushy Bimpur (8,0,6) ema oudbed Coyt) - BF imebls au mae giuen Bru Of whith Ihe givin high asd vethege amd Mat out Gpoumdid . Boolean winds Arnrn Hebh is mack fo find te arET vd Gnd sonaat tomy erm Oudbuk ik pod Hasigh dageud ger de Lmblomint te ooken sacbress ion Ta be filled in by Fac Dinervonons enw analysis including leaning OuigomesExperimen, _ Aim: To implemen, And sim a o salen, ulate the Combination Equipments Required: Laptop with DSCH/Proteus insta 2. Leaming Objectives. This experi Snables a stud; * How to implement the combi and seque * Student will learn the Simulation Of the digital cj * Students will learn the Software Usage in circuit 3. Outline of the Procedure: |. Open the DSCH so PAYEE Fe eoEevEres Fig 1. Symbol LibraryPTET SErtExperiment 6 1. AIM: The Aimm of the exper Fup. SSD Srimment i to fully understund the functionality of J-K Flip- Apparatus required: 1C 7409, 1¢ 7410, Power supply and LEDs. 2, Learning Objectives: How to real eae ae at ic fli sia lize the functionality of sequential circuits using basic flip- 3, Theory The logic cireuits whose outpus at any instant of time depend not only on the preset inpot but also on the past outputs are called sequential circuits. The simplest kind of sequential cireuit which is capable of storing one bit of information is called latch, The operation of basic latch can be modified, by providing nn additional control input that determines, when the state of the circuit is to be changed, The latch with additional control input is called the Flip-Flop. The additional control input is either the clock or enable input. [)+-° CLK. Rs Fig 1:J-K Flip flop using NAND gate Je of J-K Flip Flop und Pin configuration of 7410 Fig 2; Truth Tab!ee SS Tine Figure 3: Typical wave-form in JK, FlipFlop 4, Procedure 1, At first apply high voltage to Voc] & ‘Ver? So that the "Clock Start" button ill be enabled. 2. Neat, start the clock pulse by clicking on the "Clock Start" ina a thr esas fon Clock pulses stop the clack pulse by clicking on the" clock Stop” button, 3. Now apply high voltage to D input and set "No of clock pulses” to 1 See the changes at output (Qand Q) at positive clock edge. 4. Now apply low voltage to D input and start the clock pulse. See the changes at output (Q and Q) at positive clock, edge. 5. Cautions; 1. Do not press the IC on breadboard until pins are aligned with pours, 2. Make connection properly, 3. There should not any short circuit in the cireuit. 4, Avoid the heating of IC. 5. Provide proper clack pulse. 6, Learning Outcomes: Student will be able to leam working of flip flop"talewatcn Hummer Leorning Outcomes: (what | ‘have leamt): am Ang wachohment § haw Axor tre tug Y-T-« Ap plop ond Vis Mun oh Sh ore ge Abit OT hae Oy 9 trond how 40 Us Te gnig Bhi GX now kod hous Tou WG Ee el OA women Sto In O-0 Limi 4 To be titled in by FaguityHib Get 7 ma wo_ brs tond Comadin 8 @Experiment 7 ‘o design #3 bit binary up/down counter using Nip flop, ss required: IC. 741.876, Power supply, [LEDs and Function gencrator. ng Objectives: To lear to realize the functionality of sequential circuits using basic 1: A sequential circuit that goes through a prescribed sequence of states upon the jon of input pulses is called a counter. The input pulses, called count pulses, may be ulses. Ina counter, the sequence of states may fallow a binary count or any other ze of states. Counters are found in almost all the equipment containing digital logic, They d for counting the number of occurrences of an event and are useful for generating liming ces to control operations in a digital system. Present State Nes State 000 ooo oot os (1m) oor ota o1a oil oie roo (wo) 440 tou bot tot 110 ro rat ria oo ay binary up counter Fig: Truth Tabe of 3-bt binary comet 3-bit bi = State diagram of Procedure: Design the ere s given Bedlagram of 3 bil up counter res on = 7 tee Ip Lee nt 7 ir eur +l 7 cweit diagram of 3 bit dawn counter be LApply clock pulse of I Hz frequency and check the output on QO, Qi and Q2. S.Cautions: \.Do not press the [C on breadboard until pins ure aligned with pours. 2. Make connection properly. A There should not any short circuit in the circuit, 4 Avoid the heating of IC. 4 Provide proper clock pulse. “ eG, koa. Fos oS s 6 1 8 p 7476 4 5 z oK recray y CKPRCLR et 22 © Leaeyy, Pit Configuration of IC 7476. _ Pin configuration of IC 4027 Ohttene a Sit idan eft eaeGT op cuits ig EK Gt Gt Ss a couthes ool wad GH cased Gem decioned) «0 (000) to 4 Cm), Ming TK Gp Gb 1 og Bo & £ E ze i (we *| 2, | | > eo f° oF Y € = = Sr a ae L \ yu f- v 2 [= | 9 7 5 ~) . | 2 8poaretermense ee fo AHH 2 B kee 4 eto 8 . Barn uta git Op Ot onservasan Table BR Coum day Reghatrtan Mente op ‘1 Laaming Outcomes (what | poo ob Te {Up phe é me Gouri « wv\ boy . Harteverator. 1g Objectives: To design decade counter using binary counter and display it on seven . A decade counter requires resetting to zero when the output count reaches the decimal 10, Le. when 1010 and to do this we need to feed this condition back to the reset input. er with a count sequence from binary 0000 through to TOOL is generally referred to as a inary code decimal counter because its ten state scquences is that of BCL) colle. In Far 13534 e6rl 4. Procedure: 1. Connect the eireuit 35 given below.» Apply clock pulse of Frequency 1 Hz 3, Check the output on seven Segment display for every clock pulse. 5, Cantions: Connect all wire connection Properly and provide proper input sequence. 6 Teaming Qhitcamess Student vill be aki. ee arm |v oO Q e o ~ X A Ay