Computer Design Supervision 3

Thomas Patterson
30 October 2020

Question 1
1.a
Machine mode is the highest privilege level, then Hypervisor, Supervisor and User modes
in that order.

1.b
We can implement instead a multi-level page table, where we have a page table with
entries pointing to other page tables. This means we only have to actually store 2nd
level page tables if they are populated, saving on space. We can use the first half of the
address to index into the first level, and the second half to index into the 2nd level page
table once we have found it. This principle can be extended to more levels than just 2.
Alternatively, we can implement the page table as a hash table, hashing the virtual page
number, and storing the original VPN with the data, so we can verify we have found
the correct entry. For sparse page tables this can drastically reduce the amount of space
needed.

1.c
A superpage is a larger page size, often equal in size to a page of pages. For example,
if the normal page size is 4kb, then the superpage might be 4mb. Having larger pages,
known as superpages, means that we can cache a larger region of memory in the TLB
only using up a single entry, whilst still allowing smaller, regular pages in most cases
when we do not need such a large block of contigous memory.

1.d
We access the TLB when trying to translate a virtual address to a physical address. The
TLB stores a cache of PTEs and is very fast to access, so we look into the TLB first, and
only on a miss do we access the page table.

1.e
Ordinarily, we need to perform two memory reads to access a piece of data in memory -
one to find the PTE and another to read the actual data. However, the TLB allows us

1
to skip this first step on a TLB hit. As long as the miss rate isn’t abysmal therefore, this
should speed up memory access.

Question 2
2.a
When the system boots, all entries in the TLB will be set to invalid, as none have been
placed there yet. So then the absence of a valid bit indicates that no translation has yet
been stored in that entry. Alternatively, on a context switch, instead of removing all the
current entries from the TLB, we may simply set all the valid bits to 0, to indicate that
they are now outdated, as we now have a new virtual address space and thus a new set
of translations.

2.b
We try to find VA Page 30 in the TLB, however it is not there so we can’t. Instead we
look it up in page table, finding the PTE. We may then swap this PTE into the TLB,
replacing a victim page, most likely entry 2 since it is not valid anyway. From the PTE,
we get the physical address and so can write the data that we need to memory.

2.c
VA Page will be looked up in the TLB. We will find it this time, but see that the protection
bits are set such that we cannot write to this page. Therefore we would throw an illegal
instruction exception. (If we had sufficient permissions we would just take the physical
address PA Page 32 and proceed as in 2.b)

Question 3
Each process has its own virtual address space, but there is only one TLB. Therefore, we
can store an Address Space Identifier in the TLB entry to indicate which process/address
space it belongs to, so that we can stop one process from access the memory of another
process via the TLB, without having to delete the whole TLB on every context switch.

2008P6Q2
4.a
RISC - Reduced Instruction Set Computing, CISC - Complex Instruction Set Computing.
RISC has less, simpler instructions, with each instruction taking an equal number of clock
cycles to complete. This simplicity makes decoding instructions simpler and quicker, and
the equivalence of runtimes make pipelining much more feasible. By contrast, CISC
contains many more much more complex instructions, with each instruction taking a
variable number of clock cycles to complete. For example, an ADD instruction will be
much faster than a MULT instruction, but both are present in most CISC ISAs. This
means that not only is decoding itself much more complex, but pipelining is a lot harder,

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and gives lesser perfomance gains, as faster instructions will have to wait for longer ones
to complete.

4.b
An operand stack will likely use less memory per instruction than the register file. This
is because register file implementation needs to indicate which registers are to be used in
each instruction, whereas an operand stack instruction will just use the first x items in the
stack, where x is determined by the opcode. This means that the operand stack will have
a much higher code density, achieving the same result as the register file implementation
with a lower program size.

4.c
Accumulator machines only have a single register, the accumulator, in which to store
intermediate results. This means that more instructions will be needed to store any
additional intermediate results, or to indicate where to find a second operand for an
instruction. This means the accumulator machine will have much lower code density
that the stack machine.

4.d
We may decide to use 4 bits each for the source registers and just 3 bits for the desti-
nation register, defining that only the first 8 registers may be used to store results from
instructions. This would mean that 16 registers can be specified as sources but only 3 as
destinations. I’m not really sure what else can be said for this question.

5
A capability is a primitive type which stores a bounds-checked pointer. A normal 64 bit
pointer is stored as a capability in 128 bits, with the extra 64 bits used for permission
bits, the object type and the bounds information. We only allow the memory access
if the address is withing the bounds (and the permissions allow it). We only allow
the permissions/bounds to be decreased but never increased to maintain integrity. I
don’t really understand the purpose of storing the object type, or really what the object
being referred to it. Capabilities are used to protect against attacks via memoory safety
violations e.g. heartbleed.