DLD - Lec 4

University of Engineering and Department of Computer
Technology, Taxila Science, UET Taxila
Digital Logic & Design

Dr. Farrukh Zeeshan Khan
April 24, 2017 Department of Computer Science, UET Taxila 1

Outline
• Combinational Circuits
• Analysis Procedure
• Design Procedure
• Code Conversions
• Binary Adder-Subtractor
• Decimal Adder
• Binary Multiplier
• Decoders
• Encoders
• Multiplexers
• Three State Gate
• HDL for Combinational Circuits

Combinational Circuits

Introduction
• Logic circuits for digital systems may be either combinational or
sequential.
• A combinational circuit consists of logic gates whose outputs at
any time are determined from only the present combination of
inputs.

Combinational Circuits
• A combinational circuits
– 2n possible combinations of input values
Block Diagram of Combinational Circuit
• Specific functions
– Adders, subtractors, comparators, decoders, encoders, and multiplexers
– MSI circuits or standard cells

Analysis Procedure

Analysis Procedure
• To obtain the output Boolean functions from a logic diagram,
proceed as follows:
• Step 1: Label all gate outputs that are a function of input
variables with arbitrary symbols – but with meaningful names.
Determine the Boolean functions for each gate output.
• Step 2: Label the gates that are a function of input variables
and previously labeled gates with other arbitrary symbols.
Find the Boolean functions for these gates.

Analysis Procedure (cont.)
• Step 3: Repeat the process outlined in step 2 until the outputs
of the circuit are obtained.
• Step 4: By repeated substitution of previously defined
functions, obtain the output Boolean functions in terms of input
variables.

Analysis Procedure Example
• A straight-forward procedure

• Step 1:
– F2 = AB+AC+BC
– T1 = A+B+C
– T2 = ABC
• Step 2:
– T3 = F2'T1
• Step 3:
– F1 = T3+T2

• Step 4:
F1 = T3+T2 = F2'T1+ABC
= (AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C')(B'+C')(A+B+C)+ABC
= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC
= A'BC'+A'B'C+AB'C'+ABC

Truth Table

Design Procedure

Design Procedure
• The design procedure of combinational circuits
• Step 1: State the problem (system spec.)
• Step 2: From the specifications of the circuits, determine the
required number of inputs and outputs and assign a symbol to
each.
• Step 3: Derive the truth table that defined the required
relationship between inputs and outputs

Design Procedure (cont.)
• Step 4: Obtain the simplified Boolean functions for each

output as a function of the input variables.
• Step 5: Draw the logic diagram and verify the correctness
of the design (manually or by simulation).

Design Method and Constraints
• Functional description
– Boolean function
– HDL (Hardware description language)
• Verilog HDL
• VHDL
– Schematic entry
• Logic constraint
– number of gates
– number of inputs to a gate
– propagation delay
– number of interconnections
– limitations of the driving capabilities
Code Conversions

BCD to Excess-3 Code Conversion

BCD to Excess-3 Code Conversion K- map
• For each symbol of the Excess-3 code, we use 1’s to draw the map for simplifying Boolean function.

BCD to Excess-3 Code Conversion K- map (cont.)

BCD to Excess-3 Code Conversion
• Simplified functions
z = D‘
y = CD +C'D'
x = B'C + B'D+BC'D'
w = A+BC+BD
• Efficient implementation
z = D'
y = CD +C'D'= CD + (C+D)‘
x = B'C + B'D+BC'D' = B'(C+D) +B(C+D)'
w = A+BC+BD= A+ B(C+D)

Logic Diagram for BCD to Excess-3 Code Converter

Binary Adder-Subtractor

1-Bit Half Adder
• A combinational circuit that performs the addition of
two bits is called a half adder.
– 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = (10)2
– two input variables: x, y
– two output variables: C (carry), S (sum)
– truth table
• S = x'y+xy'=xy=(x+y)(x'+y')
• C = xy= (x'+y')'
• S' = xy+x'y'
• S = (C+x'y')'

Logic Diagram of 1-Bit Half Adder

1-Bit Full Adder
• One that performs the addition of three bits(two significant bits and a previous carry) is a
full adder.
– The arithmetic sum of three input bits
– three input bits
• x, y: two significant bits
• z: the carry bit from the
previous lower significant bit
– Two output bits: C, S

Simplified Expressions

Logic Diagram of 1-Bit Full Adder
1-bit Full adder (Sum, Carry)

Another implementation
• Full-adder can also implemented with two half adders
and one OR gate
• S = x'y'z+x'yz'+ xy'z'+xyz
= x’(y  z) +x(y  z)’ = x  y  z
• C = xy + xz + yz
= xy + xyz + xy’z + xyz + x’yz
= xy + z (x  y + xy)
= xy + z (x  y)

4-Bit Full Adder
• Binary adder
• This is also called Ripple Carry
Adder ,because of the construction
with full adders are connected in
cascade.

Carry Lookahead Adder
• Given Stage i from a Full Adder, we
know that there will be a carry
generated when Ai = Bi = "1",
whether or not there is a carry-in.
• Alternately, there will be a carry
propagated if the “half-sum” is "1"
and a carry-in, Ci occurs.
• These two signal conditions are called
generate, denoted as Gi, and
propagate, denoted as Pi respectively
and are identified in the circuit.

Carry Lookahead Adder
• In the ripple carry adder:
– Gi, Pi , and Si are local function to each cell of the adder
– Ci is also local function for each cell
• In the carry lookahead adder, in order to reduce the length of the
carry chain, Ci is changed to a more global function spanning
multiple cells
• Defining the equations for the Full Adder in term of the Pi and Gi :

Boolean functions
Pi = A i ⊕ Bi steady state value
Gi = AiBi steady state value
Output sum and carry
Si = P i ⊕ Ci
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
• C3 does not have to wait for C2 and C1 to propagate

Logic diagram of carry look-ahead generator
• C3 is propagated at the same time as C2 and C1.
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4-bit adder with carry lookahead
April 24, 2017 35

Carry Lookahead Adder - more…
• This lookahead scheme could be extended to more than four bits; in practice, due to limited gate
fan-in, such extension is not feasible.
• Instead, the concept is extended another level by considering group generate (G0-3) and group
propagate (P0-3) functions:
• Using these two equations:
• Thus, it is possible to have five 4-bit carry lookahead generator circuit to speed up 16-bit addition
(see next slide).

16-bit 2-Level Carry lookahead Adder
G0-15 P0-15
4-Bit Adder/Subtractor
• A-B = A+(2’s complement of B)
• 4-bit adder-subtractor
– M=0, A+B; M=1, A+B’+1
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Overflow Discussion
• Overflow is a problem in digital computers because the number of bits that hold
the number is finite and a result that contains n+1 bits cannot be accommodated.
– The storage is limited.
– Add two positive numbers and obtain a negative number
– Add two negative numbers and obtain a positive number
– V = 0, no overflow; V = 1, overflow
• Exanple:

Overflow on signed and unsigned
• When two unsigned numbers are added, an overflow is detected from the end
carry out of the MSB position.
• When two signed numbers are added, the sign bit is treated as part of the
number and the end carry does not indicate an overflow.
• An overflow can't occur after an addition if one number is positive and the other is
negative.
• An overflow may occur if the two numbers added are both positive or both
negative.

Decimal Adder

BCD Adder
• Add two decimal digits in BCD together with an input carry from a previous stage
– 9 inputs: two BCD's and one carry-in
– 5 outputs: one BCD and one carry-out
• Design approaches
– Since each input digit does not exceed 9, the output sum cannot be grater than 9+9+1 =19, where 1
denotes an input carry.
– A truth table with 19 entries
– Use two 4-bit binary full adders
• Modifications are needed if the binary sum > 9
• modification: +6
Truth Table of BCD Adder
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Logic Diagram of BCD Adder BCD BCD
• A decimal parallel adder that adds

n decimal digits needs n BCD adder
stages.
• The output carry from one stage
must be connected to the input carry
of the next higher-order stage.

BCD OUTPUT
Binary Multiplier

Binary multiplier
• Usually there are more bits in the partial products and it is necessary to use full adders
to produce the sum of the partial products.
April 24, 2017 46

4-Bit by 3-Bit Binary Multiplier
• For J multiplier bits and K multiplicand bits we need (J X K) AND
gates and (J − 1) K-bit adders to produce a product of J+K bits.
• K=4 and J=3, we need 12 AND gates and two 4-bit adders.

4-Bit by 3-Bit Binary Multiplier
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Magnitude Comparator
• The equality relation of each pair of bits can be expressed logically with an exclusive-NOR function as:
A = A3A2A1A0 ; B = B3B2B1B0
xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3
(A = B) = x3x2x1x0
• We inspect the relative magnitudes of pairs of MSB. If equal, we compare the next lower significant pair
of digits until a pair of unequal digits is reached.
• If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B.

(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0
Logic Diagram of
Magnitude Comparator

Decoder

Decoders
• The decoder is called n-to-m-line decoder, where m≤2n .
• the decoder is also used in conjunction with other code
converters such as a BCD-to-seven segment decoder.
• 3-to-8 line decoder: For each possible input combination, there
are seven outputs that are equal to 0 and only one that is equal
to 1.

Decoders
• An n-to-m decoder
– a binary code of n bits = 2n distinct information
– n input variables; up to 2n output lines
– only one output can be active (high) at any time
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Three-to-Eight Line Decoder

Decoder with enable input
• Some decoders are constructed with NAND gates, it becomes more economical to generate the
decoder minterms in their complemented form.
• As indicated by the truth table , only one output can be equal to 0 at any given time, all other outputs
are equal to 1.
Two-to-four-line decoder with enable input

Demultiplexer
• A decoder with an enable input is referred to as a decoder/demultiplexer.
• The truth table of demultiplexer is the same with decoder.

Decoder with Enable /Demultiplexer

3-to-8 decoder with enable implement the
4-to-16 decoder
• 4  16 decoder constructed with two 3  8 decoders
April 24, 2017 58

Combinational Logic Implementation Full Adder
• Each output = a minterm
• Use a decoder and an external OR gate to implement any Boolean function of n
input variables
• A full-adder
– S(x,y,x)=S(1,2,4,7)
– C(x,y,z)= S(3,5,6,7)

Encoder

Encoder
• An encoder is the inverse operation of a decoder.
• We can derive the Boolean functions by table 4-7
z = D1 + D3 + D5 + D7 The encoder can be
y = D2 + D3 + D6 + D7 implemented with three
x = D4 + D5 + D6 + D7 OR gates.
April 24, 2017 61

Encoder
• An implementation
x=D4+D5+D6+D7
y=D2+D3+D6+D7
z=D1+D3+D5+D7
– Limitations? Your Task…

Priority Encoder
– Resolve the ambiguity of illegal inputs
– Only one of the input is encoded
– D3 has the highest priority
– D0 has the lowest priority
– X: don't-care conditions
– V: valid output indicator
• V=0no valid inputs
• V=1valid inputs
– X’s in output columns represent don’t-care

conditions
– X’s in the input columns are useful for representing
a truth table in condensed form. Instead of listing
all 16 minterms of four variables.
4-input priority encoder
• Implementation of table 4-8
• x = D2 + D 3
• y = D3 + D1D’2
• V = D 0 + D1 + D2 + D3
April 24, 2017 64

Multiplexer

Multiplexer
• Select binary information from one of many input lines and
direct it to a single output line
• 2n input lines, n selection lines and one output line
• E.g.: 2-to-1-line multiplexer

Multiplexer
S = 0, Y = I0 S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1
April 24, 2017 Two-to-one-line multiplexer 67

4-to-1-Line Multiplexer
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Quadruple 2-to-1 Line Multiplexer
• Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic.
Compare with Fig4-24.
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Boolean Function Implementation Using MUX
• MUX: a decoder + an OR gate

• 2n-to-1 MUX can implement any Boolean function of n input variable.
• Procedure:
– assign an ordering sequence of the input variable
– the rightmost variable (D) will be used for the input lines
– assign the remaining n-1 variables to the selection lines w.r.t. their corresponding
sequence
– construct the truth table
– consider a pair of consecutive minterms starting from m0
– determine the input lines

Boolean Function Implementation Using MUX
• Example: Given F(x,y,z) = (1,2,6,7)
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4-input function with a multiplexer
• Example: Given F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
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Three State-Gates

Three-State Gate
• A multiplexer can be constructed with three-state gates.
• Output state: 0, 1, and high-impedance
Graphical Symbol for a Three-State Buffer

Four-to-One-Line Multiplexer

HDL for Combinational
Circuits

HDL for Combinational Circuits
• A module can be described in any one of the following modeling
techniques:
1. Gate-level modeling using instantiation of primitive gates and
user-defined modules.
2. Dataflow modeling using continuous assignment statements with
keyword assign.
3. Behavioral modeling using procedural assignment statements with
keyword always.

Gate-level Modeling
• A circuit is specified by its logic gates and their interconnection.
• Verilog recognizes 12 basic gates as predefined primitives.
• The logic values of each gate may be 1, 0, x(unknown), z(high-impedance).

Gate-level description on Verilog code
The wire declaration is for internal connections.

Design methodologies
• There are two basic types of design methodologies: top-down and
bottom-up.
• Top-down: the top-level block is defined and then the sub-blocks
necessary to build the top-level block are identified.(Fig.4-9 binary
adder)
• Bottom-up: the building blocks are first identified and then combined
to build the top-level block.(Example 4-2 4-bit adder)

A bottom-up hierarchical description

Full-adder

4-bit adder

Three State Gate
Gates statement: gate name(output, input, control)
>> bufif1(OUT, A, control);
A = OUT when control = 1, OUT = z when control = 0;
>> notif0(Y, B, enable);
Y = B’ when enable = 0, Y = z when enable = 1;
April 24, 2017 84

2-to-1 multiplexer
• HDL uses the keyword tri to
indicate that the output has
multiple drivers.
module muxtri (A, B, select, OUT);

input A,B,select;
output OUT;
tri OUT;
bufif1 (OUT,A,select);
bufif0 (OUT,B,select);
endmodule

Dataflow modeling
• It uses a number of operators that act on operands to produce desired results.
Verilog HDL provides about 30 operator types.
Table 4-10
Symbol Operation
+ binary addition
− binary subtraction
& bit-wise AND
| bit-wise OR
^ bit-wise XOR
~ bit-wise NOT
== equality
> greater than
< less than
{} concatenation
?: conditional
Dataflow modeling
• A continuous assignment is a statement
that assigns a value to a net.
• The data type net is used in Verilog
HDL to represent a physical connection
between circuit elements.
• A net defines a gate output declared
by an output or wire.

Dataflow description of 4-bit adder
HDL Example 4-4
//Dataflow description of 4-bit adder
module binary_adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B +Cin;
endmodule

Data flow description of a 4-bit comparator

Dataflow description of 2-1 multiplexer
• Conditional operator( ? : )
• Condition? true-expression : false-expression;

Behavioral modeling
• It is used mostly to describe sequential circuits, but can be used also to describe
combinational circuits.
• Behavioral descriptions use the keyword always followed by a list of procedural

assignment statements.
• The target output of procedural assignment statements must be of the reg data type.
Contrary to the wire data type, where the target output of an assignment may be
continuously updated, a reg data type retains its value until a new value is assigned.

Behavioral description of 2-1 multiplexer

4-to-1-line Multiplexer

Writing a simple test bench
• In addition to the always statement, test benches use the initial statement to provide stimulus to the
circuit under test.
• The always statement executes repeatedly in a loop. The initial statement executes only once starting
from simulation time=0 and may continue with any operations that are delayed by a given number
of time units as specified by the symbol #.
For example:
initial
begin
A = 0; B = 0;
#10 A = 1;
#20 A = 0; B = 1;
end

Stimulus and design modules interaction
• The signals of test bench as inputs to the design module are reg data type,
the outputs of design module to test bench are wire data type.

Example 4-9

Gate Level of Verilog Code of Fig.4-2

Test Bench of the Figure 4-2

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University of Engineering and Department of Computer

Technology, Taxila Science, UET Taxila

Digital Logic & Design

April 24, 2017 Department of Computer Science, UET Taxila 1

April 24, 2017 Department of Computer Science, UET Taxila 2

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Block Diagram of Combinational Circuit

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• Step 4: Obtain the simplified Boolean functions for each

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1-bit Full adder (Sum, Carry)

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• C3 does not have to wait for C2 and C1 to propagate

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• Using these two equations:

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• A decimal parallel adder that adds

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• If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B.

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