Advanced Analog Integrated Circuits

Operational Transconductance Amplifier III

Bernhard E. Boser
University of California, Berkeley
boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

B. E. Boser EE240B – OTA III 1

 Telescopic OTA

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 Output Swing versus Gain

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 Cascoded Telescopic OTA

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 Realizing Vbias

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 Input Capacitance

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 Neutralization Capacitor Layout

• Cn
• Note that this layout
also minimizes
wiring Cgd
• For high-speed
applications

Ref: Z. Deng, Thesis, 12/2011

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 Improved Swing: Folded Cascode

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 Folded Cascode Noise

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 Advanced Analog Integrated Circuits

Slewing

Bernhard E. Boser
University of California, Berkeley
boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

B. E. Boser EE240B – OTA III 10

 Differential Pair Transconductance
Iod

Vid

-ISS

Gm

Vid

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 Initial Transient

• Differential mode half circuit:

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 Circuit Model During Slewing

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 Initial Transient

[V]

V*

0 Time

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 Linear Settling

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 Settling Time with Slewing

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 Design Procedure with Slewing

• For circuits with significant slewing (large input compared

to 𝑉 ∗ , small closed-loop gain 𝑐)
1. Start by assuming a slewing time, e.g. 50% of ts
2. Design and verify that linear settling completes within tlin (apply
only small steps during simulation to avoid slewing)
3. Now verify with a full-scale input step and check the actual ratio
of tslew/tlin
4. Iterate until the design and verification match

• Typically you get convergence in a few iterations

• Slewing is power efficient
– Entire bias current used to charge load
– But limits maximum speed

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 Advanced Analog Integrated Circuits

Two Stage OTA

Bernhard E. Boser
University of California, Berkeley
boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

B. E. Boser EE240B – OTA III 18

 Miller Compensated 2-Stage OTA

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 Process Insensitive Realization of Rz

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 Slewing in 2-Stage Miller OTA

Ref: M. Yavari et al, “An accurate analysis of slew rate for two-stage CMOS opamps,” TCAS-II, March 2005, pp. 164-7.

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 Asymmetric Slewing

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Why is Symmetric Slewing Important?

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 Advanced Analog Integrated Circuits

OTA Design Flow

Bernhard E. Boser
University of California, Berkeley
boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

B. E. Boser EE240B – OTA III 24

 Divide and Conquer Design Flow

• Determine suitable topology based on specifications, e.g.

– Single or multi-stage
– Gain boosting

• Script based design

– Step 1: small-signal
• Make reasonable assumptions (output range, L, a etc.)
• Ignore slewing
– Step 2: large-signal
• Compute slewing time (use ideal CMFB, biasing), re-optimize
• Add CMFB, verify stability and settling
– At this point your design should meet the settling and dynamic range requirements
• Add biasing, check static settling accuracy
• Proceed to layout phase: # fingers for transistors, …

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 Remedies (Examples)

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 Advanced Analog Integrated Circuits

OTA Examples

Bernhard E. Boser
University of California, Berkeley
boser@eecs.berkeley.edu

Copyright © 2016 by Bernhard Boser

B. E. Boser EE240B – OTA III 27

 High Gain

[Bult, JSSC 1992]

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 Differential Boosters

[Ahmadi, TCAS-II, 2006]

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 Boosted Boosters

[Chiu, JSSC 2004]

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 2-Stage OTA with 2 CMFB Loops

[Yang, JSSC 2001]

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2-Stage OTA with Ribner Compensation

[Abo, JSSC 1999]

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 Simpler?

pseudo-differential

[Nauta OTA, Irfansyah, 2014]

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 Differential & Low Power

[Groenen, ISSCC 2016]

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