UNIT - IV

1. When comparing PIC16C7x with PIC16C6x, the enhanced capability is

a) digital-to-analog
b) analog-to-digital
c) encoding
d) decoding
2. The number of instruction set that the PIC microcontroller has is
a) 35 b) 34 c) 31 d) 45
3. The PIC microcontroller family uses which architecture?
a) Harward b) Von-Neumann c) Array d) Pipelining
4. In PIC microcontroller, group of locations of memory are termed as , which can be
accessed through various instruction.
a) Register find b) Register file c) Register Locate d) Register Identify
5. In the PIC microcontroller, the register bank which has 32 bytes of special purpose registers is

a) Bank 0 &1 b) Bank 1 & 2 c) Bank 0 & 2 d) Bank 0, 1 & 2

6. In PIC microcontroller, The W register serves the purpose similar to of 8085
microprocessors.
a) Program counter b) Instruction register c) Accumulator d) ISR
7. In PIC microcontroller, the watchdog timer can be cleared using the instruction
a) clcwd b) clrwdt c) clrwd d) wdtclr
8. What is the length of PCLATH?
a) 13 b) 8 c) 5 d) 4
9. The RP0 bit in PIC microcontroller is in register.
a) Flag b) Status c) FSR d) INDF
10. In PIC microcontroller, if there is any carry from lower nibble to higher nibble bit of
STATUS register becomes set.
a) AC b) CY c) DC d) OV
11. Identify the instruction of PIC which increment f, putting result in F or W is
a) inrf f,F(W) b) incf f,F(W) c) inf f,F(W) d) inxf f,F(W)
12. The instruction addlw of PIC microcontroller affects the status bits.
a) C, DC, Z b) C, Z c) C, AC, Z d) C, DC
13. The instruction of PIC16Cxx that tests the ‘b’ bit of ‘f’ register, where b = 0 to 7 and skip when it
clear is
a) btfss b) btfsc c) btccc d) btsss
14. Identify the correct instruction of PIC which AND literal value into W from the following
a) andlw b) andwf c)andff d)andwl
15. In PIC16Cxx, return from ISR; reenabling interrupts is being done by instruction.
a) return b) retlw c) retfie d) retei
16. The PIC16C7x has I/O Ports
a) 5 b) 6 c) 4 d) 0
17. Setting the TRISB of PIC16F877 microcontroller will make the respective port pin as pin
a) output b) input c) toggle d) reset
18. The 28 pin and 40 pin PIC microcontrollers have number of I/O ports
respectively. a) 3 & 5 b) 4 & 8 c) 6 & 12 d) 2 & 6
19. In PIC microcontroller, GIE stands for
a) Gain input enable b) Gain interrupt enable
c) Global interrupt enable d) Global input enable
20. The alternate use of PORT D I/O pins of PIC16C7x is
a) Serial ports; Timer I/O b) A/D converter inputs
c) Parallel slave port d) External interrupt
21. Which of the following PIC microcontroller has two CCP module in it?
a) PIC16C62A b) PIC16C64A c) PIC16C72 d) PIC16C74A
22. In CCP module of PIC microcontroller, P denotes
a) Parity b) PAL c) PWM d) Priority
23. The TMR1 cannot be stopped and changed when it is used for function.
a) compare b) capture
c) compare and capture d) PWM
24. In PIC, the time of occurrence of an input edge is determined by combination of
a) Timer 1 and CCP1 b) Timer 2 and CCP2
b) Timer 1, CCP1 and CCP2 d) Timer 1 and either of CCP1 or CCP2
25. In PIC Microcontroller, the period of PWM is controlled by
a) Timer1 prescaler and PR1 b) Timer2 prescaler and PR2
b) Timer0 prescaler and PR2 d) Timer0 prescaler and PR1
26. The PIC16C6x/7x has program counter.
a) 8 bit b) 11 bit c) 12 bit d) 13 bit
27. In PIC Microcontroller, to enable the program memory from 2k to 4k, which of the following
is to be made?
a) PCLATH.3=1 b) PCLATH.1=1 c) PCLATH.2=1 d) PCLATH.4=1
28. In PIC Microcontroller, the NOT_TO and NOT_PD are bits available in register.
 a) FSR b) INDF c) STATUS d) PCLATH
29. The status of bit can be used to identify and convert the result obtained into a BCD.
a) C b) DC c) Z d) AC
30. Which of the following is not the bit of STATUS register?
a) DC b) C d) RP0 d) FSR
31. Identify the correct simpler assembler process
a) code.asm converted to code.hex converted to MCU
b) code.hex converted to code.asm converted to MCU
c) code.oct converted to code.hex converted to MCU
d) code.hex converted to MCU
32. In PIC microcontroller, which of the following is not the file structure of IDE?
a) project_name.mcp b) project.name.mcw c) project.name.mcs d) project.name.mcc
33. In half drive mode of operation of stepper motor, how the phases are energized?
a) one and two phases simultaneously b) one and two phases alternatively
b) two and three phases simultaneously d) two and three phases alternatively
34. Which mode of stepper motor operation is suitable for better power consumption?
a) Full Drive b) Wave Drive c) Half Drive d) Quarter Drive
35. When two stator electromagnets are energized at a time, the mode is called
a) Full Drive b) Wave Drive c) Half Drive d) Quarter Drive
36. In wave drive operation of stepper motor, is less when compared to full step drive.
a) current b) voltage c) torque d) speed
37. What are the special features available in PIC microcontroller for speed control of DC motor?
a) PWM generation and analog channel b) PWM generation and ADC
c) ADC and analog channel d) PWM generation and DAC
38. When we are using the PWM controller IC’s, the error% in frequency will be
a) 3-5% b) 1-2% c) 0-1% d) 3-4%
39. The pulse width modulator method that can be used for PIC controlled DC motor is
a) analog b) digital c) analog and digital d) programming
40. When interfacing the DC motor with PIC microcontroller, the back emf of the motor can
avoided by
a) H bridge b) Large inductance c) T bridge d) Small inductance
41. uses the combination of PIC microcontroller and a DAC.
a) Waveform generator b) Sinusoidal generator
c) PWM generator d) Attenuator
42. The modification of frequency and amplitude of the generated waveform using
PIC microcontroller is achieved by
a) changing the programming b) changing carrier wave
b) changing the input parameters d) changing the controller
43. R/2R resistor ladder network which is used in waveform generator is a
a) decoder b) ADC c) DAC d) multiplier
44. The frequency counter design using PIC microcontroller needs
a) Timer 0 and Timer 1 b) Timer 0 alone c) Timer 1 alone d) ADC
45. In PIC microcontroller, for a 16 bit counter the maximum measurable frequency range is
a) 0-65k b) 0-24k c) 0-30k d) 0-70k
46. The frequency counter’s maximum range can be defined by
a) counter length b) setting it the program
b) tuning the analog circuit components d) setting the oscillator frequency
47. In PIC microcontroller, Real time clock design can be used for application
a) Data logging b) Process monitoring
c) Interrupt handling d) Rebooting
48. Inter integrated circuit protocol used in of PIC microcontroller.
a) RTC b) Waveform generator c) PWM d) Counter
49. Programmable gate pulse to the switches using PIC microcontroller has
a) a drawback that frequency cannot be varied
b) a wide range of control over frequency
c) limited frequency variation
d) a fixed frequency of operation
50. By using the feedback provided, control of abnormality of power switches is possible in
a) programmed gate pulse b) SPWM gate pulse
b) RPWM gate pulse d) floating gate pulse
51. In PIC microcontroller, the instruction fetched from successive addresses like n, n+1, n+2, n+3
and soon. When the goto address location is executed after n+1, the program counter content
will have
a) n+2 b) New Address c) Old Address d) n+3
52. In PIC microcontroller, under indirect addressing mode, the full 8 bit register file address
is written first into
a) INDF b) FSR c) PCLATH d)RP0
53. In PIC microcontroller, the program counter comprises of bit PCL and bit
PCLATH.
a) 4, 8 b) 8, 5 c) 5, 8 d) 8, 4
54. In PIC microcontroller, copy the content of f in either F or W and then rotate F or W right
through carry operation is executed byinstruction.
a) rrf b) rfr c)rff d) rfc
55. In PIC microcontroller, What is the operation of btfss STATUS,z
instruction?
a) test Z bit of STATUS and will skip to next instruction if the bit is reset
b) test Z bit of STATUS and will skip to next instruction if the bit is
set
c) test Z bit of STATUS and will go to next instruction if the bit is reset
d) test Z bit of STATUS and will go to next instruction if the bit is set
56. In PIC microcontroller, which of the following instruction complement f and putting the result
in F or W?
a) compf f,F(W) b) comf f,F(W) c) cmpf f,F(W) d) cpf f,F(W)
57. In PIC microcontroller, the W register can be using the instruction
a) clear w b) clrf w c) clrw d) clr w
58. In PIC microcontroller, which of the following instruction doesn’t take more than 1 cycle
for operation on any condition?
a) goto b) call c) btfss d) rlf
59. The instruction clrw of PIC microcontroller affects the status bit(s).
a) C, DC, Z b) Z c) C, AC, Z d) C, DC
60. In PIC microcontroller, which instruction will wait for watchdog timer or external signal to
begin program execution again?
a) nop b) sleep c) resume d) clrwdt
61. In PIC microcontroller, the instruction used to set a particular bit of register is
a) bcf f,b b) bsf f,b c) bss f,b d) bff f,b
th
62. In PIC microcontroller, what is the 6 bit of STATUS register?
a) 0 b) Z c) DC d) C
63. In PIC microcontroller, the accesses the location pointed by FSR.
a) PCLATH b) INDF c) PCL d) W
64. In PIC microcontroller, the instruction bcf STATUS,RP0 is used to
a) Select Bank 1 b) Select Bank 0 c) Reset Bank 1 d) Reset Bank 0
65. In PIC microcontroller, the number of levels of stack available is
a) 4 b) 8 c) 16 d) 32
 UNIT – V
1. RISC processors were designed for
A. Main computer
B. Mini computer
C. Mobile system
D. supercomputer
ANSWER: C
2. ARM processor is a-----device
A. 8 bit
B. 16 bit
C. 4 bit
D. 32 bit
ANSWER: D
3. Expansion of RISC is
A. Restricted Instruction Sequencing Computer
B. Restricted Instruction Sequential Compiler
C. Reduced Instruction Set Computer
D. Reduced Induction sequential Computer
ANSWER: C
4. The program counter is implemented using--------------in the ARM processor
A. Caches
B. Heaps
C. General purpose register
D. special purpose register
ANSWER: C
5. ARM machine instructions are encoded with------word
A. 2 byte
B. 3 byte
C. 8 byte
D. 4 byte
ANSWER: D
6. The first ARM processor was developed at-------computers
A. Acorn
B. Intel
C. Microchip
D. Atmel
ANSWER: A
7. The ARM instruction set features
A. 5- address register instruction
B. load store architecture
C. load and store single register
D. shift and ALU operations a multiple instruction
ANSWER: B
8. Thumb instructions are used to access the ----.
A. Current program status register
B. stack pointer
C. program counter
D. addresss bus
ANSWER: A
9. ENTRY directive specifies the-------of the execution.
 A. Start
B. End
C. Main
D. Return
ANSWER: A
10. The-----------is used to switch fast and to perform better in ARM
processor.
A. Switching circuit
B. Barrel shifter circuit
C. Integrated circuit
D. Multiplexer circuit
ANSWER: A
11. Which instructions are used in ARM processor to load or store multiple operands?
A. Banked instructions
B. Lump transfer instructions
C. Block transfer instructions
D. DMA instructions
ANSWER: C
12. The main importance of ARM processor is to provide
A. low cost and low power consumption
B. High degree of multitasking
C. Efficient memory management
D. less error
ANSWER: A
13. What is the nature of instruction size in RISC processors?
A. register based
B. variable
C. time to refine
D. Unpredictable
ANSWER: A
14. How many address lines are there in ARM processor?
A. 24
B. 32
C. 16
D. 64
ANSWER: B
15. In pipelining, before decode, data is
A. fetched
B. execute
C. initialized
D. deleted
ANSWER: A
16. The Thumb instruction set is a subset of the most commonly used----ARM instructions.
A. 32 bit
B. 24 bit
C. 16 bit
D. 64 bit
ANSWER: A
17. CPSR stands for-------
A. current program status Register
B. carry program sub-register
 C. clock power status register
D. current program saved
register ANSWER: A
18. The ARM processor has--------operating modes
A. 2
B. 4
C. 6
D. 8
ANSWER: C
19. The ARM has sets of instructions which interact with main memory
A. 1
B. 2
C. 3
D. 4
ANSWER: C
20. A--------------define the current limits of the stack in ARM processor
A. stack pointer
B. data pointer
C. program counter
D. offset
pointer
ANSWER: A
21. The thumb code requires-----------of the space of the ARM code
A. 40%
B. 50%
C. 70%
D. 100%
ANSWER: C
22. In order to easily add system features like caches and memory timing characteristics is
designed
A. ARMulator
B. AMBA Bus
C. System bus
D. ARM Memory interface
ANSWER: A
23. ARM processor with Cortex-M0 core has a clock generator with clock sources
A. 4
B. 5
C. 3
D. 6
ANSWER: B
24. is not a valid ARM Instruction
A. MUL
B. MLA
C. LDR
D. MVI
ANSWER: D
25. Identify which of the below is not the addressing mode of ARM processor?
A. Immediate addressing
B. Implied addressing
C. Register addressing
D. Base plus index addressing
 ANSWER: B
26. Which of the below mentioned code is not the condition code flag of ARM processor?
A. N
B. C
C. Z
D. OV
ANSWER: D
27. In ARM processor, when two 32 bit integers are multiplied, the result obtained is
A. 24 bit
B. 26 bit
C. 27 bit
D. 28 bit
ANSWER: B
28. The register used to store the condition code bits in ARM processor is
A. APSR
B. CPSR
C. PC
D. r12
ANSWER: B
29. ARM Processor does not support operations.
A. memory to register
B. register to register
C. memory to memory
D. register to memory
ANSWER: C
30. Which of the following category is not the ARM instructions comes under?
A. Data processing instructions
B. Memory handling instructions
C. Data transfer instructions
D. Control flow instructions
ANSWER: B
31. ARM means
A. Advanced RISC Machines
B. Advanced Rate Machines
C. Advance Running Machines
D. Artificial Running
Machines ANSWER: A
32. With 32-bit memory, the ARM code is------faster than thumb code
A. 40%
B. 45%
C. 30%
D. 20%
ANSWER: A
33. ARM processor supports address system
A. Little Endian
B. Big Endian
C. X-Little Endian
D. Both Little & Big Endian
ANSWER: D
34. Throughput means
 A. One instruction per cycle
B. Three cycles per instruction
C. Two instructions per cycle
D. Average number of clock cycles per
instruction ANSWER: A
35. Identify the available stages in 3-stage pipeline
A. Decode, Write-back, and Fetch
B. Execute, Decode and Fetch
C. Fetch, execute and buffer
D. Decode, execute and
buffer ANSWER: B
36. The hardware system prototyping tools are NOT related to
A. Rapid silicon prototyping
B. AMBA
C. Providing a platform for system verification and software development
D. ARM integrator
ANSWER:
37. The ARM code can be evaluated and debugged without the processor chip using ARMulator
which is a
A. Hardware emulator
B. Software emulator
C. Firmware emulator
D. Interrupt emulator
ANSWER: B
38. Which instruction of ARM processor did not give any carry at the output of arithmetic operation?
A. BVS
B. BGT
C. BCC
D. BCS
ANSWER: C
39. In ARM Processor, the result of product of two register content can be added to another register
content is done by the instruction
A. MUL
B. MULA
C. MLA
D. MUA
ANSWER: C
40. NUC140 processor does not consist
A. More than two timers
B. Real time clock
C. Brown out reset
D. 16-bit
ADC
ANSWER: D
41. Which of the following is NOT true related to the nuvoTon –NU-LB-NUC140 processor
A. An ARM based 32-bit microcontroller
B. It is using ARM9 cpu core
C. having SRAM
D. It uses Thumb instruction
set ANSWER: B
42. In nuvoTon –NU-LB-NUC140 architecture, ‘1’ and ‘4’ represent and repectively
A. CPU core and Function
 B. CPU core and RAM size
C. Function and CPU core
D. RAM size and Function
ANSWER:
43. Which of the following ARM processor is fastest?
A. Cortex-A processors
B. Cortex-M processors
C. ARM9E series
D. ARM64FX.
ANSWER: D
44. How many registers are available in arm processor?
A. 54
B. 45
C. 47
D. 37
ANSWER: D
45. ARM7 is a----------------ARM processor
A. 32- bit
B. 8-bit
C. 16-bit
D. 64-bit
ANSWER: A
46. Which of the following interrupt input is level sensitive and maskable?
A. FIQ
B. IPR
C. IR
D. IIS
ANSWER: A
47. Which modelling presents signals at the correct time within a cycle, allowing logic delays to
be accounted for?
A. Instruction accurate modelling
B. Cycle accurate modelling
C. Time accurate modelling
D. System accurate
modelling ANSWER: C
48. Which of the following is not the instruction of ARM processor?
A. ADC
B. ADD
C. ORR
D. ANL
ANSWER: D
49. Which of the following statements are false?
(1) ARM processor with 3-stage pipeline has A bus and B bus
(2) Barrel shifter is connected to B bus

a. (1) alone is false

b. (2) alone is false
c. Both (1) and (2) are false
d. Neither (1) nor (2)
ANSWER: D
50. Which of the following statements are true with respect to ALU bus in 3-stage pipeline of ARM
organization?
(1) It is connected between Register bank and address register
(2) It is connected between B bus and ALU

e. (1) alone is true

f. (2) alone is true
g. Both (1) and (2) are true
h. Neither (1) nor (2)
ANSWER: A
51. Executing ADD ro,r1,r2 instruction using ARM processor will
i. Add the contents of registers r0 and r2 , then stores result in r0
j. Add the contents of registers r1 and r0 , then stores result in r2
k. Add the contents of registers r1 and r2 , then stores result in r0
l. Add the contents of registers r1 and r2 , then stores result in
r1 ANSWER: C
52. MVN and MOV instructions in ARM are
m. 8-bit instructions
n. Register movement instructions
o. Not used to transfer data between registers
p. 8-bit instructions
ANSWER: B
53. LSL and MLA instructions are used to and
q. Load store logic, Multiply and accumulate
r. Logical shift left, Multiply with accumulator
s. Logical store logic, Multiply and accumulate
t. Logical shift left, Multiply and accumulate
ANSWER: D
54. Identify the instruction based on the figure shown.
A. LSR
B. LSL
C. ASL
D. ASR
ANSWER: B
55. In ARM Processor, What is the operation of the instruction ADR r1, TABLE1?
A. Copies the r1 content to Table1
B. Causes r1 to contain address of data that follows Table1
C. Copies the r1 with content of Table1
D. Causes r1 to contain address of
Table1 ANSWER: B
56. Identify the instruction which transfers data to multiple registers at a time in ARM processor.
A. LDIMR r2, { r1, r3, r5 }
B. LDA r2, { r1, r3, r5 }
C. LDMIA r1, { r0, r2, r5 }
D. LDM r1, { r0, r2, r5 }
ANSWER: C
57. The ARM processor has how many general purpose registers?
A. r0 to r14
B. r0 to r15
C. r0 to r7
 D. r0 to r31
ANSWER: A
58. How many write and read ports does the PC of ARM processor has?
A. 1 and 3 respectively
B. 2 and 3 respectively
C. 1 and 2 respectively
D. 2 and 4 respectively
ANSWER: B
59. Which of the following has the highest exception priority?
A. FIQ
B. IRQ
C. Reset
D. Prefetch abort
ANSWER: C
60. The S and H bits of binary encoding in ARM processor defines
A. type of source
B. type of destination
C. type of operand
D. type of error
ANSWER: C

 1. How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
ANSWER: (a) 4
2)   Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU) of
PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
ANSWER: (d) All of the above
3)   What is the execution speed of instructions in PIC especially while operating at the maximum value of
clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
ANSWER: (b) 0.2 μs
4)   Which operational feature of PIC allows it to reset especially when the power supply drops the voltage
below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
ANSWER:  (b)Brown-out reset
5)   Which among the below stated reasons is/are responsible for the selection of PIC implementation/design
on the basis of Harvard architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above
ANSWER: (d) All of the above
6)   Which among the below specified major functionalities is/are associated with the programmable timers of
PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs

a. Only C
b. C & D
c. A, B & D
d. A, B & C
ANSWER: (d) A, B & C
7)   Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its own
on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
ANSWER: (c) Watchdog Timer (WDT)
8)   Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
ANSWER: (b) Program Counter Latch (PCLATH) Register
9)   Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the
contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
ANSWER: (a) W
10)   How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
ANSWER: (a) 1
 

11)   The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
ANSWER: (a) Direct Addressing Mode
12)   Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial for
BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
ANSWER: (b) Digits Carry bit (DC)
13)   Which statement is precise in relation to FSR, INDF and indirect addressing mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in indirect
addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect addressing mode

a. Only A
b. Only B
c. Only A & B
d. A & D
ANSWER: (a) Only A
14)   Which among the below stated registers specify the address reachability within 7 bits of address
independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
ANSWER: (d) All of the above
15)   Where do the contents of PCLATH get transferred in the higher location of program counter while
writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
ANSWER: (c) 13th bit
16)   Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
ANSWER:(b)  Low
17)   Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
ANSWER:  (a) the detection of increment in VDD from 1.5 V to 2.1 V
18)   What is the rate of power up delay provided by an oscillator start-up timer while operating at XT, LP
and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
ANSWER: (b) 1024 cycles
19)   Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
ANSWER: (b) Sleep mode
20)   What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
ANSWER: (a) For ensuring the inception and stabilization of an oscillator in a proper manner
21)   Which program location is allocated to the program counter by the reset function in Power-on-Reset
(POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
ANSWER: (a) Initial address
22)   When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
ANSWER: (b) Only if VDD power-up slope is insufficient at a requisite level
23)   Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71

a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: (b) C & D
24)   Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique and
distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
ANSWER: (a) It can reset the PIC automatically in running condition
25)   What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
ANSWER: (a) CPU resets PIC once again in BOR mode
26)   What output is generated by OSC2 pin in PIC oscillator comprising RC components for sychronizing
the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
ANSWER:(c)  (1/8) x frequency of OSC1
27)   Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources
for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
ANSWER: (b) LP (Low-Power Clocking)
28)   Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as
compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
ANSWER: (a) All of the above
29)   What is the executable frequency range of High speed (HS) clocking method by using cystal/ ceramic/
resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
ANSWER: (d) 4-20 MHz
30)   How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
ANSWER: (c) 11 & 12 bits
31)   What location is attributed to ‘goto Mainline’ instruction in the program memory of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
ANSWER: (a) 000H
32)   When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of ‘goto Mainline ‘ instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
ANSWER: (c) At the occurrence of interrupt into the program counter
33)   How many bits are utilized by the instruction of direct addressing mode in order to address the register
files in PIC?
a. 2
b. 5
c. 7
d. 8
ANSWER:(c) 7
34)   Which registers are adopted by CPU and peripheral modules so as to control and handle the operation
of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
ANSWER: (c) Special Function Registers
35)   Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
ANSWER: (a) PORTA (05H)
36)   Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of
RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
ANSWER: (c) TRISA (85H)
37)   Which bank of RFS has a provision of addressing the status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
ANSWER: (c) Either Bank 1 or Bank 2
38)   Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the
external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
ANSWER: (b) INTEDG
39)   Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
ANSWER: (c) Either RTCC or Watchdog timer
40)   Where is the exact specified location of an interrupt flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
ANSWER: (b) ADCON0
41)   Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
ANSWER: (a) GIE
42)   When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of
PICs?
a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
ANSWER: (a) Only when RPO bit is set ‘zero’
 

43)   When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt on
change’?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
ANSWER: (a) By configuring all the pins (RB4-RB7) as inputs
44)   Which digital operations are performed over the detected mismatch outputs with an intention to
generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
ANSWER: (a) OR
45)   What is the purpose of acquiring two different bits from INTCON register for performing any interrupt
operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above
ANSWER: (b) One for enabling the interrupt & one for its occurrence detection
46)   Which among the below specified combination of interrupts belong to the category of the PIC 16C61 /
71?
a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts
ANSWER: (c) External, Timer 0 & Port B Interrupts
47)   Which condition results in setting the GIE bit of INTCON automatically?
a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit
ANSWER: (b) Execution of retfie instruction at the end of ISR
48)   What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?
a. INT
b. RBO
c. INTF
d. All of the above
ANSWER:(a)  INT
49)   Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels
in external interrupts of PIC 16C61/71?
a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register
ANSWER: (b) INTEDG bit – OPTION register
50)   Consider the following statements. Which of them is /are incorrect?
a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.

a. A & B
b. C & D
c. Only A
d. Only C
ANSWER: (b) C & D
51)   What is the purpose of setting TOIE bit in INTCON along with GIE bit?
a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
d. None of the above
ANSWER: (a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
52)   Where do the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital (ADC)
conversion process?
a. INTCON
b. ADCON0
c. OPTION
d. None of the above
ANSWER: (b) ADCON0
53)   How much time is required for conversion per channel if PIC 16C71 possesses four analog channels,
each comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
ANSWER: (c) 20 μs
54)   How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’ of PIC 16C61?
a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles
ANSWER: (a) 2-cycles
55)   Which command enables the PIC to enter into the power down mode during the operation of watchdog
timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
ANSWER: (a) SLEEP
56)   Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’ respectively in
ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
ANSWER: (c) AIN2
57)   Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion in
ADCON0?
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
ANSWER: (c) Go/!Done
58)   What would be the value of ADC clock source, if both the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
ANSWER: (d) FRC
59)   The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
ANSWER: (a) PCFG1 & PCG0
60)   Which among the below mentioned aspect issues are supported by capture/compare/PWM modules
corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
ANSWER: (d) All of the above
61)   Which register is suitable for the corresponding count, if the measurement of pulse width is less than
65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
ANSWER: (c) 16-bit register