Computer Organization

and Architecture

Chapter 3 (Part I)
CPU Organization
Chere L. (M.Tech)
Lecturer, AASTU
Chapter 1 1
Outline
 Introduction
 Instruction Set Design Factors
 Operand Addressing
 CPU (ISA) Organizations
 Single accumulator organization
 General Register Organization
 Stack Based Organization
 Summary
1. Introduction
Major Components of CPU

 Storage Components: Registers, Flags

 Execution(Processing) Components: Arithmetic Logic Unit(ALU)

 Arithmetic calculations, Logical computations, Shifts/Rotates
 Transfer Components: Internal Bus
 Control Components: Control Unit

Register
File ALU

Control Unit
2. Instruction Set Design Factors
 The Instruction Set Architecture (ISA)
 Recall that ISA is the part of the processor that is visible to the
programmer or compiler writer.
 The ISA serves as the boundary between software and hardware.

 The ISA of a processor can be described and differentiated by the

following characteristics:
Operand location
Operand Storage
in the CPU

Number of explicit Types of Operation

named operands
Type and size of
Number of bits per
operands
instruction
Cont. . . Instruction Set Design Factors

 Operand Storage in the CPU

 Where are the operands kept in the CPU other than in memory?
 Number of explicit named operands
 How many operands are named in a typical instruction.
 Operand location
 Can any ALU instruction operand be located in memory? Or
must all operands be kept internally in the CPU?
 Operations
 What operations are provided in the ISA.
 Type and size of operands
 What is the type and size of each operand and how is it
specified?
3. Addressing Architectures
 Addressing architecture – defined by the number of addresses to
memories in instructions and number of Operands.
 Memory-to-memory architecture
 All operands come directly from memory, data-path has no register set.
 Not used in new designs cause accessing a memory takes a lot of time.

 Register-to-register or load/store architecture

 allows only one memory address for load & store instructions.
 It requires a register set.

 A register-memory architecture
 accesses register and memory in one instruction.
 No of instructions and accesses to memory is intermediate
Cont. . . Operand Addressing

 Implicitly addressing:
 Some operands are not explicitly addressed because their location
is specified either by the opcode of the instruction or by an address
assigned to one of the other operands.
 In such a case, the operand has an implied address.
 If the address is implied then there is no need for a memory or
register address field for the operand in the instruction

 Explicitly addressing:
 An operand has an address in the instruction
 i.e. the operand is explicitly addressed or has an explicit address.
 No of Operands that can be explicitly addressed by the instruction
is an important factor and varies amongst different architectures
Cont. . . Operand addressing categories

 On the basis of number of address (explicitly named operands or

has explicitly address) instructions are classified as:
 Three-Address Instructions
 Two Address Instructions
 One-Address Instructions
 Zero-Address Instructions

 Consider an arithmetic statement below and let’s examine how it

executed using three, two, one and zero address instructions.
X=(A+B)(C+D)
 Here A,B,C,D are symbolized memory addresses where Operands
are stored and X is the address where result is stored after the
operation
Cont. . . Three-Address Instructions
 In three-address instruction type there are 3 fields of addresses.
 Example: program to evaluate X = (A + B) * (C + D) :
ADD T1, A, B /* M[T1]  M[A] + M[B] */
ADD T2, C, D /* M[T2]  M[C] + M[D] */
MUL X, T1, T2 /* M[X]  M[T] * M[T2] */
 Above 9 Memory Accesses are involved.
 Instead if we use Registers in place of memory (T1, T2) for
temporary storage, memory accesses are reduced 5 as follow;
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */
 Three-address instruction results in short programs.
 However , the instruction becomes long (many bits)
Cont. . . Two-Address Instructions
 There are two fields of addresses in instruction
 Example:
program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[A] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
 Above 5 Memory Accesses are involved.
Cont. . . One-Address Instructions
 One-address instruction uses implied AC register for all data
manipulation
 Example:
program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
 No of instructions and memory accesses is increased to 7
Cont. . . Zero-Address Instructions
 There are no fields for addresses within the instruction.
 Can be found in a stack-organized computer.
 Example: program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */

 No of instructions is 8,
 However memory access is reduced because it does not uses
memory in ADD and MUL instructions
4. Internal CPU Organization
 Instruction format mainly depends on the internal organization of
CPU
 From the above discussed ISA design factor Operand Storage in the
CPU (number of address fields in the ISA) is the most distinguishing
factor of internal CPU organization.
 The 3 most common types of ISAs (CPU Organization) are the
following:
Single Accumulator
Organization

CPU General Purpose

Organization Register Organization

Stack- based
Organization
a) Single accumulator organization
 The accumulator register is used implicitly for processing all
instructions of a program and store the result.

 The first ALU operand is always stored into the Accumulator and
the second operand is present either in Registers or in the
Memory.

 Accumulator is the default address thus after data manipulation

the results are stored into the accumulator.

 One address instruction is used in this type of organization.

 The format of instruction is:
Opcode + Address
where Opcode indicates the type of operation to be performed.
Cont. . . Single accumulator organization
 Mainly two types of operation are performed in single accumulator
based CPU organization:
 Data transfer operation - LOAD X, STORE Y
 ALU operation
MULT X /* AC  AC * M[X] */
ADD X /* AC  AC + M[X] */
 Advantages
 Short instructions and less memory space because of One operand always
reside in the Accumulator.
 Instruction cycle takes less time because it saves time in instruction
fetching from memory
 Disadvantages
 Memory size will increases When complex expressions are computed
 As the number of instructions increases for a program, the execution time
increases.
Cont. . . Single accumulator organization

Program Control Unit(PCU)

• AR: Address Register
• IR: Instruction Register
• PC: Program Counter

Data Processing Unit(DPU)

• AC: Accumulator Register
• DR: Data Register
b) General purpose Register organization
 Using multiple general purpose registers, instead of single
accumulator register
 Uses two or three address fields in their instruction format.
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */

Advantages
• Efficiency of CPU increases as there are large number of registers are used
• Less memory space is used since the instructions are written in compact way.
Disadvantages
• Require to avoid unnecessary usage of registers. Thus, compilers need to be
more intelligent in this aspect.
• Extra cost -- since large number of registers are used
Cont. . . General purpose Register organization

This organization presented in either of the following two type

a) Register-memory reference architecture
 CPU with less register
 Operand source 1 is always required to be in register, where
source 2 can be present either in register or in memory.
 Two address instruction format is the compatible instruction
format.
b) Register-register reference architecture
 CPU with more register
 ALU operations are performed only on a register data
 Operands are required in the register and
 After manipulation result is also placed in register.
 Three address instruction format is the compatible instruction
format.
Cont. . . General purpose Register organization
Cont. . . General purpose Register organization

 Here below is Simple General Purpose register Organization circuit diagram

 This diagram used to demonstrate how this CPU of this type works
Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output
Cont. . . General purpose Register organization

Description of the GPR organization given on the previous slide.

 Components
 7 general purpose register
 3x8 decoder
 Two 3*8 Multiplexer
 ALU with 5 bits Opcode
 1 bit Input and 1 bit output carries (external)
 Clock signal
 A common bus system
Cont. . . General purpose Register organization

 Organizations
 The output of each register connected to two multiplexers (MUX) to
form the two buses A and B.
 The selection lines in each multiplexer select one register or the input
data for the particular bus.
 The A and B buses form the inputs to a common ALU.
 The Opcode selected in the ALU determines the arithmetic or logic
micro-operation that is to be performed.
 The result of the microoperation is available for output data and also
goes into the inputs of all the registers.
 The register that receives the information from the output bus is
selected and it’s load inputs are activated by the decoder, thus
providing a transfer path for the data between the output bus and the
inputs of the selected destination register
Cont. . . General purpose Register organization

 Control word
 The combination of the two multiplexer (MUX) selectors (SELA
& SELB), Decoder selector (SELD) and Opcode selector (OPR)
define a 14-bit control word (instruction code)

3 3 3 5
SELA SELB SELD OPR
 Three fields contain three bits each, and one field has five bits.
 The first two three bits of SELA & SELB are the selector of the source
register for the A input and B input of the ALU respectively.
 The three bits of SELD select a destination register using the decoder
and its seven load outputs.
 The five bits of OPR select one of the operations in the ALU.
Cont. . . General purpose Register organization

Binary
Code SELA SELB SELD OPR
000 Input Input None Select Operation Symbol
001 R1 R1 R1 00000 Transfer A TSFA

010 R2 R2 R2 00001 Increment A INCA

011 R3 R3 R3 00010 Add A + B ADD

100 R4 R4 R4 00101 Subtract A – B SUB

101 R5 R5 R5 00110 Decrement A DECA

110 R6 R6 R6 01000 AND A and B AND

111 R7 R7 R7 01010 OR A and B OR

01100 XOR A and B XOR
(a) Encoding of Register 01110 Complement A COMA
Selection Fields 10000 Shift right A SHRA
11000 Shift left A SHLA

(b) Encoding ALU Operations

Cont. . . General purpose Register organization

 Example: to perform the operation R1  R2 + R3

 The control must provide binary selection variables to the following
selector inputs:
 MUX A selector (SELA): to place the content of R2 into bus A.
 MUX B selector (SELB): to place the content of R3 into bus B.
 ALU operation selector (OPR): to provide arithmetic addition A + B.
 Decoder destination selector (SELD): to transfer the content of the
output bus into R1.

 Accordingly the Control Word: 010 011 001 00010

Selection Field: SELA SELB SELD OPR
Symbol: R2 R3 R1 ADD
Control Word 010 011 001 00010
Cont. . . General purpose Register organization

Note:
 When SELA or SELB is 000, the corresponding multiplexer selects the
external input data.
 When SELD = 000, no destination register is selected but the contents of the
output bus are available in the external output.
Example of Micro-operation for the CPU
Symbolic Designation

Micro operation SELA SELB SELD OPR Control Word

R1  R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
Cont. . .
Exercise - GPR
 A general purpose organized CPU similar the one discussed in the
section has 16 registers with 32 bits in each, ALU and destination
selector decoder.
a) How many multiplexers (MUX) are there in each bus (i.e. bus
size of the MUX)?
b) What is the size of multiplexers (MUX)?
c) How many selection inputs are needed for MUX A & MUX B?
d) What is the size of decoder (number of inputs and outputs)?
e) How many inputs and outputs are there in the ALU for data
including input and output carries?
f) Formulate a control word for the CPU assuming that the ALU
has 35 operations.
Cont. . .
Solution
a) 32 multiplexers, because the MUX select one 32 bits register.
b) The size of each MUX is 16 × 1 (connected to 16 registers).
c) 4 inputs each, to select one of 16 registers.
d) 4-to-16 – line decoder
e) 32 + 32 + 1 = 65 data input lines and
32 + 1 = 33 data output lines
f) Control word
4 4 4 6
SELA SELB SELD OPR
 c) Stack based organization
 A useful feature that is included in the CPU of most computers is a
stack or last-in, first-out (LIFO) list.
 A stack is a storage device that stores information in such a manner
that the item stored last is the first item to be retrieved.
 The operation of a stack can be compared to a stack of trays. The last
tray placed on top of the stack is the first to be taken off.
 The stack in digital computers is essentially a memory unit with an
address register that can count only (after an initial value is loaded into it)

 The register that holds the address

for the stack is called a stack
pointer (SP) which its value always
points to the top item of stack.
Cont. . . Stack based organization

 The two operations of a stack are the insertion (PUSH) and deletion
(POP) of items.

 These operations are simulated by incrementing or decrementing

the stack pointer register.
 To remove the top item, the stack is popped by reading the
memory word at address 3 and decrementing the content of SP.
 To insert a new item, the stack is pushed by incrementing SP and
writing a word in the next-higher location hi the stack

 Advantages
 Very useful feature for nested subroutines, nested loops control
 Efficient for arithmetic expression evaluation
Cont. . . Stack based organization

 A stack can be placed in a portion of a large memory or it can be

organized as a collection of a finite number of registers.
 Here below is Computer memory with program, data, and stack
segments

stack Address
63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
B 2
A 1
0
DR

(a) Register Stack (b) Memory Stack

A portion of memory is used as a stack
with a processor register as a stack pointer
Cont. . . Stack based organization

 The push operation

 Implemented with the following sequence of micro-operations:
SP  SP + 1 Increment stack pointer
M[SP]  DR Write item on top of the stack
If (SP= 0) then (FULL  1) Check if stack is full
EMTY  0 Mark the stack not empty

 The pop operation

 consists of the following sequence of micro-operations:

DR  M[SP] Read item from the top of the stack

SP  SP -1 Decrement stack pointer
If (SP= 0) then (EMTY  1) Check if stack is full
FULL  0 Mark the stack not full
Cont. . . Stack based organization

 Note that:
 SP holds the address of the top of the stack and that M[SP] denotes
the memory word specified by the address presently available in SP.
 The first item stored in the stack is at address 1.
 The last item is stored at address 0.
 If SP reaches 0, the stack is full of items, so the FULL flag is set to 1
 When SP reaches 1, the stack is empty and EMPTY flag set to 1 and
FULL is cleared to 0, so that SP points to the word at address 0 and
the stack is marked empty and not full.
 If the stack is not full (if FULL = 0), a new item is inserted with a push
operation
 Most computers do not provide hardware to check stack overflow
(full stack) or underflow(empty stack)
Cont. . . Stack based organization

Example:
 In a 64-word stack, the stack pointer contains 6 bits since 26 = 64.
 Because SP has only six bits, it cannot exceed a number greater
than 63 (111111 in binary).
 When 63 is incremented by 1, the result is 0 since 111111 + 1 =
1000000 in binary, but SP can accommodate only the six least
significant bits.
 Similarly, when 000000 is decremented by 1, the result is 111111.
 The one-bit register FULL is set to 1 when the stack is full, and the
one-bit register EMTY is set to 1 when the stack is empty of items
Cont. . . Stack based organization

1000

Program
PC (instructions)

Data
AR
(operands)

3000
SP
stack

3997
3998
3999
4000
4001

DR
Cont. . . Reverse Polish Notation
 A stack organization is very effective for evaluating arithmetic
expressions.
 Mathematical method of writing arithmetic expression
 A + B Infix notation (difficult to evaluate using computer)
Most common method of writing expressions
 + A B Prefix Polish notation
 A B + Postfix or reverse Polish notation
very suitable for stack manipulation
 Example 1: A * B + C * D
 Postfix notation: AB*CD*+
 Example 2: (A + B) * [C * (D + E) + F]
Postfix notation: A B + D E + C * F + *
Cont. . . Evaluation of Arithmetic Expressions

 The following numerical example may clarify this procedure.

 Consider the arithmetic expression
(3 * 4) + (5 * 6)
 In reverse Polish notation, it is expressed as; 3 4 * 5 6 * +

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +

Exercise: 10 + (2 * 8) - 3 a) Write its postfix format

b) Evaluate the expression using Stack
Cont. . .

Exercise:
1. Given the arithmetic expression 10 + (2 * 8) - 3
a) Write its postfix format
b) Evaluate the expression using Stack (show all the steps)

2. Consider a memory with 256-word stack.

a) How many items are available when the stack is FULL?
b) What is the SP value when the stack is FULL?
 Reading Resources/Materials
Chapter 8: Central Processing Unit
 M. Marios Mano: Computer System Architecture (3rd edition),
Pearson, 1992

Chapter 3: A Top-Level View of Computer

Chapter 14: Processor Structure and Function
Stallings William: Computer Organization and
Architecture: Designing for Performance (10th ed.),
Prentice Hall, 2016.

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THANKS!!

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