Japanese Journal of Applied Physics

Vol. 43, No. 4B, 2004, pp. 2283–2287

#2004 The Japan Society of Applied Physics

Characteristics of Si Integrated Antenna for Inter-Chip Wireless Interconnection

A. B. M. Harun-ur RASHID
, Shinji W ATANABE and Takamaro K IKKAWA
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527, Japan
(Received September 24, 2003; accepted November 28, 2003; published April 27, 2004)

The characteristics of a small-size integrated dipole antenna on Si have been evaluated for use in inter-chip wireless
interconnections and the measured characteristics are compared with the results obtained by 3D finite element simulation. The
measured inter-chip transmission coefficients for a 0.02 mm2 dipole antenna pair manually separated by 10.5 mm each other in
the horizontal plane and in a omit plane where the receiver chip is 2.6 mm higher than the transmitter chip were 42.7 dB and
57.5 dB at 20 GHz when the antennas were fabricated on a high-resistivity Si substrate and on standard Si substrate,
respectively. This shows the feasibility of using integrated dipole antennas for wireless clock distribution and data
transmission in future 3D ICs or in stacked chip scale packaging. [DOI: 10.1143/JJAP.43.2283]
KEYWORDS: wireless interconnects, integrated antennas, clock distribution, transmission gain, interference, ULSI

1. Introduction
The fundamental limitations of conventional interconnect
systems in reducing signal propagation delay has led to the
proposal of intra-chip wireless interconnections using
integrated antennas,1–3) microstrip transmission lines4–6)
and optical networks.7) Among these approaches, microwave
clock distribution using integrated antennas can reduce the
chip area used in interconnections while reducing the clock
skew and dispersion thus enabling a high clock frequency.
At the same time, the growing complexity in integrated
circuit design such as the design of system on a chip (SoC)
has increased the urgency for realizing 3D ICs and stacked
chip scale packaging. Inter-chip wireless interconnections
using integrated antennas are very promising for such
systems with the potential of realizing very-high-frequency
data and clock transmission while eliminating the need for
complex wiring. However, studies on inter-chip wireless
interconnects using integrated antennas have not yet been
performed.
In this paper, we report on the feasibility of inter-chip
wireless interconnections using Si integrated antennas. The
measured characteristics are compared with simulated
results obtained by employing a 3D finite element method
using the Ansoft HFSS program. The improvement of inter-
chip signal transmission by the use of a high-resistivity Si
substrate is also studied.
2. Antenna Test Structure Fabrication, Measurement
and Simulation
Figure 1 shows the conceptual diagram of the inter-chip
clock and data transmission in stacked chip packaging using
an integrated antenna. The transmitting antenna transmits
clock and data to the receiver antenna within the chip or to
another chip of the stacked package. Antenna test structures
were fabricated on a 260-mm-thick Si wafer with a 0.5-mm-
thick field oxide. A 1-mm-thick aluminum layer was
sputtered on top of the oxide and patterned by electron
beam lithography to form the antenna. The antenna length
and width were fixed at 2 mm and 10 mm, respectively.
Figure 2 shows various configurations used for the evalua-
tion of inter-chip signal transmission. For reference pur-


On leave from Bangladesh University of Engineering and Technology,
Dhaka, Bangladesh.
2283
Fig. 1. Concept of inter-chip wireless signal transmission in stacked chip
packaging. Tx —transmitting antenna, Rx —receiving antenna.
poses, intra-chip signal transmission, where the antenna
distance is d0 ¼ 3:0 mm, was evaluated first (Fig. 2(a)). This
was followed by evaluation of inter-chip signal transmission
with both chips placed on the same horizontal plane i.e. both
chips at the same height (Fig. 2(b)). The gap between the
two chips (dair ) was fixed at 0.5 mm so that the total
horizontal antenna distance was dtotal ¼ 3:5 mm. Next, we
evaluated inter-chip signal transmission with one chip
2.6 mm higher than the other and with a horizontal gap of
0.5 mm between the chips so that the total horizontal antenna
distance was dtotal ¼ 3:5 mm (Fig. 2(c)) i.e. the two chips
does not overlap each other. Finally we simulated inter-chip
signal transmission with one chip 2.6 mm higher than the
other and with both chips completely overlapping each other
(Fig. 2(d)). We were not able to measure data for this
configuration (Fig. 2(d)) because of the difficulties of placing
the probe. Figure 3 shows the setup for the measurement of
S-parameter. It consists of a HP8510C vector network
analyzer, 6.0–26.5 GHz 180 hybrid coupler, signal-signal
probes and a probe station. This setup converts the
unbalanced signals from the network analyzer to balanced
signals used to excite the dipole antenna. Semi-rigid cables
were used to increase measurement reliability. Wafers were
measured on a block of a thick (2.6 mm) low-k substrate
placed on the metal chuck of the probe station. This was
done to avoid the interference from the bottom metallic plate
of the probe chuck and to eliminate the reactive near-field
2284 Jpn. J. Appl. Phys., Vol. 43, No. 4B (2004) A. B. M. H. RASHID et al.

0
-2
-4
-6
-8

S11 (dB)
-10 Intra-chip, d0=3.0mm
-12 Inter-chip, dtotal=3.5mm
Inter-chip, h=2.6mm, dtotal=3.5mm
-14
-16 Antenna length = 2.0 mm
-18
-20
5 10 15 20 25
Frequency ( GHz )

Fig. 4. Measured reflection coefficient (S11 ) of antenna for various

Fig. 2. Different configurations used for evaluation of inter-chip signal
transmission and for comparison of the result with intra-chip character-
istics. (a) Intra-chip: transmitting antenna and receiving antenna are on
the same chip. (b) Inter-chip on same plane (h ¼ 0): the transmitting and
the receiving antenna are on different chips and both the chips are placed
in the same low-k layer with an air gap of 0.5 mm between the chips. In
this configuration, the two chips and the antennas are at the same height.
(c) Inter-chip with height between the chips h ¼ 2:6 mm: the transmitting
and the receiving antenna are on different chips. The chip with the
transmitting antenna is placed on a low-k substrate with a thickness of
2.6 mm. The chip with the receiving antenna is placed at a height of
2.6 mm from the transmitting antenna chip by supporting it on four very
small low-k material pads placed at the four corner of the chip and resting
it on top of the bottom low-k substrate. The separation between the chips
in the horizontal plane is 0.5 mm. Hence the height between the two chips
is 2.6 mm. (d) Inter-chip overlap with h ¼ 2:6 mm. Here the chip
containing the transmitting antenna and the chip containing the receiving
antenna are at a height difference of 2.6 mm and the chips overlap each
other completely. This configuration is used only in simulation. In all the
above cases, the length of the antenna is 2 mm and its width is 10 mm.
configurations shown in Fig. 2. For all configurations shown here, the
length and width of the antenna are 2 mm and 10 mm, respectively and the
antennas are fabricated on standard Si substrates having a resistivity of
10
cm.
finite element methods. The exact thickness and dielectric
properties of each layer of the integrated antenna structures
including of the low-k material were incorporated in the
simulation. The simulated characteristics were then com-
pared with the measured characteristics.
3. Results and Discussion
3.1 Inter-chip signal transmission on standard Si
Inter-chip signal transmission was measured and simulat-
ed on standard P-type-Si with a resistivity of 10
cm.
Figure 4 shows the measured reflection coefficient of the
transmitting antenna on a standard Si substrate. The
reflection coefficient of the transmitting antenna is identical
for all the configurations since it depends solely on the
substrate material and the antenna dimensions. Figure 5
shows the measured forward transmission coefficient (S21 ) of
the transmitter-receiver pair for intra-chip and various inter-

180°
Port 1 Hybrid SS
Coupler -10
Probe
Intra-chip, d0=3.0mm
Antenna -20 Inter-chip, dair=0.5mm, dtotal=3.5mm
50 Ω Termination
Inter-chip, h=2.6mm, dair=0.5mm, dtotal=3.5mm, Fig.2(c)
HP8510C -30
VNA Antenna
180° -40
S21 (dB)

Hybrid
Port 2 Coupler SS -50
Probe
-60
50 Ω Termination
-70 Antenna length = 2.0 mm
Fig. 3. Experimental setup for characterization of intra-chip and inter-
chip signal transmissions. -80
5 10 15 20 25
Frequency ( GHz )
capacitive coupling between the antenna and the bottom
metallic chuck of the probe station.2) The relative dielectric Fig. 5. Measured transmission coefficient of intra-chip and inter-chip
signal transmissions in various configurations shown in Fig. 2. The length
constant of the low-k layer was 2.15 at 1 GHz and was duly
and width of the antenna are 2 mm and 10 mm, respectively and the
incorporated in the simulation. Simulation of antenna antennas are fabricated on standard Si substrates having a resistivity of
structures was carried out with the ANSOFT High Fre- 10
cm. The distance between the antennas is 3 mm for intra-chip and
quency Structure Simulator (HFSS) program which uses 3D 3.5 mm in the horizontal plane for inter-chip configurations.
 Jpn. J. Appl. Phys., Vol. 43, No. 4B (2004) A. B. M. H. RASHID et al. 2285

chip configurations as shown in Fig. 2. As seen from Fig. 5,

the transmission coefficient of inter-chip signal transmission
reduces by 3 dB compared to the intra-chip one when the
two chips are placed close to each other with same antenna
length. A part of this reduction is due to the 0.5 mm air gap
between the two chips in the inter-chip configuration which
increases the antenna distance to 3.5 mm compared to 3 mm
in the intra-chip one and partly because the efficiency of
signal transmission through air is less than that through the
Si substrate. When one of the chips is raised 2.6 mm above
the other one without any overlap between then as shown in
Fig. 2(c), the transmission coefficient decreases by approx-
imately 5.6 dB. This reduction is due to the fact that the
effective distance of the receiving antenna from the trans-
mitting antenna increases in this case and also the major path
of electromagnetic wave through the Si and low-k substrates Fig. 7. Comparison of measured and simulated transmission coefficient
is interrupted by the air gap before reaching the receiver. (S21 ) versus frequency for intra-chip and various inter-chip configurations
Figure 6 shows the simulated transmission coefficient for shown in Fig. 2. In both measurement and simulation, the distance
intra-chip and various inter-chip configurations. As seen between the antennas is 3 mm for intra-chip and 3.5 mm in the horizontal
plane for inter-chip configurations. The length and width of the antenna
from Fig. 6, when the two chips completely overlap each are 2 mm and 10 mm, respectively and the antennas are fabricated on
other with the same antenna distance (Fig. 2(d)), the standard Si substrates of resistivity 10
cm.
transmission coefficient is approximately 5 dB greater than
that without overlap (Fig. 2(c)). This is because the total path
traveled by the electromagnetic wave through the Si layer is
-30
longer when the chips completely overlap each other and the Inter-chip, dtotal=3.5mm, h=2.6mm
antenna efficiency of transmission through air is less than Inter-chip, dtotal=5.5mm, h=2.6mm
that through the Si substrate. On the other hand, when the -40
Inter-chip, dtotal=8.0mm, h=2.6mm
two chips are separated by a small air gap of 0.5 mm and Inter-chip, dtotal=10.5mm, h=2.6mm
kept at the same height, the transmission coefficient is -50
S21 (dB)

almost the same as that of the intra-chip one. The reason for
the very slight decrease in transmission coefficient is the -60
same as described for the measured case. The measured
transmission coefficient is compared with the simulated
-70
value in Fig. 7. The measured and simulated data show
similar trends and match within 2 dB for all types of Antenna length = 2.0 mm
configurations in all frequency regions except for the case -80
where one chip is 2.6 mm higher than the other in which case 10 15 20 25
the measured data is 10 dB higher than the simulated data in Frequency ( GHz )

Fig. 8. Measured inter-chip transmission coefficient (S21 ) versus frequen-

cy for the configuration shown in Fig. 2 (b). Here, the distance between
-10
Intra-chip, d0=3.0mm the antenna is varied while keeping the air gap distance between the chips
Inter-chip, dair=0.5mm, dtotal=3.5mm, Fig.2(b) (dair ) at the fixed value of 0.5 mm.
-20
Inter-chip, h=2.6mm, dair=0.5mm, dtotal=3.5mm, Fig.2(c)
-30 Inter-chip, h=2.6mm, overlaped dtotal=3.5mm, Fig.2(d)
the low-frequency region (below 15 GHz). The reason for
-40
S21 (dB)

this discrepancy could be due to the exclusion of a number

of factors in the simulation such as the effect of the small
-50
low-k layer materials used for holding the receiver chip at a
-60 height of 2.6 mm from the transmitter chip. Figure 8 shows
the measured transmission coefficient versus frequency plot
-70 Antenna length = 2.0 mm
when the transmitter receiver separation distance is varied
-80
from 3 mm to 10 mm in the horizontal plane with a fixed air
5 10 15 20 25 gap of 0.5 mm between the chips so that the total horizontal
Frequency ( GHz ) antenna distances are 3.5 mm and 10.5 mm, respectively. At
20 GHz, the transmission coefficient are 48.7 dB and
Fig. 6. Simulated s-parameter forward transmission coefficient for various 57.5 dB at a distance of dtotal ¼ 3:5 mm and dtotal ¼
inter-chip wireless configurations shown in Fig. 2. The length and width 10:5 mm, respectively. The transmission gain increases with
of the antenna are 2 mm and 10 mm and the antennas are fabricated on frequency and decreases with distance as expected. The
standard Si substrates having a resistivity of 10
cm. The distance
between the antennas is the same as that used in the measurement i.e. effect of the air gap on inter-chip signal transmission is
3 mm for intra-chip and 3.5 mm in the horizontal plane for inter-chip shown in Fig. 9. In this figure, the antenna distance between
configurations. chips is varied by varying the air gap between the antenna on
2286 Jpn. J. Appl. Phys., Vol. 43, No. 4B (2004) A. B. M. H. RASHID et al.

Fig. 9. Measured variation of transmission coefficient (S21 ) plotted with Fig. 10. Improvement of inter-chip signal transmission coefficient by
actual distance between the transmitting and receiving antennas. using high-resistivity Si substrate (65 k
cm). When the chips are
fabricated on high-resistivity Si substrates (65 k
cm), the transmission
coefficients for the 2-mm-long antenna pair separated by 10 mm are
increased by 13.4 dB and 21.8 dB at 20 GHz and 25 GHz, respectively
the same horizontal plane i.e. with both chips on the same compared to those for standard Si substrates (10
cm).
low-k substrate. This is then compared with the case where
the air gap between the chips is kept constant at 0.5 mm and
the antenna distance is varied by using different patterns on
Si. As seen from Fig. 9, when both the chips are on a low-k 200 Input (a)
substrate, the increase of inter-chip antenna distance by 100 Vp-p=430 mV
Vin (mV)

increasing the air gap between the transmitter and receiver 0

-100
gives the same transmission coefficient as in the intra-chip
-200
case for the same antenna distance. Since the Si layer is very 6
thin, a large part of the electromagnetic waves pass through 4 Vr:Received signal on standard Si
dtotal=3.5mm (b)
the low-k substrate and hence the air gap has negligible 2
Vr (mV)

0
effect. On the other hand, when the receiving antenna chip is
-2
raised 2.6 mm above the transmitting antenna chip with an Vp-p=3.1562 mV
-4
air gap between them, the gain reduces by approximately -6
3 dB. As described before, this reduction is due to the fact 4 Vr:Received signal on standard Si
2 dtotal=10.5 mm (c)
that the effective distance of the receiving antenna from the
Vr (mV)

0
transmitting antenna increases in this case and also the major -2
path of electromagnetic waves through the Si and low-k -4 Vp-p=1.04 mV
substrates is interrupted by the large air gap before the waves -6
25 50 75 100
reach the receiver. Time (Ps)

3.2 Inter-chip signal transmission on high-resistivity Si
In order to simplify the design of analog interface circuits,
it is necessary to improve the inter-chip transmission
coefficient. To improve the inter-chip transmission coeffi-
cient of integrated antennas, we have increased the resis-
tivity of the Si substrate to an extremely high value by
proton implantation throughout the entire depth of the Si
substrate.2) The proton dose was 5  1014 cm2 and implan-
tation energy was 17.4 MeV. The measured value of
resistivity after proton implantation was approximately
65 k
cm. As shown in Fig. 10, after proton implantation,
the inter-chip transmission coefficient for the 2-mm-long
antenna pair separated by 10.5 mm in the horizontal
direction increased by 14.8 dB and 21.8 dB at 20 GHz and
25 GHz, respectively, compared to that on a standard Si
substrate having a resistivity of 10
cm. Figure 11 shows
the wave shape of inter-chip transmission of a sinusoidal
signal at 20 GHz on standard Si. The peak-to-peak ampli-
tudes of the received signal at the receiver antenna were
3.15 mV and 1.04 mV at the total horizontal antennas
distances of 3.5 mm and 10.5 mm, respectively. However,
Fig. 11. Inter-chip transmission of sinusoidal signal at 20 GHz for the
configuration shown in Fig. 2(c). Antenna length is 2 mm. (a) shows the
input signal. (b) and (c) show the received signal at the total horizontal
antenna distances of 3.5 mm and 10.5 mm, respectively. The peak-to-peak
amplitude of the transmitting signal was 430 mV at the input terminal.
as shown in Fig. 12, at the total horizontal distance of
10.5 mm, the received signal peak-to-peak amplitude in-
creased 6-fold to 6.88 mV when a high-resistivity Si
substrate was used.
4. Conclusion
Inter-chip signal transmission between standard 10
cm
Si substrates shows forward signal transmission coefficients
of 57.5 dB and 54.1 dB at 20 GHz and 25 GHz, respec-
tively, for 2-mm-long antennas when the transmitting and
the receiving antenna separation distance is 10.5 mm and the
receiver chip is 2.6 mm higher than the transmitter chip.
However, when a high resistivity (65 k
cm) Si substrate is
used, the transmission coefficient values increase to
 Jpn. J. Appl. Phys., Vol. 43, No. 4B (2004) A. B. M. H. RASHID et al. 2287

6 signal transmission using an integrated antenna with high

4 Standard Si
dtotal=10.5 mm
resistivity Si in 3D ICs or in stacked chip scale packaging.
2
Vr (mV)

0
Acknowledgements
-2
-4 Vp-p=1.04 mV This work is partially supported by the Ministry of
6
-6
Proton Implanted Si Education, Culture, Sports, Science and Technology under
4
2 dtotal=10.5mm the Grant-in-Aid for Scientific Research and also by JSPS.
Vr (mV)

0
-2
-4 Vp-p=6.88 mV 1) K. Kim, H. Yoon and Kenneth K. O : Int. Electron. Device. Meet.
-6 Tech. Dig. (2000) p. 485.
0 25 50 75 100
Time (Ps) 2) A. B. M. H. Rashid, S. Watanabe and T. Kikkawa : IEEE Electron
Device Lett. 23 (2002) 731.
Fig. 12. Peak-to-peak amplitude of received signal increases from 1 mv to 3) A. B. M. H. Rashid, S. Watanabe and T. Kikkawa : Jpn. J. Appl. Phys.
6.9 mV by using a high-resistivity Si substrate for the configuration 42 (2003) 2204.
shown in Fig. 2(c). The inter-chip height is 2.6 mm, the separation 4) Y. Yokoyama, T. Tsushima, H. Shinoki, N. Takagi and K. Masu : Ext.
distance between the antennas in the total horizontal distance is 10.5 mm Abstr. Int. Conf. Solid State Devices and Materials (Business Center
and the antenna length is 2 mm. The applied 20 GHz sinusoidal signal had for Academic Societies Japan, Tokyo, 2001) p. 58.
a peak-to-peak amplitude of 430 mV at the input terminal. 5) Mau-chung Frank Chang, Vwani P. Roychowdhury, L. Zhang, H. Shin
and Y. Qian: Proc. IEEE 89 (2001) 456.
6) M. F. Chang, V. Roychowdhury, L. Y. Zhang, S. N. Zhou, Z. Y.
Wang, Y. C. Wu, P. X. Ma, C. S. Lin and Z. J. Kang: Proc. IEEE VLSI
42.7 dB and 32.3 dB at 20 GHz and 25 GHz, respectively Tech. Symp. (2000) p. 21.
and the amplitude of the received sinusoidal signal at 7) A. V. Mule, M. Schultz, E. N. Glytsis, T. K. Gaylord and J. D. Meindl:
20 GHz increases from 1 mV to 6.8 mV. This demonstrates Proc. IEEE Inter. Interconnect Tech. Conf. (2001) p. 128.
the feasibility and the effectiveness of inter-chip wireless