1 module uart_top(// Inputs

2 CLK,
3 BTN_SOUTH,
4 BTN_WEST,
5 RS232_DCE_RXD,
6 dout_rdy,
7 dout_byte,
8 // Outputs
9 d_rdy,
10 d_byte,
11 RS232_DCE_TXD,
12 //Monitoring Signal
13 clk_x
14 );
15
16 parameter SIZE = 11;
17 parameter MAX = 1302;
18 //---- Port Declarations ----
19 input CLK ;
20 input BTN_SOUTH ;
21 input BTN_WEST ;
22 input RS232_DCE_RXD ;
23 input dout_rdy ;
24 input [7:0] dout_byte ;
25
26 output d_rdy ;
27 output [7:0] d_byte ;
28 output RS232_DCE_TXD ;
29 output clk_x ;
30
31 //-- Intermediate Signals Declaration --
32 reg [3:0] count_div ;
33 reg [SIZE-1:0] count_div_19200 ;
34 reg clk_16x ;
35 reg d_rdy ;
36 reg [7:0] d_byte ;
37 reg [7:0] databyte ;
38 reg drdy ;
39
40 wire [7:0] dout_byte_wire ;
41 wire dout_rdy_wire ;
42 wire clk_x ;
43
44 ///////////////////////////////////////////////////////////////////
45 ////////////// CLOCK DIVIDER BLOCK for Baud Rate /////////////////
46 ///////////////////////////////////////////////////////////////////
47 always @(posedge CLK or posedge BTN_SOUTH)
48 begin
49 if(BTN_SOUTH) begin
50 count_div_19200 <= 0 ;
51 clk_16x <= 1'b0 ;
52 end
53 else if(count_div_19200 == MAX-1) begin
54 count_div_19200 <= 0 ;
55 clk_16x <= ~clk_16x;
56 end
57 else begin
58 count_div_19200 <= count_div_19200 + 1;
59 clk_16x <= clk_16x;
60 end
61 end
62
63 // clk_16x = 19200 Hz
64 always @(posedge clk_16x or posedge BTN_SOUTH)
65 begin
66 if(BTN_SOUTH)
67 count_div <= 4'd0 ;
68 else
69 count_div <= count_div + 1;
 70 end
71
72 // clk_x = 1200 Hz
73 assign clk_x = count_div[3];
74 /////////////////////////////////////////////////////
75 /////////////////////////////////////////////////////
76
77 always @(posedge CLK or posedge BTN_SOUTH)
78 begin
79 if(BTN_SOUTH) begin
80 d_rdy <= 1'b0 ;
81 d_byte <= 8'd0 ;
82 end
83 else if(BTN_WEST) begin
84 d_rdy <= dout_rdy ;
85 d_byte <= dout_byte ;
86 end
87 else begin
88 d_rdy <= dout_rdy_wire ;
89 d_byte <= dout_byte_wire ;
90 end
91 end
92
93 always @(posedge CLK or posedge BTN_SOUTH)
94 begin
95 if(BTN_SOUTH) begin
96 drdy <= 1'b0 ;
97 databyte <= 8'd0 ;
98 end
99 else begin
100 drdy <= d_rdy ;
101 databyte <= d_byte ;
102 end
103 end
104
105 // Uart Transmitter
106 uat_top uat_top_inst(//Inputs
107 .clk_x (clk_x ), //1-bit System Clock in
108 .rst_p (BTN_SOUTH ), //1-bit Asyncronous
Active Low Reset input
109 .din_rdy (drdy ), //1-bit ready input
signal that indicates the data is ready at input for Tx
110 .din_byte (databyte ), //8-bit data input in
UART for Tx
111 // Output
112 .ser_out (RS232_DCE_TXD) //1-bit Tx data output
from UART
113 );
114
115 // Uart Reciever
116 uar_top uar_top_inst(// Inputs
117 .clk_16x (clk_16x ),
118 .rst_p (BTN_SOUTH ),
119 .ser_in (RS232_DCE_RXD ),
120 // Outputs
121 .dout_rdy (dout_rdy_wire ),
122 .dout_byte (dout_byte_wire )
123 );
124 endmodule
125
126 //------------------------------------------------------------------------------------
-----------
127 // Project : UART Core for FPGA
128 // File : uat_top.v
129
130 module uat_top(//Inputs
131 clk_x, //1-bit System Clock input
132 rst_p, //1-bit Asyncronous Active Low Reset input
133 din_rdy, //1-bit ready input signal that indicates the data
 is ready at input for Tx
134 din_byte, //8-bit data input in UART for Tx
135 // Output
136 ser_out //1-bit Tx data output from UART
137 );
138 // Declaration inputs, outputs
139 input clk_x ;
140 input rst_p ;
141 input din_rdy ;
142 input [7:0] din_byte ;
143 output ser_out ;
144
145 reg ser_out;
146 reg [7:0] data_buf;
147 reg [2:0] shift_count;
148 reg din_rdy_reg;
149
150 wire start_bit_sig;
151 wire data_bits_sig;
152 wire stop_bit_sig;
153
154 // Registered Data Ready Signal
155 always @(posedge clk_x or posedge rst_p)
156 begin
157 if(rst_p)
158 din_rdy_reg <= 1'b0;
159 else
160 din_rdy_reg <= din_rdy ;
161 end
162
163 //Output Logic
164 //always @(posedge clk_x or posedge rst_p)
165 always @(negedge clk_x or posedge rst_p)
166 begin
167 if(rst_p)
168 ser_out <= 1'b1;
169 else
170 begin
171 case({start_bit_sig,data_bits_sig,stop_bit_sig})
172 3'b100: ser_out <= 1'b0;
173 3'b010: ser_out <= data_buf[0];
174 3'b001: ser_out <= 1'b1;
175 default: ser_out <= 1'b1;
176 endcase
177 end
178 end
179
180 // strat bit pipelinin
181 always @(posedge clk_x or posedge rst_p)
182 begin
183 if(rst_p)
184 data_buf <= 8'd0;
185 else if(start_bit_sig)
186 data_buf <= din_byte; // at just arriving the start_bit_sig , we load data into
data_buffer
187 else if(data_bits_sig)
188 data_buf <= {1'b1,data_buf[7:1]};
189 else
190 data_buf <= data_buf;
191 end
192
193 // Counter that count shift in Data Buffer Logic
194 always @(posedge clk_x or posedge rst_p)
195 begin
196 if(rst_p)
197 shift_count <= 3'd0;
198 else if(data_bits_sig)
199 shift_count <= shift_count + 1; //Counter will start when data is vlaid by High
the data_bits_sig flag
200 else
201 shift_count <= 3'd0;
202 end
203
204 // State machine for Tx
205 uat_sm uat_sm_inst(// Inputs
206 .clk_x (clk_x ),
207 .rst_p (rst_p ),
208 .din_rdy (din_rdy_reg ), // 1-bit serial data from
channel
209 .shift_count (shift_count ),
210 // Outputs
211 .start_bit_sig (start_bit_sig), // Start bit insertion
Control Signal generate from State Mechiene
212 .data_bits_sig (data_bits_sig), // Data bits insertion
Control Signal generate from State Mechiene
213 .stop_bit_sig (stop_bit_sig ) // Stop Bit insertion
Control Signal generate from State Mechiene
214 );
215 endmodule
216 //------------------------------------------------------------------------------------
-----------
217 // Project : UART Core for FPGA
218 // File : uat_sm.v
219
220 module uat_sm(// Inputs
221 clk_x,
222 rst_p,
223 din_rdy,
224 shift_count,
225 // Outputs
226 start_bit_sig,
227 data_bits_sig,
228 stop_bit_sig
229 );
230
231 input clk_x ;
232 input rst_p ;
233 input din_rdy ;
234 input [2:0] shift_count ;
235 output start_bit_sig ;
236 output data_bits_sig ;
237 output stop_bit_sig ;
238
239 parameter [3:0] IDLE = 4'b0001 ;
240 parameter [3:0] START_BIT_ST = 4'b0010 ;
241 parameter [3:0] DATA_BITS_ST = 4'b0100 ;
242 parameter [3:0] STOP_BIT_ST = 4'b1000 ;
243
244 reg start_bit_sig ;
245 reg data_bits_sig ;
246 reg stop_bit_sig ;
247 reg [3:0] tx_state ;
248
249
250 always @(posedge clk_x or posedge rst_p)
251 begin
252 if(rst_p) begin
253 tx_state <= 4'd0 ;
254 end
255 else begin
256 case(tx_state)
257 IDLE : begin
258 if(din_rdy)
259 tx_state <= START_BIT_ST;
260 else
261 tx_state <= IDLE;
262 end
263 START_BIT_ST : begin
264 tx_state <= DATA_BITS_ST;
265 end
266 DATA_BITS_ST : begin
267 if(shift_count == 3'd7)
268 tx_state <= STOP_BIT_ST;
269 else
270 tx_state <= DATA_BITS_ST;
271 end
272 STOP_BIT_ST : begin
273 if(din_rdy)
274 tx_state <= START_BIT_ST;
275 else
276 tx_state <= IDLE;
277 end
278 default : begin
279 tx_state <= IDLE ;
280 end
281 endcase
282 end
283 end
284
285 always @(tx_state)
286 begin
287 case(tx_state)
288 IDLE : begin
289 start_bit_sig = 1'b0 ;
290 data_bits_sig = 1'b0 ;
291 stop_bit_sig = 1'b0 ;
292 end
293 START_BIT_ST : begin
294 start_bit_sig = 1'b1 ;
295 data_bits_sig = 1'b0 ;
296 stop_bit_sig = 1'b0 ;
297 end
298 DATA_BITS_ST : begin
299 start_bit_sig = 1'b0 ;
300 data_bits_sig = 1'b1 ;
301 stop_bit_sig = 1'b0 ;
302 end
303 STOP_BIT_ST : begin
304 start_bit_sig = 1'b0 ;
305 data_bits_sig = 1'b0 ;
306 stop_bit_sig = 1'b1 ;
307 end
308 default : begin
309 start_bit_sig = 1'b0 ;
310 data_bits_sig = 1'b0 ;
311 stop_bit_sig = 1'b0 ;
312 end
313 endcase
314 end
315
316 endmodule
317
318 //------------------------------------------------------------------------------------
-----------
319 // Project : UART Core for FPGA
320 // File : uar_top.v
321
322 module uar_top(// Inputs
323 clk_16x,
324 rst_p,
325 ser_in,
326 // Outputs
327 dout_rdy,
328 dout_byte
329 );
330
331 // Inputs
332 input clk_16x ;
333 input rst_p ;
334 input ser_in ;
335 // Outputs
336 output dout_rdy ;
337 output [7:0] dout_byte ;
338
339 reg ser_in_r1 ;
340 reg ser_in_r2 ;
341 reg [4:0] count_rdy_sig ;
342 reg [3:0] count_sample ;
343 reg [3:0] shift_count ;
344 reg [7:0] dout_byte_temp ;
345 reg dout_rdy_temp ;
346 reg [7:0] dout_byte ;
347 reg dout_rdy ;
348 reg dout_rdy_d ;
349
350 wire start_bit_sig ;
351 wire data_bits_sig ;
352 wire stop_bit_sig ;
353 wire valid_data ;
354
355
356 // Detect Input Data
357 always @(posedge clk_16x or posedge rst_p)
358 begin
359 if(rst_p) begin
360 ser_in_r1 <= 1'b1 ;
361 ser_in_r2 <= 1'b1 ;
362 end
363 else begin
364 ser_in_r1 <= ser_in ;
365 ser_in_r2 <= ser_in_r1 ;
366 end
367 end
368
369 assign valid_data = (~ser_in_r1 & ser_in_r2) ;
370
371 // Output Logic
372 always @(posedge clk_16x or posedge rst_p)
373 begin
374 if(rst_p)
375 count_sample <= 4'd0 ;
376 else if(start_bit_sig | data_bits_sig | stop_bit_sig )
377 count_sample <= count_sample + 1 ;
378 else
379 count_sample <= 4'd0 ;
380 end
381
382 // Counter that count shift in Data Buffer Logic
383 always @(posedge clk_16x or posedge rst_p)
384 begin
385 if(rst_p)
386 shift_count <= 4'd0 ;
387 else if(count_sample == 4'd9 && shift_count == 4'd9)
388 shift_count <= 4'd0 ;
389 else if(count_sample == 4'd9 && (start_bit_sig | data_bits_sig | stop_bit_sig))
390 shift_count <= shift_count + 1 ;
391 else
392 shift_count <= shift_count ;
393 end
394
395 // Output Logic
396 always @(posedge clk_16x or posedge rst_p)
397 begin
398 if(rst_p) begin
399 dout_byte_temp <= 8'd0 ;
400 dout_rdy_temp <= 1'b0 ;
401 end
402 else begin
403 case({stop_bit_sig, data_bits_sig, start_bit_sig})
404 3'b001 : begin // Data Bits Extract
405 dout_byte_temp <= dout_byte_temp ;
406 dout_rdy_temp <= 1'b0 ;
407 end
408 3'b010 : begin // Data Bits Extract
409 if(count_sample == 4'd7)
410 dout_byte_temp <= {ser_in_r2, dout_byte_temp[7:1]} ;
411 dout_rdy_temp <= 1'b0 ;
412 end
413 3'b100 : begin // Data Bits Extract
414 if(count_sample == 4'd7 && ser_in_r2 == 1'b1)
415 dout_rdy_temp <= 1'b1 ;
416 else
417 dout_rdy_temp <= 1'b0 ;
418 dout_byte_temp <= dout_byte_temp ;
419 end
420 default : begin // Retain previous status
421 dout_byte_temp <= dout_byte_temp ;
422 dout_rdy_temp <= 1'b0 ;
423 end
424 endcase
425 end
426 end
427
428 // Latch Decode Data
429 always @(posedge clk_16x or posedge rst_p)
430 begin
431 if(rst_p)
432 dout_byte <= 8'd0 ;
433 else if(dout_rdy_temp)
434 dout_byte <= dout_byte_temp ;
435 else
436 dout_byte <= dout_byte ;
437 end
438
439 always @(posedge clk_16x or posedge rst_p)
440 begin
441 if(rst_p) begin
442 count_rdy_sig <= 5'd0 ;
443 dout_rdy_d <= 1'b0 ;
444 end
445 else if(dout_rdy_temp) begin
446 count_rdy_sig <= 5'd1 ;
447 dout_rdy_d <= 1'b1 ;
448 end
449 else if(count_rdy_sig != 5'd0 && count_rdy_sig != 5'd16) begin
450 count_rdy_sig <= count_rdy_sig + 1 ;
451 dout_rdy_d <= 1'b1 ;
452 end
453 else begin
454 count_rdy_sig <= 5'd0 ;
455 dout_rdy_d <= 1'b0 ;
456 end
457 end
458
459 // Delay Data Ready Signal
460 always @(posedge clk_16x or posedge rst_p)
461 begin
462 if(rst_p)
463 dout_rdy <= 1'b0 ;
464 else
465 dout_rdy <= dout_rdy_d ;
466 end
467
468 // State machine for Tx
469 uar_sm uar_sm_inst(// Inputs
470 .clk_16x (clk_16x ),
471 .rst_p (rst_p ),
472 .din_rdy (valid_data ),
473 .shift_count (shift_count ),
474 .count_sample (count_sample ),
475 // Outputs
476 .start_bit_sig (start_bit_sig),
477 .data_bits_sig (data_bits_sig),
478 .stop_bit_sig (stop_bit_sig )
479 );
480 endmodule
481
482 //------------------------------------------------------------------------------------
-----------
483 // Project : UART Core for FPGA
484 // File : uar_sm.v
485
486 module uar_sm(// Inputs
487 clk_16x,
488 rst_p,
489 din_rdy,
490 shift_count,
491 count_sample,
492 // Outputs
493 start_bit_sig,
494 data_bits_sig,
495 stop_bit_sig
496 );
497 // Inputs
498 input clk_16x ;
499 input rst_p ;
500 input din_rdy ;
501 input [3:0] shift_count ;
502 input [3:0] count_sample;
503 // Outputs
504 output start_bit_sig ;
505 output data_bits_sig ;
506 output stop_bit_sig ;
507
508 parameter [3:0] IDLE = 4'b0001 ;
509 parameter [3:0] START_BIT_ST = 4'b0010 ;
510 parameter [3:0] DATA_BITS_ST = 4'b0100 ;
511 parameter [3:0] STOP_BIT_ST = 4'b1000 ;
512
513 // Register and Wire Declaration
514 reg start_bit_sig ;
515 reg data_bits_sig ;
516 reg stop_bit_sig ;
517 reg [3:0] rx_state ;
518
519 // State Register, Next State & Output Logic
520 always @(posedge clk_16x or posedge rst_p)
521 begin
522 if(rst_p) begin
523 rx_state <= IDLE ;
524 end
525 else begin
526 case(rx_state)
527 IDLE : begin
528 if(din_rdy)
529 rx_state <= START_BIT_ST ;
530 else
531 rx_state <= IDLE ;
532 end
533 START_BIT_ST : begin
534 if(shift_count == 4'd1)
535 rx_state <= DATA_BITS_ST ;
536 else
537 rx_state <= START_BIT_ST ;
538 end
539 DATA_BITS_ST : begin
540 if(shift_count == 4'd9)
541 rx_state <= STOP_BIT_ST ;
542 else
543 rx_state <= DATA_BITS_ST ;
544 end
545 STOP_BIT_ST : begin
546 if(count_sample == 4'd9)
547 rx_state <= IDLE ;
548 else
549 rx_state <= STOP_BIT_ST ;
550 end
551 default : begin
552 rx_state <= IDLE ;
553 end
554 endcase
555 end
556 end
557
558 always @(rx_state)
559 begin
560 case(rx_state)
561 IDLE : begin
562 start_bit_sig = 1'b0 ;
563 data_bits_sig = 1'b0 ;
564 stop_bit_sig = 1'b0 ;
565 end
566 START_BIT_ST : begin
567 start_bit_sig = 1'b1 ;
568 data_bits_sig = 1'b0 ;
569 stop_bit_sig = 1'b0 ;
570 end
571 DATA_BITS_ST : begin
572 start_bit_sig = 1'b0 ;
573 data_bits_sig = 1'b1 ;
574 stop_bit_sig = 1'b0 ;
575 end
576 STOP_BIT_ST : begin
577 start_bit_sig = 1'b0 ;
578 data_bits_sig = 1'b0 ;
579 stop_bit_sig = 1'b1 ;
580 end
581 default : begin
582 start_bit_sig = 1'b0 ;
583 data_bits_sig = 1'b0 ;
584 stop_bit_sig = 1'b0 ;
585 end
586 endcase
587 end
588 endmodule