Design of Sequential Circuits - Example 1.4 http://osp.mans.edu.eg/cs212/Seq_circuits_state_reduction_ex_1_4.

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Design of Sequential Circuits

This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176.

Example 1.4 Design a sequential circuit whose state tables are specified in Table 12, using D flip-flops.

Table 12. State table of a sequential circuit.

Present State Next State Output
Q 0 Q1 x=0 x=1 x=0 x=1

00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1

Table 13. Excitation table for a D flip-flop.

Output Transitions Flip-flop inputs
QàQ(next) D

0 à 0 0

0 à 1 1

1 à 0 0
1 à 1 1

Next step is to derive the excitation table for the design circuit, which is shown in Table 14. The output of the
circuit is labeled Z.
Present State Next State Input Flip-flop Inputs Output
Q0 Q 1 Q0 Q 1 x D0 D1 Z

00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1

Table 14. Excitation table

Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean expressions, which
is shown in Figure 16.

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Design of Sequential Circuits - Example 1.4 http://osp.mans.edu.eg/cs212/Seq_circuits_state_reduction_ex_1_4.htm

Figure 16. Karnaugh maps

The simplified Boolean expressions are:

D0 = Q0 * Q1' + Q0' * Q1 * x
D1 = Q0' * Q1' * x + Q0 * Q1 * x + Q0 * Q1' * x'
Z = Q 0 * Q1 * x

Finally, draw the logic diagram.

Figure 17. Logic diagram of the sequential circuit.

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