1696 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 06, NO.
11, NOVEMBER 2016
Analysis of Interfacial Peeling of an Ultrathin
Silicon Wafer Chip in a Pick-Up Process
Using an Air Blowing Method
Eun-Beom Jeon, Sung-Hyeon Park, Yun-Sik Yoo, and Hak-Sung Kim
Abstract— The ultrathin integrated circuit (IC) chip ejecting
and pick-up process plays an important role in advanced pack-
ages since the success ratio and productivity are determined
by the delamination of chips from the adhesive tape substrate.
As thinning of the IC chip occurs, chip cracking between the
adhesive tape and ultrathin IC chip increases due to the low
strength of the ultrathin IC chip in the die pick-up process. In this
paper, the interfacial adhesion strength and energy release rate
between an ultrathin IC chip and base tape were measured by a
90° peel test as a function of the peeling velocity. Also, an index
was defined to characterize the competing fracture behavior
between the delamination of the chip from the adhesive tape and
chip cracking. Finite-element analysis of the die pick-up process
with a virtual crack-closure technique was performed to predict
stable peeling off of the chip with respect to the velocity of the
chip holder as well as the pressure of the blown air considering
the interfacial energy release rate and chip strength. The results
show that the velocity of the chip holder and the pressure of
the blown air should be lower than 50 mm/min and 90 kPa,
respectively.
Index Terms— Adhesive tape, chip crack, chip strength,
die pick-up process, energy release rate, ultrathin IC chip, virtual
crack-closure technique (VCCT).
I. I NTRODUCTION
R ECENTLY, the demand of advanced packages has
tremendously increased in electronics and communica-
tion equipment such as 3-D chip stacking, system-in-package,
Manuscript received May 11, 2016; revised September 11, 2016; accepted
September 14, 2016. Date of publication October 12, 2016; date of cur-
rent version November 7, 2016. This work was supported in part by the
Semiconductor Industry Collaborative Project between Hanyang University
and Samsung Electronics Company, Ltd., in part by the National Research
Foundation of Korea, funded by the Ministry of Education under Grant
2015R1D1A1A09058418, in part by the Industrial Strategic Technology
Development Program funded by the Ministry of Trade, Industry and
Energy, Korea, through the Project titled In-line Semiconductor Chip/Package
Inspection system with THz imaging under Grant 201500000002212, and
in part by the research fund of Hanyang University under Grant HY-2013.
Recommended for publication by Associate Editor B. Dang upon evaluation
of reviewers’ comments.
E.-B. Jeon was with the Department of Mechanical Convergence
Engineering, Hanyang University, Seoul 133-791, South Korea. He is
now with Solution Product & Development, Samsung Electronics,
Hwaseong 1884-8, South Korea.
S.-H. Park is with the Department of Mechanical Convergence Engineering,
Hanyang University, Seoul 133-791, South Korea.
Y.-S. Yoo is with Samsung Electronics Company, Ltd., Asan 336-711,
South Korea.
H.-S. Kim is with the Department of Mechanical Convergence Engineering,
Hanyang University, Seoul 133-791, South Korea, and also with the Insti-
tute of Nano Science and Technology, Hanyang University, Seoul 133-791,
South Korea (e-mail: kima@hanyang.ac.kr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2016.2612238
2156-3950 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
and package-on-package applications, which are challenging
current electronic assembly techniques. One of the major
challenges is the capability of handling thin integrated cir-
cuit (IC) chips during the assembly process [1]–[3]. It is
of significance to fundamentally understand the effects of
thin chips on electronic packaging in terms of how the
length and thickness of the chip affect the assembly [4], [5].
In particular, the ultrathin IC chip ejecting and pick-up
process plays an important role in advanced packages since
the success ratio and productivity of the package products
are determined by the delamination of chips from the sub-
strate [6]. An ejecting method using a needle or multineedle
has been used to eject the IC chip from the adhesive
tape of the wafer. To decrease chip failure in the pick-up
process, Chong and Cheung [2] and Lin and Hwang [7]
investigated the effects of some key parameters, including the
needle ejecting speed, vacuum pressure, pressing force, and the
needle radius by static finite-element model (FEM) based on
the Taguchi method. Also, an interfacial peeling mechanism of
chip-on-substrate structures using a needle was experimentally
and analytically investigated [8]–[10]. Liu et al. [5] effectively
reduced the die cracking stress and improved the peeling
energy using a multineedle ejector. Lin and Hwang [7] showed
that there was a competing relationship between the chip
peeling off and chip cracking. They also demonstrated that
peeling off of a thinner chip had a lower peeling energy
release rate and higher chip fracture stresses than a thicker
chip, demonstrating that it is more difficult to peel a thinner
chip from adhesive tape to an anticipated extent. On the other
hand, one of the critical issues after chip peeling off is how to
effectively pick the chip up from the remaining bonded region
using vacuum tools. In particular, for a thin chip, the picking
up process is more likely to fail due to incomplete separation
between the chip and the adhesive tape. It was considered that
this failure may be caused by the larger unseparated region [3].
Moreover, as the IC chip thins (under 30-μm thickness),
defects of the ultrathin IC chip such as chip cracking occurred
due to the low mechanical strength of the ultrathin IC chip and
stress concentration by the needle tip [11], [12]. In addition,
Peng et al. [13] demonstrated that the pick-up process using
needles can only peel off chips with a thickness greater than
37 μm from the substrate. Therefore, in this paper, an air
blowing method using distributed air blowing below the chip
was developed to avoid chip cracking as it can prevent the
concentrated force of the chip. There are few reports that
further investigate chip picking up, especially regarding the
JEON et al.: ANALYSIS OF INTERFACIAL PEELING OF AN ULTRATHIN SILICON WAFER CHIP
TABLE I
M ATERIAL P ROPERTIES OF U LTRATHIN NAND F LASH
M EMORY C HIP, DAF, AND A DHESIVE TAPE
effects of the air blowing pressure and displacement of the
chip holder.
For the analysis, the critical energy release rate between
the ultrathin IC chip and the adhesive tape as a function of
the peel speed was measured and calculated by conducting
a 90° peel test of the adhesive tape. Finite-element analy-
sis (FEA) using the virtual crack-closure technique (VCCT)
with dummy nodes was employed to compute the energy
release rate at the interface between the IC chip and the
adhesive tape as well as the chip cracking stress. In addition,
an index to characterize the competing relationship of the chip
peeling off and chip cracking was established. Based on the
competing index, optimization of the die pick-up process using
the air blowing method was performed with respect to the
velocity of the chip holder and pressure of the blowing air.
II. E XPERIMENT
A. Specimen Preparation
In order to measure the critical energy release rate between
the ultrathin IC chip and the adhesive tape, ultrathin NAND
flash memory chips (Samsung Electronics, Korea) were pre-
pared with the dimensions of 9.46 mm × 15.08 mm × 30 μm
(length × width × thickness). The material properties and
dimensions of the materials used are listed in Table I, where
E is Young’s modulus, ν is the Poisson ratio, and ρ is the
density of the layers. The die attach film (DAF) and the
adhesive tape were made of acryl resins and epoxy resins,
which are UV curable. The purpose of UV curing is to reduce
the interfacial strength between the DAF layer and adhesive
tape layer and to be able to handle the chip easily in the
packaging process. For the information related to the adhesion
strength, the surface roughness and contact angle of the wafer
were measured using atomic focused microscope (AFM, Park
system, XE 100) and goniometer (S.E.O. Co, Phoenix10),
respectively [Fig. 1(a) and (b)]. The AFM machine allows
for a low thermal drift of less than 1.5 mm/min/°C. The
scan areas were 256 × 256 pixels over 45 × 45 μm2 using
a 1-Hz scan rate with noncontact mode to minimize sample
damage. The water contact angle was measured at five times
across the sample surface using the sessile drop method by
dispensing 5-μL drops of deionized water on the surface
of the bottom of the NAND chip. As a result, the surface
roughness of the NAND chip was determined with 45.55 nm
as a value of Ra and 322.45 nm as a value of Rpv with a
value of Rku (3.49). Also, the contact angle was determined
as 68. 05 1°C of the average value.
1697
Fig. 1. (a) 3-D morphology. (b) Contact angle images of the bottom of
the NAND chip. (c) Experimental setup for peel test of the ultrathin IC chip.
(d) Schematic of the peel test. (e) Peeling load–displacement curve. (f) Critical
energy release rate with respect to the peel speed.
B. 90° Peel Test for the Interfacial Toughness Measurement
at the Chip/Adhesive Tape Interface
In order to measure the critical energy release rate (interface
toughness) G interface
c between the chip and the adhesive tape,
a 90° peel test was conducted, as shown in Fig. 1(c). The
3 × 5 array of the ultrathin NAND flash memory chip was
fixed on the steel plate, and a strip of 12-mm-wide scotch tape
(3M Brand 600) was attached on the middle array of the
chip. Then, the attached adhesive tape on the chips was peeled
off in a 90° direction. Fig. 1(d) shows the schematic of the
90° peel test. The peel test was performed using an LRX Plus
Series universal test machine, which has a force resolution
and an accuracy of 0.0005 N and ± 0.5%, respectively. The
loading speed was varied from 25 to 250 mm/min. During
the test, the peeling load was applied in the vertical direction,
while the specimens were moved at the same speed in the
direction parallel to the vertical loading speed to maintain the
90° peeling direction by the wire connections. The peeling
loading–displacement curve is shown in Fig. 1(e). In the
90° peel test, the energy release rate is generally the same as
the peel force per unit width [14]. Therefore, the 90° peel test
was employed to measure the critical energy release rate in this
paper. The peel force (N) from the peel test can be calculated
as the energy release rate using the following equation:
G Interface
C = peel force (N)/width of tape (mm). (1)
1698 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 06, NO. 11, NOVEMBER 2016

TABLE II
C RITICAL E NERGY-R ELEASE R ATE W ITH R ESPECT TO THE P EEL S PEED

Fig. 1(f) shows the critical energy release rate between the
chip and the adhesive tape with respect to the peel speed.
The energy release rate monotonically increased as the peeling
speed increased, similar to the results obtained in [14]. This
is because the viscoelastic force of the adhesive tape becomes
larger as the peeling speed is faster in a steady-state peeling
process [15], [16]. The peel force as a function of the peeling
velocity was calculated to determine the critical energy release
rate G interface
c using (1). The critical energy release rate as a
function of the peel velocity is listed in Table II, and these
properties were used in the FEM analysis at the interface.

III. C OMPETING F RACTURE M ECHANISM B ETWEEN THE

C HIP /A DHESIVE TAPE I NTERFACIAL D ELAMINATION
AND C HIP C RACKING
A. Mechanical Model
The schematic of the die pick-up process using blowing air
is shown in Fig. 2. The air blowing chip pick-up process is
composed of three stages: gripping of the adhesive tape with
vacuum suction, moving up the chip holder, followed by air
blowing of the chip to accomplish full delamination of the
chip from the adhesive tape. First, the vacuum pressure Ptape
is applied to hold the adhesive tape, as shown in Fig. 2(a).
The process time of gripping the adhesive tape with vacuum
suction is 0.5 s, and the process time of the pick-up process
was designed to operate the product line effectively by the
manufacturer.
Fig. 2(b) depicts the chip holder lifting up the chip at a
height h in the peeling-off stage. In this stage, delamination
between the chip and the adhesive tape is initiated at the edge
of the chip, and it is gradually propagated to the center of
the chip. The process time of moving up of the chip holder
is 0.06 s. Subsequently, the pressure of the blowing air Pchip
blows up the delaminated chip over 0.5 s, during which the
chip is separated fully from the adhesive tape, as shown in
Fig. 2(c), and the chip collector picks up the delaminated chip
from the adhesive tape and moves it to the proper position for
the next packaging process [17].
B. Competing Fracture Criteria Between the
Chip Delamination From the Adhesive Tape
and Chip Cracking
For the fracture analysis of the whole chip-on-adhesive tape
structure, there are two variables to consider, G peel and σcrack ,
where G peel is the peeling energy release rate of the interface
between the chip and the adhesive tape and σcrack is the
Fig. 2. Mechanical modeling of chip-on-adhesive tape structure in die
pick-up process using air blow. (a) Vacuum sorption below the adhesive
tape. (b) Lifting of the chip holder. (c) Air blow and picking up of chip
using pick-up head.
maximum stress on the top surface of the chip, which is
responsible for the chip cracking failure. Fig. 3 shows the
mechanical model of the chip-on-adhesive tape structure. The
two major concerns, chip peeling off and chip cracking,
are shown in Fig. 3 and are considered as two competing
delamination and fracture paths. One is the chip cracking at
the top surface, which occurs when the maximum stress of
the chip is higher than the ultimate strength of the silicon
chip (σcSi : 146 MPa). The other is the interfacial delamination
at the interface between the chip and the adhesive tape. Note
that full delamination at the interface should occur without
chip cracking to guarantee a reliable die pick-up process.
In the analysis of the interfacial delamination of the chip
from the adhesive tape, the 90◦ wedge can be considered as
an initial crack with a zero length (Fig. 3) [18], [19]. The
chip is peeled off from the adhesive tape, which is similar
to the steady-state propagation of an interfacial crack. It was
assumed that the interfacial delamination propagates steadily
once the interfacial peeling energy release rate G reaches its
critical value, i.e., interfacial toughness G interface , based on
c
the Griffith criterion. On the other hand, the chip cracking
can be predicted by comparing the maximum stress of the
chip and the ultimate strength of the chip (σcSi ) since silicon
chips are brittle. Thus, criteria for the two fracture paths are
JEON et al.: ANALYSIS OF INTERFACIAL PEELING OF AN ULTRATHIN SILICON WAFER CHIP
Fig. 3. Chip-on-adhesive tape structure of mechanical model and two
competing failure modes.
as follows: G peel > G interface
c for interfacial delamination,
i.e., chip peeling off, and σcrack > σcSi for chip cracking.
If the chip peeling occurs first, the strain energy of the chip-
on-adhesive tape structure is released, σcrack stops increasing,
and thus, the chip is safe from damage. Conversely, when chip
cracking is initiated first, the interfacial peeling is suppressed.
Only one of the two modes will actually occur. For the chip
pick-up process, the interfacial peeling should occur first so as
not to lose the chip due to catastrophic chip cracking. Thus, it
is of significance to examine the competing mechanism of the
two behaviors. By combining the two criteria, the competing
relation criterion is obtained as follows:
G peel /G interface
C > σcrack /σcSi for chip pick-up (2)
G peel /G interface
C < σcrack /σcSi for chip cracking. (3)
When either value of G peel /G interface
C and σcrack /σcSi exceeds
the other first, the corresponding mode occurs. Fracture
behavior is indeterminate under the critical relation of
G peel /G interface = σcrack /σcSi . From (2) and (3), the competing
C 3 × 3 chip array and analyzed using ABAQUS 6.12 (Hibbit,
fracture criteria can be transformed as follows:
G peel /σcrack > G interface
c /σcSi for chip pick-up (4)
G peel /σcrack < G interface /σcSi for chip cracking. (5)
c
For convenience, a competing index  was defined as the
ratio of the peeling energy release rate to the chip cracking
stress in order to characterize the competing fracture behavior,
given as follows:
 ≡ G peel /σcrack . (6)
The relative tendency of the chip to be peeled off from
the substrate or to crack can be assessed using this index.
c = G interface
c /σcSi denotes the critical competing index deter-
mined by the silicon material and interface characteristics of
the chip-on-adhesive tape structure. Therefore, the competition
between peeling along the interface path and chip cracking on
1699
Fig. 4. FEM for the chip-on-adhesive tape structure.
the top surface of the die depends on the competing index and
its corresponding critical value with the following criteria:
 > c for chip pick-up (7)
 < c for chip cracking. (8)
In this paper, the process parameters that affect the
competing index, including the velocity of the chip holder and
the pressure of the blowing air, were evaluated.
IV. C OMPUTATIONAL M ODEL OF THE C HIP ON THE
A DHESIVE TAPE S UBSTRATE S TRUCTURE
A. Computational Model of the Chip-on-Adhesive
Tape Structure
To examine how the air blowing pressure and displacement
of the chip holder affect the competing fracture behavior of the
chip-on-substrate structure, an FEM of the chip-on-adhesive
tape structure was generated as a 1/4 symmetric model with a
Karlsson and Sorensen, USA). The computational model can
be briefly described as follows. Both the chip and adhesive
tape are taken to be linear elastic materials. The material
properties and dimensions of the materials used are listed in
Table I. Because of the symmetry, a fourth of the chip-on-
adhesive structure was modeled, as shown in Fig. 4. An eight-
node linear brick element with reduced integration (C3D8R)
was used for the chip, adhesive tape, and chip holder. The
boundary conditions XSYMM and YSYMM were applied
on the whole model, as shown in Fig. 4, where XSYMM
is the symmetric constraint about the plane with a constant
x-coordinate, U1 = UR2 = UR3 = 0. Likewise, YSYMM
is the symmetric constraint about the plane with a constant
y-coordinate, U2 = UR1 = UR3 = 0. The pressure for the
vacuum suction and pressure of the blowing air were modeled
as a distributed uniform pressure under the adhesive tape.
1700 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 06, NO. 11, NOVEMBER 2016

Fig. 5. Fracture interface element with dummy nodes.

A distributed load resulting from the blowing air Pchip was

applied to the bottom of the adhesive tape. The friction
between the adhesive tape and the chip holder was neglected.
The chip holder was composed of two parts, an inner part
(plate shape) and an outer part, as shown in Fig. 4. There
is a gap with height h between the outer part of the chip
holder and the inner part of the chip holder. The role of the
outer part of the chip holder is to move the chip up. The
inner part of the chip holder supports the bended chip to
prevent excessive bending of the chip by the vacuum suction.
The detailed information of the chip holder is not shown
in this paper due to a confidentiality agreement with the
manufacturer (Samsung Electronics, Korea). The chip holder
could move up only along the z-direction as a function of
the velocity of the chip holder, where the other degrees of
freedom were restricted. The energy release rate of the chip-
on-adhesive interface and chip maximum stress were evaluated
using VCCT with dummy nodes, which was implemented Fig. 6. (a) Energy release rate at the chip/adhesive interface and maximum
using user-defined elements’ subroutines. The properties of the stress of the chip as functions of mesh size from 4 to 25 μm. (b) Chain index
interface between the chip and the adhesive tape were applied of the variations of energy release rate and chip cracking stress.
from the 90° peel test, as listed in Table II. The VCCT with
dummy nodes is briefly described in Section IV-B. where G I , G II , and G III are the respective contributions
of mode I (normal opening), mode II (in-plane shear), and
B. VCCT With Dummy Nodes mode III (out-plane shear) to the energy release rate [22].
Based on the VCCT, Xie and Biggers [20], [21] developed The three components of the energy release rate are shown
an interface element called fractured elements with dummy as follows [20]:
nodes, which can extract information for displacement open- G I = (Fy ν)/2Ba G II = G III = (Fx u)/2Ba (10)
ings behind the crack tip and the virtual crack jump ahead of it.
Therefore, through this interface element, great integration of where u and v are the two components of the displacement
the FEA and post-process calculations of the parameters of openings behind the crack tip, Fx and Fy are the nodal forces
the fracture mechanics is achieved and the energy release rate at the crack tip, a is the crack jump length, and B is the
can be calculated simultaneously as the FEA is performed. thickness of the body. G III is the same as G II because the
Fig. 5 shows the algorithm of this fracture interface element. adhesive tape is an isotropic material.
It is composed of five nodes numbered from 1 to 5, three of V. A NALYSIS OF THE C HIP P ICK -U P P ROCESS
which (3–5) are dummy nodes. The dummy nodes are those
A. Mesh Sensitivity Analysis
used merely to extract information from the FEA and do not
contribute to the rigidity matrix of the element. Nodes 1 and 2 A mesh sensitivity analysis was conducted as a part of
are located at the crack tip, nodes 3 and 4 are behind, and the FEA. The chip and the adhesive tape were meshed with
node 5 is ahead of the crack tip. A strong spring is placed elements of different sizes ranging from 4 to 25 μm. The
between nodes 1 and 2 in order to calculate the nodal forces velocity of the chip holder and the pressure of blowing air
at the crack tip [13]. The total peeling energy release rate G is were 50 mm/s and 60 kPa, respectively. The set of mesh
defined as follows: sizes and the corresponding energy release rates and maximum
stress of the chip were plotted, as shown in Fig. 6(a). To show
G = G I + G II + G III (9) how much their values vary relative to the neighboring values,
JEON et al.: ANALYSIS OF INTERFACIAL PEELING OF AN ULTRATHIN SILICON WAFER CHIP
Fig. 7. Maximum stress of the chip and BDSTAT of the adhesive tape during
the die pick-up process. (a) Vacuum sorption. (b) Moving up of chip holder.
(c) Air blow and chip picking up.
the chain indices of the variations are plotted in Fig. 6(b).
When the mesh size is greater than 12.5 μm, the energy
release rate and chip cracking stress vary below 4% and 1%,
respectively. Considering both convergence and computational
cost, it is suggested that a mesh size of 12.5 μm is optimal.
Based on the mesh sensitivity study, a mesh size of 12.5 μm
was selected for the FEA.
B. Effect of the Velocity of the Chip Holder
Fig. 7 shows the stress distribution of the chip and bonding
state of the adhesive tape during the die pick-up process.
For convenience, the output of the FEA was mirrored by the
xz-plane and yz-plane. The BDSTAT variable in the ABAQUS
results indicates the bonding state of the interface between the
chip and the adhesive tape. Red corresponds to a fully bonded
interface between the chip and the adhesive tape, while blue
corresponds to the delaminated region of the adhesive tape.
When the vacuum suction of the adhesive tape is applied,
the stress distribution of the chip is lower than the critical
strength of the chip, as shown in Fig. 7(a). In the case of the
vacuum suction stage, BDSTAT shows a red color in the entire
adhesive tape layer because delamination at the chip/adhesive
interface did not occur yet. After the chip holder moved up,
the maximum stress occurred at the edge of the chip while the
delamination was initiated from the edge of the adhesive tape
and then the chip was detached partially from the adhesive
tape [Fig. 7(b)]. Also, the remaining bonded area was found
in the center of the chip. In the air blowing stage, the center
of the chip showed a higher stress distribution than the edge
of the chip due to the delamination of the remaining bonded
region. In addition, it was found that the chip was separated
fully from the adhesive tape, as shown in Fig. 7(d).
Fig. 8(a) shows the energy release rate and the maximum
stress of the chip with respect to the velocity of the chip
holder. The air blowing pressure was fixed at 60 kPa in all
cases. It was found that the maximum stress of the chip
increased greatly as the velocity of the chip holder increased
[Fig. 8(c)]. This is because the chip was deformed more at
higher displacements due to the same process time (0.06 s)
with a higher velocity of the chip holder, as shown in Fig. 8(c).
1701
Fig. 8. (a) Energy release rate and maximum stress of chip as a function
of the velocity of the chip holder. (b) Competing index c = G interface
c /σcSi .
(c) Maximum stress and displacement of the chip. (d) Microscope images of
the failed ultrathin NAND flash memory chip in the die pick-up process.
The energy release rates G I , G II , and G III increased slightly
as the velocity of the chip holder increased, which is similar
to previous results [4], [13]. Fig. 8(b) shows the competing
index with respect to the velocity of the chip holder. The
critical competing index c = G interface
c /σcSi was calculated
based on the critical energy release rate and the chip cracking
strength shown in Table I. Note that as the higher peeling
speed increases, G interface
c increases, and thus the critical
competing index increased with a larger chip moving velocity
[Figs. 1(d) and 8(b)]. The intersections of this line with the
critical competing index curve c represent the critical points
as a function of the velocity of the chip holder, below which
chips will not be detached from the adhesive tape, but chip
cracking occurred. It was found that above a moving speed
of 100 mm/min, the maximum stress of the chip becomes
higher than the chip cracking stress of 146 MPa, as shown in
Fig. 8(a). Therefore, it could be concluded that the velocity of
the chip holder should be lower than 50 mm/min to prevent the
potential risk of chip cracking in an actual process. To verify
the analysis, the chip was moved with a velocity of the holder
of 250 mm/min in the actual pick-up process. It was found
that the chip was fractured at the edge of the chip due to
the geometry of the chip holder, as shown in Fig. 8(d). The
fractured region coincided well with the FEA results shown
in Fig. 8(c).
C. Effect of the Air Blowing Pressure
Fig. 9(a) shows the energy release rate at the chip/adhesive
tape interface and the maximum stress of the chip with respect
to the air blowing pressure. The velocity of the chip holder
was fixed at 50 mm/min in all cases, as determined above. The
energy release rate increased slightly as the air blowing pres-
sure was increased, demonstrating that a higher air blowing
pressure affects chip peeling. The maximum stress of the chip
occurred in the center of the chip [Fig. 9(c)] because the air
blowing bends the chip with a convex shape [see displacement
1702 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 06, NO. 11, NOVEMBER 2016
Fig. 9. (a) Energy release rate and maximum stress of chip as function of the
air blow pressure. (b) Competing index c = G interface
c /σcSi . (c) Maximum
stress and displacement of the chip. (d) Microscope image of the failed
ultrathin NAND flash memory chip in the die pick-up process.
distribution in Fig. 9(c)]. Also, the maximum stress area
becomes concentrated in the center area as the air blowing
pressure increases due to the higher bending displacement,
as shown in Fig. 9(c). A higher bending displacement may
result from the fact that the viscoelastic force of the adhesive
tape increases when a larger force is applied on the viscoelastic
adhesive tape material connecting the chip and the substrate.
In addition, the displacement along the z-direction increased
as the air blowing pressure increased. The competing index 
decreased as the maximum stress became larger than the
increase in the total energy release rate, as shown in Fig. 9(b).
In the case of an air blowing pressure of 120 kPa, the
competing index was lower than the critical competing index
as the maximum stress of the chip was higher than the ultimate
strength of the chip. This was also verified in the experiment
where the chip was fractured at the center of the chip with an
air blowing pressure of 120 kPa in the actual pick-up process,
as shown in Fig. 9(d), which is similar to the FEA results
[Fig. 9(c)]. It can be concluded that the air blowing pressure
should be lower than 90 kPa to prevent chip cracking
VI. C ONCLUSION
In this paper, a competing index was defined to characterize
the competing fracture behavior between the chip cracking and
chip peeling off in the die pick-up process with air blowing.
In addition, FEA of the die pick-up process with VCCT was
performed to predict the stable chip peeling off with respect
to the velocity of the chip holder and the air blowing pressure.
The results show that the velocity of the chip holder and the
air blowing pressure should be lower than 50 mm/min and
90 kPa, respectively, to accomplish the die pick-up process
without chip cracking.
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Eun-Beom Jeon, photograph and biography not available at the time of
publication.
Sung-Hyeon Park, photograph and biography not available at the time of
publication.
Yun-Sik Yoo, photograph and biography not available at the time of
publication.
Hak-Sung Kim, photograph and biography not available at the time of
publication.