8085A Instruction Set Reference Encyclopedia’ * Courtesy of Intel Corporation. 467THE INSTRUCTION SET INSTRUCTION SET ENCYCLOPEDIA In the ensuing dozen pages, the complete 8085A instruction set is described, grouped in order under five different functional headings, as follows: 1. Data Transfer Group — Moves data be- tween registers or between memory locations and registers. includes moves, Toads, stores, and exchanges. 2. Arithmetic Group — Adds, subtracts, in- crements, or decrements data’ in registers or memory. 3. Logic Group — ANDs, ORs, XORs, com- partes, rotates, or complements data in registers or between memory and a register. 4, Branch Group — Initiates conditional or unconditional jumps, calls, returns, and restarts. 5. Stack, VO, and Machine Control Group — Includes instructions for maintaining the stack, reading from input ports, writing to output ports, setting and feading interrupt masks, and setting and clearing flags. ‘The formats described in the encyclopedia feflect the assembly language processed by Intel-supplied assembler, used with the intellec® development systems. Dota Transfer Group ‘This group of instructions transters data to and from registers and memory. Condition flags not affected by any instruction in this group. MOV rt, 72 y= ‘The content of register 12 is moved to register 11 (Move Register) MOV1,M_ (Move from memory) (GH) L) ‘The content of the memory location, whose address is in registers H and L, is moved to register F. reg. indirect MOV M,r (Move to memory) HY) — 40) The content of register r is moved to the memory location whose address is in registers H and L. TTT TTT o 1 1 1 o]s ss Cycles: 2 States: 7 Addressing: reg. indirect Flags: none MVIr, data (Move Immediate) (f) — @yte 2) ‘The content of byte 2 of the instruction is moved to register T Team lal o o}o dv o]1 14 0 data Cycles: 2 States: 7 Addressing: immediate Flags: none MVIM,data (Move to memory immediate) HY (L) ~ (byte 2) The content of byte 2 of the instruction is moved to the memory location whose ad- dress is in registers H and L. T a naa o 1/0 do v]s ss ToT Tt oo 41 1°04 1 °0 Cycles: 1 States: 4 (8085), 5 (6080) Addressing: register Flags: none AM moemonies eopysighted Ine! Corporation 176 data Cycles: 3 States: 10 Addressing: immed Jreg. indirect Flags: noneTHE INSTRUCTION SET LXI rp, data 16 (Load register pair immediate) (ch) — (byte 3), (e) — (byte 2) Byte 3 of the instruction is moved into the high-order register (rh) of the register pair fp. Byte 2 of the instruction is moved into the low-order register (1) of the ragister pair 'P. LHLD addr (Load H and L direct) (L)=((byte 3ybyte 2) (H)—(oyte 3Nbyte 2)+-1) ‘The content of the memory Igcation, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register L. The content of the memory location at the suc> ceeding address is moved to register H. T T7711 o o}/R Pj}o 0 0 1 aa o 0 10 1 0 1 0 low-order data loworder addr LDA addr high-order data high-order addr Cycles: 3) Gyles: 5 States: 10 States: 16 Addressing: immediate Addressing: direct Flags: none (Load Accumulator direct) (A) — ((oyte 3ybyte 2) The content of the memory location, whose address Is specified in byte 2 and byte 3 of moyed to register A. TTT _T 1 0 410 low-order addr high-order addr STA addr cycles: 4 States: 13 Addressing: direct Flags: none (Store Accumulator direct) (byte Sybyte 2) ~ (A) ‘The content of the accumulator is moved to the memory location whose address is specified in byte 2 and byte Sof the instruc- tion, a oo 1 1 0 0 4 0 low-order addr SHLD addr LDAX rp Flags: none. (Store H and L direct) (byte SNbyte 2))—(L) (byte 3ybyte 2)+1)—(H) The content of register L is moved to the memory location whose address is specified in byte 2 and byte 3. The content of register H Is moved to the succeeding memory location. o°0 10 0 0 1 0 low-order addr high-order addr Cycles: 5 States: 16 Addressing: direct Flags) none (Load accumulator indirect) (A) — (ep) The content of the memory location, whose address is in the register pair ¢p, is moved to register A. Note: only register pairs (p=B (registers B and ©) or m=D (egisters D and E) may be specified high-order addr ia eee alee o ofr pP}]1 0 4 0 Cycles: 4 States) 13, Addressing: direct Flags: none “AN anamonics copyrighted ate Corparation 1976 Cycles: 2 States: 7 Addressing: reg. indirect Flags: noneTHE INSTRUCTION SET PCHL (Qump H and L indirect — move H and L to PC) (PCH) ~ (H) (PCL) ~ (L) The content of register H Is moved to the high-order eight bits of register PC. The content of register L is moved to the low- order eight bits of register PC. Cycles: 1 States: 6 (8085), 5 (8080) Addressing: register Flags: none Stack, VO, and Machine Control Group ‘This group of instructions performs VO, manipu- lates the Stack, and alters internal controt flags. Unless otherwise specified, condition flags are not affected by any Instructions in this group. PUSH rp (Push) (SP) — 1) - (eh) (SP) - 2) ~ (ol) (SP) — (SP) - 2 The content of the high-order register of register pair rp is moved to the memory location whose address is one less than the content of register SP. The content of the low-order register of register pair 1p is moved to the memory tocation whose ad. dress is two less than the content of register SP. The content of register SP is decremented by 2. Note: Register palr rp = SP may not be specified. Tre Sasa le 1 t{rR plo 1 04 Cyolos: 3 States: 12 (8085), 11 (8080) Addressing: reg. indirect Flags: none PUSH PSW (Push processor status word) (SP) - 1) - A) (SP) = 2p — (GY), (SP) — 2, — X MSP) - 2p ~ (P), (SP) — Ze ~ X (SP) ~ 2e ~ (AC) (SP) — 25 — X (SP) ~ 2, ~ 2), (SP) ~ 27 ~ 8) (SP) ~ (SP) - 2 X: Undetined. “ha mnemonics copyrighted inte Corporation 1976. The content of register A is moved to the memory location whose address is one Jess than register SP. The contents of the Condition flags are assembled into a pro- cessor status word and the word is moved to the memory location whose address is two less than the content of register SP. ‘The content of register SP is decremented by two. Cycles: 3 States: 12 (8085), 11 (8080) Addressing: reg. indirect, Flags: none FLAG WORD Dy Dy Ds Dy Dy Dz Dy Dp s|[z|x fac} x] P| x |or X: undefined POP ip (Pop) (0) ~ «SPD (om) — (SP) +) (SP) (SP) +2 The content of the memory location, whose address is specified by the content of register SP, is moved to the low-order register of register pair rp. The content of the memory location, whose address is one more than the content of register SP, is moved to the high-order rogister of register fp. The content of register SP is in- T T lS a yo1}R Plo oO 0 4 Gycles: 3 States: 10 Addressing: reg.indirect Flags: oneTHE INSTRUCTION SET STAX rp (Store accumulator indirect) rp) — (A) The content of register A is moved to the memory location whose address is in the register pair rp. Note: only register pairs (registers B and C) or rp=D (egisters D and E) may be specified. TTT 7 TTT o ofR Pio o 1 0 Gyoles: 2 States: 7 Addressing: reg. indirect Flags: none XCHG (€xchange H and L with D and ) (H) ~ (0) O-68 The contents of registers H and L are ex. changed with the contents of registers D and E. a toto 40 1 0°44 Gyotes: 4 States: 4 Addressing: register Flags: none Arithmetic Group This group of instructions performs arithmetic operations on data in registers and memory. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Carry, according to the stan: and Auxiliary Carry fla dard rules. All subtraction operations are performed via two's complement arithmetic and set the carry flag to one to indicate a borrow and clear it to indicate no borrow. ADD r (Add Register) A) +0 ‘The content of register r is added to the content of the accumulator. The result is placed in the accumulator. ADD M (Add memory) (A) = (A) (4) (D) The content of the memory location whose address is contained in the H and L registers is added to the content of the ac- cumulator. The result is placed in the ac ‘cumulator. ADI data Cycles: 2 States. 7 Addressing: reg. indirect Flags: Z,3,P,CY,AC (Add immediate) (A) — (A) + (byte 2) The content of the second byte of the struction is added to the content of the ac- cumulator. The result is placed in the ac- cumulator. cycles: 2 States: 7 Addressing: immediate Flags: Z,S,P,CY.AC ape r (Add Register with carry) (A) — A) + (9) + (CY) ‘The content of register r and the content of the carry bit are added to the content of the accumulator. The result is placed in the ac- cumulator. ia TT 1 0 0 0 o|s ss Cycles: 1 States: 4 Addressing: register Flags: 2,S,P,CY,AC “A maomonios copyrighted intel Corpora Cycles: 1 States. 4 Addressing: register Flags: Z.S,P,CY,AC