Date Sheet No. Cycle - 1: Index

Name: J Prashanth Roll No: 17071A0484
INDEX
Date Sheet No.
Cycle – 1
1. Realisation of all logic gates using Dataflow and Behavioural Modelling
Styles
2. Design of Multiplexers
a. 2 to 1 Mux using all modelling styles
b. 4 to 1 using 2 to 1 Mux
c. 8 to 1 using 4 to1 Mux and 2 to 1 Mux
3. Design of Encoders
a. 4 to 2 Encoder using all modelling styles
b. Priority Encoder
4. Design of Decoders
a. 2 to 4 Decoder using all Modelling styles
b. 3 to 8 Decoder using 2 to 4 Decoder
5. Design of Adders
a. Half adder using all Modelling styles
b. Full Adder using all Modelling Styles
6. Design of Code Converters
a. Gary to binary
b. Binary to Gray
7. Design of 2-Bit comparator using all modelling Styles
8. Design of Flip-Flips
a. JK Flip-Flop using Preset and Clear
b. SR Flip-Flop using Preset and Clear
c. D Flip-Flop using JK Flip-Flop
d. T Flip-Flop using JK Flip-Flop
9. Design of Counters
a. BINARY Counter
b. BCD Counter
10. Design of Shift registers
a. SISO, SIPO, PISO, PIPO
11. Design of FSM
a. JK Flip-Flop
CYCLE-II
12. Design and Simulation of CMOS Inverter
13. Design and Simulation of CMOS NAND
1
14. Design and Simulation of CMOS NOR
15. Design and Simulation of CMOS XOR
16. Design and Simulation of CMOS MUX
17. Design and Simulation of SR Flip Flop
18. Design and Simulation of JK Flip Flop
19. Design and Simulation of D Flip Flop
20. Design and Simulation of T Flip Flop
2
EXPERIMENT-1
REALIZATION OF LOGIC GATES
1. AIM: Design, simulate and implement logic gates using Synopsys Tools.
2. SOFTWARE USED: Xilinx
3. SIMULATOR USED: iSim
4. SYNTHESIZER USED: XST
5. PROCEDURE:
a. Write the program code in Behavioural modelling, Dataflow modelling and Structural modelling styles
for all logic gates.
b. Next execute this code in the ISE project navigator by first clicking the “Behavioural Check Syntax”
option.
c. After checking the syntax successfully, next go for the option “Simulate Behavioural Model” which
simulates the function of the program in the ISIM tool.
d. For the Implementation of the code check the Implementation option and go for the option “View RTL
Schematic” for the synthesis of the program code.
6. Verilog Reports:
Behavioural modelling for all Logic Gates

AND Gate:
module
loggates(yand,a,
b);
input a,b;
output reg yand;
always @(a,b)
begin
case({a,b})
2'b00:begin
yand = 0; end
2'b01:begin
yand = 0; end
2'b10:begin
yand = 0; end
2'b11:begin
yand = 1; end
endcase
end
endmodule
3
Simulation result:
OR Gate:
module
loggates(yor,a,b);
input a,b;
output reg yor;
always @(a,b)
begin
case({a,b})
2'b00:begin yor = 0;
end
end
end
end
endcase
end
endmodule
Simulation result:
4
NAND Gate:
module
loggates(ynand,a,b
);
input a,b;
output reg ynand;
always @(a,b)
begin
case({a,b})
2'b00:begin ynand
= 1; end
2'b01:begin ynand
= 1; end
2'b10:begin ynand
= 1; end
2'b11:begin ynand
= 0; end
endcase
end
endmodule
Simulation result :
NOR Gate:
module
loggates(ynor,a,b)
;
input a,b;
output reg ynor;
always @(a,b)
begin
case({a,b})
2'b00:begin ynor =
1; end
2'b01:begin ynor =
0; end
2'b10:begin ynor =
0; end
2'b11:begin ynor = 0;
end
endcase
end
endmodule
5
Simulation result:
EX-OR Gate:
module
loggates(yxor,a,b)
;
input a,b;
output reg yxor;
always @(a,b)
begin
case({a,b})
2'b00:begin yxor
= 0; end
2'b01:begin yxor
= 1; end
2'b10:begin yxor
= 1; end
2'b11:begin yxor
= 0; end
endcase
end
endmodule
Simulation result:
6
EX-NOR Gate:
module
loggates(yxnor,a,b);
input a,b;
output reg yxnor;
always @(a,b)
begin
case({a,b})
2'b00:begin yxnor =
1; end
2'b01:begin yxnor =
0; end
2'b10:begin yxnor =
0; end
2'b11:begin yxnor =
1; end
endcase
end
endmodule
Simulation results:
7
Dataflow Modelling (Using Assign Statements)
OR Gate:
module
loggates(yor,a,b);
input a,b;
output yor;
assign yor = a | b;
endmodule
Simulation result:
AND Gate:
module
loggates(yand,a,b);
input a,b;
output yand;
assign yand = a & b;
endmodule
8
Simulation result:
NAND Gate :
module
loggates(ynand,a,b)
;
input a,b;
output ynand;
assign ynand = ~ (a
& b);
endmodule
Simulation result:
NOR Gate:
module
loggates(ynor,a,b);
input a,b;
output ynor;
assign ynor = ~ (a |
b);
endmodule
9
Simulation result:
EX-NOR Gate:
module
loggates(yxnor,a,b);
input a,b;
output yxnor;
assign yxnor = ~ (a ^ b);
endmodule
Simulation result:
7. Result: Designed and Implemented all the basic logic gates using data flow and
behavioral modelling using Xilinx ISE Tool.
10
EXPERIMENT-2
DESIGN OF MULTIPLEXERS
(a). AIM: Design, simulate and implement of 2 to 1 Multiplexer in all modelling styles using
Synopsys Tools.
SOFTWARE USED: Xilinx
SIMULATOR USED: iSim
SYNTHESIZER USED: XST
PROCEDURE:
for 2 to 1 MUX.
option.
Verilog Reports:
Behavioral modelling of 2 to 1 Mux

2 to 1 MUX
module
mux21(in0,in1,sel,out);
input in0,in1, sel;
output reg out;
always @(*)
begin
if(sel)
out= in1;
else
out=in0;
end
endmodule
11
Simulation result:
Data Flow Modelling of 2 to 1 MUX

2 to 1 MUX:
module
input in0,in1, sel;
output out;
assign out = (sel)?in1:in0;
endmodule
Simulation result:
12
Structural Modelling of 2 to 1 MUX

2 to 1 MUX:
module
input in0,in1,sel;
output out;
wire [1:0]t;
wire selb;
and (t[1],in1,sel) ,
(t[0],in0,selb);
not (selb,sel);
or (out,t[1],t[0]);
endmodule
Simulation result:
RESULT: Designed and Implemented 2 to 1 Mux in structural, data flow and behavioral modelling styles
using Xilinx ISE Tool.
13
(b). AIM: Design, simulate and implement of 4 to 1 Mux using 2 to 1 Mux using
Synopsys Tools.
PROCEDURE:
for all logic gates.
option.
Verilog Reports:
4 to 1 MUX using 2 to 1 MUX

module
mux41(y,d0,d1,d2,d3,s0,s1);
input s0,s1,d0,d1,d2,d3;
output y;
wire w1,w2;
mux21s m1(w1,s0,d0,d1);
mux21s m2(w2,s0,d2,d3);
mux21s m3(y,s1,w1,w2);
endmodule
14
Simulation result:
RESULT: Designed and Implemented 4 to 1 Mux using 2 to 1 Mux using Xilinx ISE Tool.
(c). AIM: Design, simulate and implement of 8 to 1 Mux using 4 to 1 Mux and 2 to 1 Mux using
Synopsys Tools.
PROCEDURE:
a. Write the program code in Behavioural modelling and Dataflow modelling styles for 4 to 1 MUX using 2
to 1 MUX.
option.
15
Verilog Reports:
8 to 1 MUX
module
mux81(y,d7,d6,d5,d4,d3,d2,d1,d0,s0,s1,s2
);
input s0,s1,s2;
input d7,d6,d5,d4,d3,d2,d1,d0;
output y;
wire w1,w2;
mux41 m1(w1,d0,d1,d2,d3,s0,s1);
mux41 m2(w2,d4,d5,d6,d7,s0,s1);
mux21s m3(y,s2,w1,w2);
endmodule
Simulation result:
Result: Designed and Implemented 8 to 1 Mux using 4 to 1 and 2 to 1 Mux using Xilinx ISE Tool.
16
EXPERIMENT-3
Design of Encoders
(a). AIM: Design, simulate and implement of 4 to 2 Encoder in all modelling styles using
Synopsys Tools.
PROCEDURE:
for 4 to 2 Encoder.
b. Next execute this code in the ISE project navigator by first clicking the “behavioural Check Syntax”
option.
c. After checking the syntax successfully, next go for the option “Simulate behavioural Model” which
Verilog Reports:
Behavioral Modelling Style

4 to 2 Encoder
module en42(y,x,en);
input [3:0]x;
input en;
output reg [1:0]y;
always @(x,en)
begin if(en==1'b1)
case({x})
4'b0001: y = 2'b00;
4'b0010: y = 2'b01;
4'b0100: y = 2'b10;
4'b1000: y = 2'b11;
endcase
end
endmodule
17
Simulation result:
Dataflow Modelling Style

4-2 Encoder
module en42(y,x,en);
input [3:0]x;
input en;
output [1:0]y;
assign y[0] = x[1] |
x[3];
assign y[1] = x[2] |
x[3];
endmodule
Simulation result:
RESULT: Designed and Implemented 4 to 2 Encoder in data flow and behavioral modelling styles using
Xilinx ISE Tool.
18
(b). AIM: Design, simulate and implement of 4 to 2 priority Encoder using Synopsys Tools.
PROCEDURE:
a. Write the program code in Behavioural modelling style for 4 to 2 Priority Encoder.
option.
Verilog Reports:
4 to 2 Priority Encoder
module
pr_en(y,x,en)
;
input [3:0]x;
input en;
output reg
[1:0]y;
always
@(x,en)
begin
if(en==1'b1)
casex({x})
4'b0001 : y =
2'b00;
4'b001x : y =
2'b01;
4'b01xx : y =
2'b10;
4'b1xxx : y =
2'b11;
endcase
end
endmodule
19
Simulation result:
RESULT: Designed and Implemented 4 to 2 Priority Encoder in data flow and behavioral modelling styles
20
EXPERIMENT-4
DESIGN OF DECODERS
(a). AIM: Design, simulate and implement of 2 to 4 Decoder in all modelling styles using
Synopsys Tools.
PROCEDURE:
for 2 to 4 Decoder.
option.
Verilog Reports:
Behavioral modelling of 2 to 4 Decoder

2 to 4 Decoder
module
dec24(d,x,en);
output reg [3:0]d;
input [1:0]x;
input en;
always @(x,en)
begin if(en==1'b1)
casex({x})
2'b00 : d =
4'b0001;
2'b01 : d =
4'b0010;
2'b10 : d =
4'b0100;
2'b11 : d =
4'b1000;
endcase
end
endmodule
21
Simulation result:
Dataflow modelling of 2 to 4 Decoder

2 to 4 Decoder
module dec24(d,x);
output [3:0]d;
input [1:0]x;
assign d[0] = ~x[1] &
~x[0];
assign d[1] = ~x[1] & x[0];
assign d[2] = x[1] & ~x[0];
assign d[3] = x[1] & x[0];
endmodule
Simulation result:
RESULT: Designed and Implemented 2 to 4 Decoder in data flow and behavioral modelling styles using
Xilinx ISE Tool.
22
(b). AIM: Design, simulate and implement of 3 to 8 Decoder using 2 to 4 decoder using
Synopsys Tools.
PROCEDURE:
a. Write the program code for 3 to 8 decoders using 2 to 4 decoder.

option.
Verilog Reports:
3 to 8 decoder using 2 to 4 decoder

module dec328(d,a);
input [2:0]a;
output [7:0]d;
dec2to4
d1(d[7:4],a[1:0],a[2]);
dec2to4
d2(d[3:0],a[1:0],~a[2]);
endmodule
23
Simulation result:
RESULT: Designed and Implemented 3 to 8 Decoder using 2 to 4 Decoder using Xilinx ISE Tool.
24
EXPERIMENT-5
DESIGN OF ADDERS
(a). AIM: Design, simulate and implement of Half adder in all modelling styles using
Synopsys Tools.
PROCEDURE:
for Half adder.
option.
Verilog Reports:
Behavioral modelling of Half Adder

Half Adder
module
ha(s,cout,a,b)
;
input a,b;
output reg
s,cout;
always
@(a,b)
begin
{cout,s} = a +
b;
end
endmodule
25
Simulation result:
Dataflow modelling of Half Adder

Half Adder
module
ha(s,cout,a,b);
input a,b;
output s,cout;
assign s = a ^ b;
assign cout = a & b;
endmodule
Simulation result:
RESULT: Designed and Implemented Half Adder in data flow and behavioral modelling styles using Xilinx
ISE Tool.
26
(b). AIM: Design, simulate and implement of Full Adder using Synopsys Tools.
PROCEDURE:
for Full adder.
option.
Verilog Reports:
Behavioral modelling of Full Adder

Full Adder
module
fa(s,cout,a,b,cin);
input a,b,cin;
output reg s,cout;
always @(a,b,cin)
begin
{cout,s} = a + b +
cin;
end
endmodule
27
Simulation results:
Dataflow modelling of Full Adder

Full Adder
module
fa(s,cout,a,b,cin)
;
input a,b,cin;
output s,cout;
assign s = a ^ b ^
cin;
assign cout = a &
b | b & cin | cin
& a;
endmodule
Simulation results:
28
Structural modelling of Full Adder

Full Adder
module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire [2:0]w;
xor x1(s,a,b,cin);
and a1(w[0],a,b);
and a2(w[1],b,cin);
and a3(w[2],cin,a);
or
o1(cout,w[0],w[1],w[2]);
endmodule
Simulation results:
RESULT: Designed and Implemented Full Adder in structural, data flow and behavioural modelling styles
29
EXPERIMENT-6
DESIGN OF CODE CONVERTERS
(a). AIM: Design, simulate and implement of Gray to Binary Code converter using
Synopsys Tools.
PROCEDURE:
a. Write the program code for Gray to Binary code converter.

option.
schematic” for the synthesis of the program code.
Verilog Reports:
Gray to Binary Code Converter

module gry2bin(b,g);
input [3:0]g;
output [3:0]b;
assign b[3] = g[3];
assign b[2] = b[3] ^ g[2];
assign b[1] = b[2] ^ g[1];
assign b[0] = b[1] ^ g[0];
endmodule
30
Simulation results:
Binary to Gray
module bin2gray(bin,G);
input [3:0]bin;
output [3:0]G;
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
endmodule
Simulation result:
Result : Implemented binary to gray and Gray to binary code converters using ISE tool.
31
EXPERIMENT-7
DESIGN OF 2-BIT COMPARATOR
AIM: Design, simulate and implement of 2-bit comparator in all modelling styles using Synopsys Tools.
PROCEDURE:
for 2-bit comparator.
option.
Verilog Reports:
Dataflow modelling of 2-Bit Comparator

2-bit Comparator
module bit_comp(a,b,g,e,l );
input [1:0]a;
input [1:0]b;
output g,e,l;
assign g = (a[1] & ~b[1]) |
(a[0] & ~b[0] & ~b[1]) | (a[1]
& a[0] & ~b[0]);
assign e = ~(a[0] ^ b[0]) &
~(a[1] ^ b[1]);
assign l = (~a[1] & b[1]) |
(~a[1] & ~a[0] & b[0]) | (~a[0]
& b[1] & b[0]);
endmodule
32
Simulation result:
Behavioral modelling of 2-Bit Comparator

2 bit Comparator
module bit_comp(a,b,g,e,l); begin
input [1:0]a; g = 1'b0;
input [1:0]b; e = 1'b0;
output reg g,e,l; l = 1'b1;
always @(a,b) end
begin else
if(a==b) begin
begin g = 1'b1;
g = 1'b0; e = 1'b0;
e = 1'b1; l = 1'b0;
l = 1'b0; end
end end
else if(a<b) endmodule
Simulation result:
33
Implementation of RTL View:
RESULT: Designed and Implemented 2-Bit Comparator in data flow and behavioral modelling styles using
Xilinx ISE Tool.
34
EXPERIMENT-8
DESIGN OF FLIP-FLOPS
(a). AIM: Design, simulate and implement of JK Flip Flop using preset and clear using Synopsys Tools.
SOFTWARE USED: Xilinx 14.2
PROCEDURE:
a. Write the program code for JK Flip Flop.

b. Next execute this code in the ISE project navigator by first clicking the “Behavioral Check Syntax”
option.
c. After checking the syntax successfully, next go for the option “Simulate Behavioral Model” which
Schmatic” for the synthesis of the program code.
Verilog Reports:
JK Flipflop
module jkf(q,qb,j,k,clk,clr,prs);
input j,k,clk,clr,prs;
output reg q;
output qb;
assign qb = ~q;
always @ (posedge clk)
begin
if(clr) begin
q <= 1'b0;
end
else if(prs) begin
q <= 1'b1;
end
else begin
case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 1'b0;
2'b10 : q <= 1'b1;
2'b11 : q <= ~q;
endcase
end
end
endmodule
35
Simulation result:
RESULT: Designed and Implemented JK Flip Flop using Xilinx ISE Tool
36
(b). AIM: Design, simulate and implement of SR Flip Flop using preset and clear using Synopsys Tools.
Verilog Code:
SR FlipFLop
module srff(q,qb,s,r,clk,clr,prs);
input s,r,clk,clr,prs;
output reg q;
output qb;
assign qb = ~q;
begin
if(clr) begin
q <= 1'b0;
end
else if(prs) begin
q <= 1'b1;
end
else begin
case ({s,r})
2'b00 : q <= q;
2'b01 : q <= 1'b0;
2'b10 : q <= 1'b1;
endcase
end
end
endmodule
Simulation result:
37
RTL View:
RESULT: Designed and Implemented JK Flip Flop using Xilinx ISE Tool
38
(c). AIM: Design, simulate and implement of D Flip Flop using JK Flip Flop using Synopsys Tools.
Verilog Code
D Flipflop Using JK Flipflop

module dujk(q,qb,d,clk,clr,prs);
input d,clk,clr,prs;
output q;
output qb;
jkf d1(q,qb,d,~d,clk,clr,prs);
endmodule
module jkf(q,qb,j,k,clk,clr,prs);
output reg q;
output qb;
assign qb = ~q;
begin
if(clr) begin
q <= 1'b0;
end
else if(prs) begin
q <= 1'b1;
end
else begin
case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 1'b0;
2'b10 : q <= 1'b1;
2'b11 : q <= ~q;
endcase
end
end
endmodule
39
RTL View:
Simulation result:
RESULT: Designed and Implemented D Flip Flop using JK Flip Flop using Xilinx ISE Tool.
40
(d). AIM: Design, simulate and implement of T Flip Flop using JK Flip Flop using Synopsys Tools.
T flipflop using JK Flipflop

module tujk(q,qb,t,clk,clr,prs);
input t,clk,clr,prs;
output q;
output qb;
jkf1 d1(q,qb,t,t,clk,clr,prs);
endmodule
module jkf1(q,qb,j,k,clk,clr,prs);
output reg q;
output qb;
assign qb = ~q;
begin
if(clr) begin
q <= 1'b0;
end
else if(prs) begin
q <= 1'b1;
end
else begin
case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 1'b0;
2'b10 : q <= 1'b1;
2'b11 : q <= ~q;
endcase
end
end
endmodule
Simulation result:
41
RTL View:
RESULT: Designed and Implemented T Flip Flop using JK Flip Flop using Xilinx ISE Tool.
42
EXPERIMENT-9
DESIGN OF COUNTERS
(a). AIM: Design, simulate and implement of Binary Counter using Synopsys Tools.
PROCEDURE:
a. Write the program code for Binary Counter.

option.
schematic” for the synthesis of the program code.
Verilog Reports:
Binary Counter
module
bi_c(c,clk,rst)
;
input clk,rst;
output reg
[3:0]c;
always
@(posedge
clk)
begin
if(rst)
c <= 0;
else
c <= c+1;
end
endmodule
43
Simulation result:
(b). AIM: Design, simulate and implement of BCD counter using Synopsys Tools.
BCD Counter
module
bcd(count,clk,rst
);
input clk,rst;
output reg
[3:0]count;
always
@(posedge clk)
begin
if(rst ||
count==9)
count = 4'b0000;
else
count = count +
1'b1;
end
endmodule
Simulation result:
Result: Designed and implemented Binary and BCD counter using ISE tool.
44
EXPERIMENT-10
DESIGN OF SHIFT REGISTERS
(a). AIM: Design, simulate and implement of Shift registers using Synopsys Tools.
PROCEDURE:
a. Write the program code for Shift Registers.

option.
Verilog Report:
Serial in Serial Out

module
siso(so,si,clk,rst);
input clk,rst,si;
output reg so;
reg [3:0]temp;
always
@(posedge clk)
begin
if(rst)
temp = 4'b0000;
else
begin
temp = temp >>
1;
temp[3] = si;
end
so = temp[0];
end
endmodule
45
Simulation result:
Serial in Parallel Out

module sipo(po,clk,rst,si);
input clk,rst,si;
output [3:0]po;
reg [3:0]temp;
always @(posedge clk)
begin
if(rst)
temp = 4'b0000;
else
begin
temp = temp >> 1;
temp[3] = si;
end
end
assign po = temp;
endmodule
Simulation result:
46
Parallel In Serial Out

module
piso(so,pi,clk,rst,load)
;
input clk,rst, load;
input [3:0]pi;
output so;
reg [3:0]temp;
always @(posedge
clk)
begin
if(rst)
temp = 4'b0000;
else if(load)
temp = pi;
else
begin
temp = temp >> 1;
end
end
assign so = temp[0];
endmodule
Simulation result:
47
Parallel In Parallel Out
module
pipo(po,clk,rst,pi);
input [3:0]pi;
input clk,rst;
output [3:0]po;
reg [3:0]temp;
always@(posedge
clk)
begin
if(rst)
temp<=4'b0000;
else
temp<=pi;
end
assign po=temp;
endmodule
Simulation result:
RESULT: Designed and Implemented Shift registers using Xilinx ISE Tool.
48
EXPERIMENT-11
DESIGN OF FSM
AIM: Design, simulate and implement of JK Flip Flop using Synopsys Tools.
PROCEDURE:
a. Write the program code for JK Flip Flop using Finite state machine.
b. Next execute this code in the ISE project navigator by first clicking the “Behavioral Check Syntax”
option.
c. After checking the syntax successfully, next go for the option “Simulate Behavioral Model” which
Schmatic” for the synthesis of the program code.
Verilog Reports:
JK Flip Flop using moore machine code:

Verilog Program:
module jkmoorefsm(q,qb,clk,rst,j,k);
input clk,rst,j,k; always @(Ps)
output reg q,qb; begin
reg [1:0]Ps,Ns; case(Ps)
parameter s0=2'b00,s1=2'b01; s0 : begin q=1'b0; qb=1'b1; end
s1 : begin q=1'b1; qb=1'b0; end
always @ (posedge clk) endcase
begin end
if(rst) endmodule
Ps=s0;
else
Ps=Ns;
end
always @(j,k,Ps)
begin
case(Ps)
s0 : if (j==1 && k==0 || j==1 && k==1)
Ns=s1;
else
Ns=s0;
s1 : if(j==1'b0 && k==1'b1 || j==1'b1 && k==1'b1)
Ns=s0;
else
49
Ns=s1;
endcase
end
Simulation result:
RESULT: Designed and Implemented JK Flip Flop using Xilinx ISE Tool.
50
CYCLE-II
EXPERIMENT-1
CMOS INVERTER
AIM: To design architecture of CMOS inverter circuit using schematic and find the power,delay and area of
CMOS inverter
SOFTWARE USED : 1.DSCH 3.5
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of CMOS inverter in DSCH 3.5 software.
 Convert the schematic diagram into a Verilog file from the option “Make the Verilog file” available in
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the CMOS inverter.
We also can know the Area and delay values of the circuit.
 Now by running the simulation we get the waveform and from that we can know the power value of the
CMOS inverter.
Reports:
Schematic Diagram
51
Layout
Waveform
52
Design Constraints of CMOS Inverter
Power Consumption 0.449 µW

Delay .010 ns
Area of Circuit 6.2 µm2
RESULT: Designed and Analysis of CMOS Inverter is completed with evaluation of Design
constraints using DSCH 3.5 and Microwind 3.5 software.
53
EXPERIMENT-2
CMOS NAND GATE
AIM: To design architecture of CMOS NAND gate circuit using schematic and find the power, delay and area of
CMOS NAND gate.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of CMOS NAND in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the CMOS NAND.
We also can know the area and delay values of the circuit.
CMOS NAND.
Reports:
Schematic diagram
54
Layout
Waveform
55
Design Constraints of CMOS Nand

Delay .0007 ns
RESULT: Designed and Analysis of CMOS Nand gate is completed with evaluation of Design
56
EXPERIMENT-3
CMOS NOR GATE
AIM: To design architecture of CMOS NOR gate circuit using schematic and find the power, delay and area of
CMOS NOR gate.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of CMOS NOR in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the CMOS NOR. We
also can know the area and delay values of the circuit.
CMOS NOR.
Reports:
Schematic Diagram
57
Layout
Waveform
58
Design Constraints of CMOS Nor

Delay .019 ns
RESULT: Designed and Analysis of CMOS NOR gate is completed with evaluation of Design
59
EXPERIMENT-4
CMOS XOR GATE
AIM: To design architecture of CMOS XOR gate circuit using schematic and find the power, delay and area of
CMOS XOR gate.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of CMOS XOR in DSCH 3.5 software.
 Convert the schematic diagram into a verilog file from the option “Make the verilog file” available in the
DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the CMOS XOR. We
CMOS XOR.
Reports:
Schematic diagram
60
Layout
Waveform
61
 Design constraints for CMOS XOR gate:

Power Consumption 4.021µW
Area of Circuit 48.0µm2
Delay 0.033ns
RESULT: Designed and Analysis of CMOS XOR gate is completed with evaluation of Design constraints
using DSCH 3.5 and Microwind 3.5 software.
62
EXPERIMENT-5
CMOS MUX
AIM: To design architecture of CMOS MUX circuit using schematic and find the power, delay and area of CMOS
MUX.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of CMOS MUX in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the CMOS MUX. We
CMOS MUX.
Reports:
Schematic Diagram
63
Layout
Waveform
64
 Design constraints for CMOS MUX:

Delay 0.031ns
RESULT: Designed and Analysis of CMOS MUX is completed with evaluation of Design constraints using
DSCH 3.5 and Microwind 3.5 software.
65
EXPERIMENT-6
SR FLIP FLOP
AIM: To design architecture of SR Flip Flop circuit using schematic and find the power, delay and area of SR Flip
Flop.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of SR Flip Flop in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the SR Flip Flop. We
SR Flip Flop.
Reports:
Schematic Diagram
66
Layout
Waveform
67
 Design constraints for SR Flip Flop:
Delay 0.024ns
RESULT: Designed and Analysis of SR Flip Flop is completed with evaluation of Design constraints using
DSCH 3.5 and Microwind 3.5 software.
68
EXPERIMENT-7
JK FLIP FLOP
AIM: To design architecture of JK Flip Flop circuit using schematic and find the power, delay and area of JK Flip
Flop.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of JK Flip Flop in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the JK Flip Flop. We
JK Flip Flop.
Reports:
Schematic Diagram
69
Layout
Waveform
70
 Design constraints for JK Flip Flop:

Power Consumption 1.108.µW
Delay 0.037ns
RESULT: Designed and Analysis of JK Flip Flop is completed with evaluation of Design
71
EXPERIMENT-8
D FLIP FLOP
AIM: To design architecture of D Flip Flop circuit using schematic and find the power, delay and area of D Flip
Flop.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of D Flip Flop in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the D Flip Flop. We
 Now by runnning the simulation we get the waveform and from that we can know the power value of the
D Flip Flop.
Reports:
Schematic Diagram
72
Layout
Waveform
73
 Design constraints for D Flip Flop:

Delay 0.024ns
RESULT: Designed and Analysis of D Flip Flop is completed with evaluation of Design
74
EXPERIMENT-9
T FLIP FLOP
AIM: To design architecture of T Flip Flop circuit using schematic and find the power, delay and area of T Flip
Flop.
2. Microwind 3.5
PROCEDURE:
 Design the Schematic diagram of T Flip Flop in DSCH 3.5 software.
the DSCH software.
 Now compile the Verilog file in Microwind 3.5 software then we get the Layout of the T Flip Flop. We
 Now by runnning the simulation we get the waveform and from that we can know the power value of the
T Flip Flop.
Reports:
Schematic Diagram
75
Layout
Waveform
76
 Design constraints for T Flip Flop:

Delay 0.036ns
RESULT: Designed and Analysis of T Flip Flop is completed with evaluation of Design
77

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Name: J Prashanth Roll No: 17071A0484

REALIZATION OF LOGIC GATES

2. SOFTWARE USED: Xilinx

3. SIMULATOR USED: iSim

4. SYNTHESIZER USED: XST

Behavioural modelling for all Logic Gates

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Behavioral modelling of 2 to 1 Mux

Data Flow Modelling of 2 to 1 MUX

Structural Modelling of 2 to 1 MUX

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

4 to 1 MUX using 2 to 1 MUX

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Behavioral Modelling Style

Dataflow Modelling Style

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Behavioral modelling of 2 to 4 Decoder

Dataflow modelling of 2 to 4 Decoder

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

a. Write the program code for 3 to 8 decoders using 2 to 4 decoder.

3 to 8 decoder using 2 to 4 decoder

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Behavioral modelling of Half Adder

Dataflow modelling of Half Adder

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Behavioral modelling of Full Adder

Dataflow modelling of Full Adder

Structural modelling of Full Adder

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

a. Write the program code for Gray to Binary code converter.

Gray to Binary Code Converter

SOFTWARE USED: Xilinx

SIMULATOR USED: iSim

SYNTHESIZER USED: XST

Dataflow modelling of 2-Bit Comparator

Behavioral modelling of 2-Bit Comparator

Implementation of RTL View: