VLSI ASSIGNMENT

Submitted by: J Prashanth (17071A0484), ECE-2

1.ALL LOGIC GATES:

All Logic gates using Behavioral Modelling:

All Logic gates using DataFlow Modelling:

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All Logic gates using Structural Modelling

All Logic gates Simulation results:

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2.FULL ADDER VERILOG CODES:

Full Adder using Behavioral Modelling:

Full Adder using Dataflow Modelling:

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Full Adder using Structural Modelling:

Full Adder simulation results:

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3.FULL SUBTRACTOR VERILOG CODES:

Full Subtractor using Behavioral Modelling:

Full Subtractor using Dataflow Modelling

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Full Subtractor using Structural Modelling:

Full Subtractor Simulation results:

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4. (8 to 3) Encoder Verilog Codes:

8 to 3 Encoder using Behavioral Modelling

8 to 3 Encoder using Dataflow Modelling

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8 to 3 Encoder using Structural Modelling

8 to 3 Encoder simulation results:

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5. (2 to 4) Decoder Verilog Codes:

2 to 4 Decoder using Behavioral Modelling

2 to 4 Decoder using Dataflow Modelling

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2 to 4 Decoder using Structural Modelling

2 to 4 Decoder simulation results:

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6. (8 to 1) Multiplexer Verilog Codes:

8 to 1 Mux using Behavioral Modelling

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8 to 1 Mux using Dataflow Modelling

8-1 Mux simulation results:

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7. (1 to 8) Demultiplexer Verilog Codes:

1 to 8 Demux using Behavioral Modelling

1 to 8 Demux using Dataflow Modelling

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1 - 8 Demux Simulation results:

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