Testbench for full adder in Verilog

For writing the testbench:

 We’ll first add the timescale directive. It starts with a grave accent ` and does
not end with a semicolon. Timescale directive is used for specifying the unit of
time used in further modules and the time resolution (here one picosecond).
The time resolution is the precision factor that determines the degree of
accuracy of the time unit in the modules.

timescale 1ns / 1ps

Next is the module and variable declaration.

 The register (reg) type holds the value until a next value is being driven by
the clock pulse onto it and is always under initial or always block. It is
used to apply a stimulus to the input.
Hence A_input B_input and C_input are declared as registers.
 Wires(wire) are declared for the variables which are passive in nature. Their
values don’t change, and they can’t be assigned
inside always and initial block. Hence sum Sum and
carry C_Output variables are declared as wires.

module top;

reg  A_input, B_input, C_input;

wire Sum, C_output;

Then comes the module instantiation.

 The test bench applies stimulus to the Device Under Test DUT. To do this,
the DUT must be instantiated under the testbench. The syntax for
instantiation is given below. Port mapping is the linking of testbench’s
modules with that of the design modules.

name_of_module name_of_instance(port_map)

 Now we’ll give an initial stimulus to the input variables. This is done under
the initial block.
 We can also stop the simulation in a pre-mentioned delay time
using $finish.
initial  

  begin

A_input=0;

  B_input=0;   

   C_input=0;    

#100 $finish;  

end

The additional thing over here is the use of two system tasks:

 $dumpfile is used to dump the changes in the values of net and registers in
a VCD file (value change dump file).
 $dumpvars is used to specify which variables should be dumped in the file
name specified by argument in the filename.

initial  

  begin

A_input=0;   

   B_input=0;   

   C_input=0;   

     #100 $finish;  

end

 Now, it depends on the user whether he wants to display the simulation result
on the TCL console or not. I have used $monitor which displays the value of
the signal whenever its value changes.
 It is executed inside always block, and the sensitivity list remains the same as
explained in the above section.
  The format specifier %t gives us the current simulation time and %d is used to
display the value of the variable in decimal.

always @(A_input or B_input or C_input)   

   $monitor("At TIME(in ns)=%t, A=%d B=%d C=%d Sum = %d Carry = %d", $time,
A_input, B_input, C_input, Sum, C_output);

Summing up the testbench code:

//timescale directive

`timescale 1ns / 1ps

module top;

//declare testbench variables

reg  A_input, B_input, C_input;

  wire Sum, C_output;  

//instantiate the design module and connect to the testbench variables

full_adder instantiation(.A(A_input), .B(B_input), .Cin(C_input), .S(Sum),

.Cout(C_output));

initial

   begin

     $dumpfile("xyz.vcd");
      $dumpvars;

     //set stimulus to test the code

     A_input=0;

     B_input=0;

     C_input=0;

      #100 $finish;

   end

//provide the toggling input (just like truth table input)

//this acts as the clock input

always #40 A_input=~A_input;

always #20 B_input=~B_input;

always #10 C_input=~C_input;

//display output if there’s a change in the input event

always @(A_input or B_input or C_input)

     $monitor("At TIME(in ns)=%t, A=%d B=%d C=%d Sum = %d Carry = %d", $time,
A_input, B_input, C_input, Sum, C_output);
endmodule