Datasheet

ESP-CV®
Custom Design Formal Equivalence Checking Based on Symbolic Simulation

Overview Verification Scope

ESP-CV is an equivalence checker for ESP-CV verifies that two different design representations are functionally equivalent.
full custom designs. It enables efficient These designs may be described as Verilog behavioral models, RTL, UDP’s, gates,
transistors, or SPICE netlist views (Figure 1).
comparison of a Verilog reference
design against other Verilog models
ESP Fills the Verification Gap
or a transistor-level SPICE netlist.
ESP-CV provides fast and extensive
if always
coverage, enabling users to quickly wait
Verilog
find bugs and have the confidence behavioral level description
Create Verilog model
that the Verilog reference design fork join
case
repeat

is functionally identical to other Behavioral Verilog

Verilog models or its transistor-level Equivalence

checking
implementation. ESP Verilog
Design spec Symbolic Symbolic
simulation ESP
ESP-CV improves overall verification simulation
SPICE
productivity by simplifying the Equivalence
checking
testing process. It directly verifies Custom circuit
the SPICE netlist, eliminating Implement circuit
the need to manually extract the SPICE
transistor level implementation
transistor network into a gate-level
representation.

Figure 1: Bridging the verification gap between Verilog and SPICE

Benefits
Higher Quality
ESP-CV provides fast and complete
coverage, enabling you to quickly find
bugs and have the confidence that the
reference model is functionally identical to
the transistor model.
Increased Productivity
With ESP-CV, you no longer have to
derive directed and random tests or have
a long delay in releasing models while you
complete your verification suite.
Easy to Use
ESP-CV directly verifies the SPICE netlist,
eliminating the need to manually extract
the transistor network into a gate-level
representation.
Memories are Changing
Over 50 percent of the total silicon real
estate in today’s SOC is consumed by
memories. And as designs move toward
sub-nanometer process technology,
functionalities such as redundancy, ECC,
BIST, pipelining, etc. are being added to
these designs, resulting in significantly
higher functional complexity.
With few standards and many degrees
of freedom, functional verification of
embedded memories has become
a critical need in the SOC design
verification process. A key requirement of
a successful design is that the behavioral
reference model used for SOC full chip
simulation is functionally identical to the
transistor-level netlist that represents the
actual implementation.
As the quantity and complexity of memory
designs continues to increase, and the
project schedules and available resources
continues to shrink, designers are faced
with the challenges of delivering high
quality memories on-time and with limited
resources.
High Coverage Verification
Traditional methods used to verify
memories such as SPICE simulation or
cell-based formal verification have their
limitations. SPICE simulation provides
circuit-level accuracy but its coverage is
dependent on the vector set created by
the engineers and the time available for
running the simulation. Likewise, cell-
based formal verification may provide
complete coverage but cannot accurately
represent the behavior of the transistor-
level netlist.
ESP-CV is based on a patented symbolic
simulation technology that combines the
power of formal methods with proven
event-driven simulation technology.
ESP-CV leverages symbolic simulation to
perform sequential equivalence checking,
dramatically increasing the quality of
functional verification (Figure 2).

((CS1*RS1)CS2)*RS2

.....CS2.....CS1 (((CS1*RS1) ((CS1*RS1)

CS2)*RS2) ((((CS1*RS1)
CS CS2)*RS2
CS2 CS2)*RS2)
REG
CS2)*RS2
Resulting
.....RS2.....RS1
RS equations
.....RS2.....RS1 ((CS1*RS1)CS2)*RS2 after two
clock cycles
CS1*RS1*CS2*RS2
CS1*RS1
RS2*((CS1* *CS2*RS2
(CS1*RS1 RS1*CS2)(((CS1
((CS1*RS1) *CS2) REG
*RS1)CS2)
CS2)*RS2 (((CS1*RS1) *RS2*CS2))
*CS2 CS2)*RS2*CS2)
CLK

Figure 2: Symbolic simulation propagation — ESP performs formal analysis on output equations to establish equivalence

ESP-CV® 2
ESP-CV simultaneously simulates two 0
different design representations using Z=0&0
0
symbolic inputs while observing the Symbolic simulation delivers high
s1 coverage functional verification
outputs of each representation to assure 0
· Event-driven (like traditional
equivalent responses. Instead of applying 1 Z=0&1
logic simulation)
all possible combinations of binary states, Z=s1&s2 · Uses symbols (variables) as
1
ESP-CV applies a symbol that represents inputs instead of just 1s and 0s
0 Z=1&0 s2 · Propagates equations instead of
all possible input states. This results in
discrete events
coverage of 2N possible states with only N 1 · Formal analysis, equivalence
number of symbols (Figure 3). 1 Z=1&1 checking using generated
equations
ESP-CV is capable of applying formal 4 vectors 1 vector
verification to the circuit-level designs,
delivering an easy-to-use verification
Figure 3: Using symbols as inputs delivers high coverage
solution that is circuit-aware.

Unlike other methods that require

Behavioral Behavioral
modeling of transistor-level designs
to cell-based gate equivalent netlists, RTL RTL
ESP-CV directly verifies the functional
equivalence of the SPICE-level netlist Gate Gate
against a behavioral or RTL representation
of the design. ESP-CV greatly simplifies Switch Switch
the inclusion of transistor parasitic effects
Transistor Transistor
in the functional model by automatically
calculating the RC value based on
transistor length, width, and process Figure 4: Direct verification of behavioral Verilog, RTL, gate and
technology (Figure 4). transistor-level design netlists

Differentiating Features
Incorrect isolation Missing level shifter
Power Integrity Verification
The Power Integrity Verification flow 0.7V 1.1V
detects common low-power design errors 1 Z
and power-down/sleep-mode failures.
When errors are found, this flow also 0 0.7V
generates SPICE vectors for analysis and
debug (Figure 5). 0 1

Power/ground shorts Unbuffered Inputs

0.7V 1.1V
0
0 0

1 Pad

Sneak paths

Figure 5: ESP power-integrity verification

ESP-CV® 3
Redundancy Verification Flow
ESP-CV uses formal techniques to quickly Verilog SPICE
verify that the redundancy logic added (w/wo redundancy) (with redundancy)

to the memory array to replace defective

cells and improve yields is performing
correctly (Figure 6). Redundancy
ESP
control signals
(with bit-cell
Verdi Interface defect
Expected defect injection)
Using the Verdi3 advanced debug platform tolerance (n bits)
environment already used by most RTL
designers, ESP-CV provides a graphical Pass Fail

way to debug mismatches in transistor-

For all possible n-bit defects, Location of bit-cell
level design using Interactive Signal some redundancy setting defects that can’t be
Tracing (IST). ESP-CV also provides preserves equivalence compensated for

resistance, capacitance and delay

information for events on schematic Figure 6: Redundancy verification flow
nets as well as traditional Verilog “1”,
“0”, “X” and “Z” logic values. Using
Verdi3 dramatically reduces the overall
verification debug time and improves
productivity by providing a common
debug platform for logic and circuit
designers alike (Figure 7).

Device Model Simulation

ESP-CV Device Model Simulation allows
you to perform ESP verification for new
device technologies, e.g. FinFET and
FDSOI, as soon as your SPICE circuit
simulator supports that technology.
It supports multiple circuit simulators
and transparently handles CMI and TMI
encrypted models (Figure 8).

Figure 7: Verdi3 interface provides graphical debug environment

ESP-CV
User-specified inputs Tcl script sets up and invokes circuit
· Device model library path simulations, collects and packages results
· Target device list
· Device length/width range Simulation ESP device model
· Operating voltage Runs for each SPICE deck
device name/size library
· Path to circuit simulator template (user owned)
Sizes substituted
· ESP Device Model (EDM) into template
output file name

SPICE SPICE Output files from

device model library simulator SPICE .MEAS
statements

ESP-CV
esp _ shell> set _ process –i –f <EDM>
esp _ shell> read _ verilog –r <DESIGN.v>
esp _ shell> read _ spice –i <DESIGN.sp>
esp _ shell> verify

Figure 8: Generating ESP device models from SPICE models

ESP-CV® 4
ESP-CV Additional Features Interactive Signal Tracing (IST) High Capacity

Full Verilog (RTL, Structural and
Behavioral) Language
The tool supports all constructs from the
Verilog language, including behavioral
structures, such as fork, join, and
task, etc.
Timing Dependent Functionality
It calculates transition time as a function
of symbolic states and transistor widths
and lengths, and therefore supports
timing dependent functionality.
Automated error validation
It spawns SPICE simulation to validate
verification differences and provides
generated waveforms for debugging.
Distributing Testbench Execution
The tool supports simulation of
testbenches in parallel using LSF and
Oracle GRID (SGE), and therefore
reducing time-to-results.
Integrated Test Suite Management
A designers’ productivity is improved
by automating multiple test bench
simulations and producing a merged
coverage report.
IST provides unique features to help It has the ability to verify over one billion
debug verification errors. By using a transistor designs on a single workstation.
simple command-based interface or
Verdi schematic display, a designer
can back trace incorrect or suspicious
Typical Applications
Compiled memories
``
values in the design. It also tracks internal
signal transitions and reports calculated Custom memories (i.e. CAM, SRAM,
``
transistor strengths. ROM, etc.)
Datapath blocks
``
Transistor Level Verification Programmable Logic (FPGA)
``
Transistors are natively supported by ESP- Problematic / Dynamic circuits
``
CV and it does not depend upon gate
Standard cell and I/O libraries
``
extraction or pattern matching techniques.
Asynchronous Timing Conclusion
It supports asynchronous clocks, pulsed With the increasing complexity and the
logic and self-timed logic. importance of memories in modern
ICs, there is a clear need for specialized
No State Point Mapping tools and techniques for the design and
It verifies functional equivalency of verification of embedded memory blocks.
designs with different structures, ESP-CV brings formal technology into the
without any dependency on isomorphic memory designer’s hands and raises their
state mapping. confidence in the quality of the design
while simplifying the testing process and
increasing overall verification productivity.

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08/15.rd.CS6332.