GATE NoteBook

Target JRF - UGC NET Computer Science Paper 2

1000 MEQs
50 Qs on DIGITAL LOGIC
Most Expected Questions Course
501. Consider the (decimal) number 182, whose binary representation is
10110110. How many positive integers are there in the following set?
{n∈N:n≤182 and n has exactly four ones in its binary representation}
a) 91
b) 70
c) 54
d) 35
e) 27
182 = 10110110  Total Bits = 8 (given)

Case 1 :
Starts with 0, then it must be less than 182
So, in the remaining 7 Bits, you need to choose 4 bits as 1 ==> (7P4) = 35

Case 2 :
Starts with 1, then next bit should be 0 for total decimal value ≤ 182.
So, in the remaining 6 Bits, you need to choose 3 bits as 1 ==> (6P3) = 20

Case3 :
But in this 20 patterns, 1011100010111000 is grater than given number.
So, only 19 patterns are matching with our condition.

Total = 35+19 = 54
501. Consider the (decimal) number 182, whose binary representation is
10110110. How many positive integers are there in the following set?
{n∈N:n≤182 and n has exactly four ones in its binary representation}
a) 91
b) 70
c) 54
d) 35
e) 27
502. In which of the following Base Systems, 127 is NOT a valid
Number ?

a) Base 10
b) Base 16
c) Base 8
d) Base 3
502. In which of the following Base Systems, 127 is NOT a valid
Number ?

a) Base 10
b) Base 16
c) Base 8
d) Base 3

Ternary is a numeral system with base 3.

Only uses 3 digits to make up its numbers :
0,1,2
503.What is the octal equivalent of the binary number (110111101)2 ?

a) 675
b) 275
c) 572
d) 573
503.What is the octal equivalent of the binary number (110111101)2 ?

a) 675
b) 275
c) 572
d) 573
504. Which statement(s) is/are TRUE ?

Consider the statement :

S1 : In Johnson counter, the outcome of the last flip flop is passed to the first
flip flop as an input.
S2 : In ring counter, the inverted outcome of the last flip flop is passed as an
input.

a) Only S1
b) Only S2
c) Both S1 and S2
d) None of these
504. Which statement(s) is/are TRUE ?

Consider the statement :

S1 : In Johnson counter, the outcome of the last flip flop is passed to the first
flip flop as an input.
S2 : In ring counter, the inverted outcome of the last flip flop is passed as an
input.

a) Only S1
b) Only S2
c) Both S1 and S2
d) None of these
505. Which of the following logic gates does not follow commutative law ?
1. XOR
2. XNOR
3. NOR
4. NAND

A) Only 1 and 2
B) Only 3 and 4
C) Only 1 and 3
D) Only 2 and 4
E) None of these
505. Which of the following logic gates does not follow commutative law ?
1. XOR
2. XNOR
3. NOR
4. NAND

A) Only 1 and 2
B) Only 3 and 4
C) Only 1 and 3
D) Only 2 and 4
E) None of these
506. Which of the following logic gates does not follow Associative law ?
1. XOR
2. XNOR
3. NOR
4. NAND

A) Only 1 and 2
B) Only 3 and 4
C) Only 1 and 3
D) Only 2 and 4
E) None of these
506. Which of the following logic gates does not follow Associative law ?
1. XOR
2. XNOR
3. NOR
4. NAND

A) Only 1 and 2
B) Only 3 and 4
C) Only 1 and 3
D) Only 2 and 4
E) None of these
507. Which of the following boolean expression does not follows
Consensus law ?
a) AB + BC' + AC = BC' + AC
b) (A + B).(A' + C).(B + C) = (A + B).(A' + C)
c) PQ’ + QR + RS = QR + RS
d) XY + YZ’ + XZ = YZ’ + XZ
507. Which of the following boolean expression does not follows
Consensus law ?
a) AB + BC' + AC = BC' + AC
b) (A + B).(A' + C).(B + C) = (A + B).(A' + C)
c) PQ’ + QR + RS = QR + RS
d) XY + YZ’ + XZ = YZ’ + XZ
509. A variable ANDed with 0 gives 0, while a variable ORed with 1 gives 1.
This law is called as _____________

a) Idempotent law
b) Annulment law
c) Absorption law
d) Double negation law
e) None of these
509. A variable ANDed with 0 gives 0, while a variable ORed with 1 gives 1.
This law is called as _____________ A.0 = 0
A+1=1
a) Idempotent law
b) Annulment law
c) Absorption law
d) Double negation law
e) None of these
510.
511.
512. Which of following consume minimum power ?
(A) TTL
(B) CMOS
(C) DTL
(D) RTL
512. Which of following consume minimum power ?
(A) TTL
(B) CMOS
(C) DTL
(D) RTL

CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS
transistors are connected in complimentary mode, such that one device
is ON & one is OFF.
 Difference Between CMOS and TTL

1. TTL circuits utilize BJTs while CMOS circuits utilize FETs.

2. CMOS allows a much higher density of logic functions in a single chip compared
to TTL.
3. TTL circuits consumes more power compared to CMOS circuits at rest.
4. CMOS chips are a lot more susceptible to static discharge compared to TTL chips.
5. There are CMOS chips that have TTL logic and are meant as replacements for TTL
chips.
513. How many address bits are required to represent 4K
memory ?
(A) 5 bits.
(B) 12 bits.
(C) 8 bits.
(D) 10 bits.
513. How many address bits are required to represent 4K
memory ?
(A) 5 bits.
(B) 12 bits.
(C) 8 bits.
(D) 10 bits.
514. How many select lines will a 32:1 multiplexer will have
(A) 5
(B) 8
(C) 9
(D) 11
514. How many select lines will a 32:1 multiplexer will have
(A) 5
(B) 8
(C) 9
(D) 11

For 32 inputs, 5 select lines will be required, as 25 = 32.

515. How many two input AND gates and two input OR gates
are required to realize
Y = BD+CE+AB

(A) 1, 1
(B) 4, 2
(C) 3, 2
(D) 2, 3
515. How many two input AND gates and two input OR gates
are required to realize
Y = BD+CE+AB

(A) 1, 1
(B) 4, 2
(C) 3, 2
(D) 2, 3

There are three product terms, so three AND gates of two inputs are required.
As only two input OR gates are available, so two OR gates are required to get the
logical sum of three product terms.
516. Which of following can not be accessed randomly
(A) DRAM.
(B) SRAM.
(C) ROM.
(D) Magnetic tape.
516. Which of following can not be accessed randomly
(A) DRAM.
(B) SRAM.
(C) ROM.
(D) Magnetic tape.

Magnetic tape can only be accessed sequentially

SRAM
SRAM has lower access time, which is faster
compared to DRAM.
costlier than DRAM.
consumes more power.
SRAM offers low packaging density.
Uses transistors and latches.
The storage capacity of SRAM is 1MB to 16MB.
SRAM is in the form of on-chip memory.
The SRAM is widely used on the processor or
lodged between the main memory and processor
of your computer.
SRAM is of a smaller size.
These are used in cache memories.
DRAM
DRAM has a higher access time. It is slower than
SRAM.
DRAM cost is lesser
DRAM requires reduced power consumption as the
information stored in the capacitor.
DRAM offers a high packaging density.
Uses capacitors and very few transistors.
The storage capacity of DRAM is 1 GB to 16GB.
DRAM has the characteristics of off-chip memory.
The DRAM is placed on the motherboard.
DRAM is available in larger storage capacity.
These are used in main memories.
517. Which of following requires refreshing?
(A) SRAM.
(B) DRAM.
(C) ROM.
(D) EPROM.
517. Which of following requires refreshing?
(A) SRAM.
(B) DRAM.
(C) ROM.
(D) EPROM.
518. The prime implicant which has at least one element
that is not present in any other implicant is known as
___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
518. The prime implicant which has at least one element
that is not present in any other implicant is known as
___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
519. Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
519. Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate

AND gate is known as coincidence detector due to multiplicity behaviour, as

it outputs 1 only when all the inputs are 1.
520. The AND function can be used to ___________ and the OR function can be used
to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
520. The AND function can be used to ___________ and the OR function can be used
to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert

The AND gate and OR gate are used for enabling and disabling respectively because of
their multiplicity and additivity property. The AND gate outputs 1 when all inputs are
at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.
521. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
521. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS

AS-TTL (Advanced Schottky) has a maximum clock frequency of 105 MHz. S-TTL
(Schottky High Speed TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S
separate TTL. HCMOS has 50 MHz clock frequency.
522. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS
522. Which of the following logic families has the shortest propagation delay?
a) S-TTL
 HCMOS = high-density CMOS.
b) AS-TTL  used to describe microprocessors, and other complex
integrated circuits.
c) HS-TTL  use a smaller manufacturing processes, producing more
transistors per area.
d) HCMOS
 Example = Freescale 68HC11

AS-TTL (Advanced Schottky) has a maximum clock frequency that is 105 MHz. So, the
propagation delay will be given by 1/105 sec which is the lowest one. It is followed by
S-TTL and HCMOS in terms of increasing propagation delay.
523. An eight stage ripple counter uses a flip-flop with propagation delay
of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the
input signal which can be used for proper operation of the counter is
approximately
(A) 1 MHz.
(B) 500 MHz.
(C) 2 MHz.
(D) 4 MHz.
523. An eight stage ripple counter uses a flip-flop with propagation delay
of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the
input signal which can be used for proper operation of the counter is
approximately
(A) 1 MHz.
(B) 500 MHz.
(C) 2 MHz.
(D) 4 MHz.

Maximum time taken for all

flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must
be less than 1/650ns = 1.5 MHz.
524. The number of full and half adders are required to add 16-bit number is
__________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
524. The number of full and half adders are required to add 16-bit number is __________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders

Half adder has two inputs and two outputs whereas Full Adder has 3 inputs and 2 outputs.
One half adder can add the least significant bit of the two numbers whereas full adders
are required to add the remaining 15 bits as they all involve adding carries.
525. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
525. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line

4 to 16 line decoder as the minterms are ranging from 1 to 14.

526. Calculate the max terms of the given expression
f(A,B,C,D) = ABCD + BC’ + ABD’ + A

A. (4,5,8,9,10,11,12,13,14,15)
B. (0,1,2,3,6,7)
C. (0,1,2,3,6,9)
D. (0,1,2,3,6,7,8,9,10,11)
526. Calculate the max terms of the given expression
f(A,B,C,D) = ABCD + BC’ + ABD’ + A

A. (4,5,8,9,10,11,12,13,14,15)
B. (0,1,2,3,6,7)
C. (0,1,2,3,6,9)
D. (0,1,2,3,6,7,8,9,10,11)

Min terms for f(A,B,C,D) are 4,5,8,9,10,11,12,13,14,15

Max terms are 0,1,2,3,6,7
527. In the 4-bit CLA circuit, No. of OR gates and AND gates are
A. 6, 10
B. 6, 12
C. 4, 10
D. 4, 12
527. In the 4-bit CLA circuit, No. of OR gates and AND gates are
A. 6, 10
B. 6, 12
C. 4, 10
D. 4, 12

No. of OR gates in n-bit CLA circuit = n

So no. of OR gates = 4
No. of AND gates in n-bit CLA circuit = n(n+1)/2
So, no. of AND gates = 10
528. Which of the following is not the example combinational circuit
A. Carry look ahead adder
B. Parallel binary adder
C. Full adder
D. Serial binary adder
528. Which of the following is not the example combinational circuit
A. Carry look ahead adder
B. Parallel binary adder
C. Full adder
D. Serial binary adder

Serial binary adder is example of sequential circuit

And all the remaining are examples of combinational circuit
529. Which of the following statement is not true about binary number representations?
a) 1s complement, 2s complement and sign magnitude have same representation of
positive numbers
b) 1s complement has 2 representations of zero
c) 2s complement has larger range of numbers than 1s complement and sign magnitude
for same number of bits in number
d) 2s complement has 2 representations of zero
529. Which of the following statement is not true about binary number representations?
a) 1s complement, 2s complement and sign magnitude have same representation of
positive numbers
b) 1s complement has 2 representations of zero
c) 2s complement has larger range of numbers than 1s complement and sign magnitude
for same number of bits in number
d) 2s complement has 2 representations of zero

Only option D is not true (false statement)

2s complement representation has only 1 representation of zero and because of that it
has one more number to be represented as compared to other two representation,
which leads it to have a larger range of numbers.
530. The two numbers represented in signed 2s complement form are P = 11101101
and Q = 11100110 . If Q is subtracted from P , the value is
A.1000001111
B.00000111
C.11111001
D.111111001
530. The two numbers represented in signed 2s complement form are P = 11101101
and Q = 11100110 . If Q is subtracted from P , the value is
A.1000001111
B.00000111
C.11111001
D.111111001

P=-19
Q=-26
P-Q=-19+26=7 (00000111)
531. Consider a boolean operator $ defined as A$B= A’B’. Let F(a,b,c)= Σ(0,1,3,7) and
G(a,b,c)= Σ(1,2, 5,7). Then F $ G= .
a) Σ(4,6)
b) Σ(0,2,3,4,5,6,7)
c) Σ(0,2)
d) Σ(2,4)
531. Consider a boolean operator $ defined as A$B= A’B’. Let F(a,b,c)= Σ(0,1,3,7) and
G(a,b,c)= Σ(1,2, 5,7). Then F $ G= .
a) Σ(4,6)
b) Σ(0,2,3,4,5,6,7)
c) Σ(0,2)
d) Σ(2,4)

F(a,b,c)= Σ(0,1,3,7).
F’(a,b,c)= Σ(2,4,5,6).
G(a,b,c)= Σ(1,2,5,7).
G’(a,b,c)= Σ(0,3,4,6)

F $ G = F’G’
= Σ(2,4,5,6) . Σ(0,3,4,6)
The minterms 4 and 6 are common terms. Therefore, F $ G= Σ(4,6)
532.
532.
533.
533.
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536.
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537.
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538.
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539.
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540.
540.
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542.
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543.
543.
544.
544.
545.
545.
546.
546.
547.
547.
548.
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550.
 GATE NoteBook
Target JRF - UGC NET Computer Science Paper 2

1000 MEQs
50 Qs on Computer System
Architecture
Most Expected Questions Course
551. The main objective of using a multiprocessor is to boost the system’s
execution speed, with other objectives being fault tolerance and application
matching.
Multiprocessor is a system :

a) that operates with multiple CPUs

b) that is a cluster of computers that operate as a singular computer.
c) Where program tends to be easier and easy to construct.
d) that supports distributed computing.
551. The main objective of using a multiprocessor is to boost the system’s
execution speed, with other objectives being fault tolerance and application
matching.
Multiprocessor is a system :

a) that operates with multiple CPUs

b) that is a cluster of computers that operate as a singular computer.
c) Where program tends to be easier and easy to construct.
d) that supports distributed computing.
552. Multiprocessor supports _________ computing and Multicomputer supports
____________ computing.

a) parallel, single
b) distributed, parallel
c) parallel, parallel
d) parallel, distributed
e) distributed, distributed
552. Multiprocessor supports _________ computing and Multicomputer supports
____________ computing.

a) parallel, single
b) distributed, parallel
c) parallel, parallel
d) parallel, distributed
e) distributed, distributed
553. As the multicomputer is capable of messages passing between the processors,
a) it is possible to divide the task between the processors to complete the task.
b) it is possible to merge the tasks of multiple processors to complete the task.
c) it is possible to share the tasks between the processors to complete the task.
d) All of the above
e) None of the above
553. As the multicomputer is capable of messages passing between the processors,
a) it is possible to divide the task between the processors to complete the task.
b) it is possible to merge the tasks of multiple processors to complete the task.
c) it is possible to share the tasks between the processors to complete the task.
d) All of the above
e) None of the above
554. Quantum computing is a phenomenon where it is possible :

a) in a single state at a given time, either on or off.

b) to be in more than one state at a time.
c) Either a) or b)
d) None of these
554. Quantum computing is a phenomenon where it is possible :

a) in a single state at a given time, either on or off. (Conventional Computing)

b) to be in more than one state at a time.
c) Either a) or b)
d) None of these
555. CMOS transistors are the basic building blocks of
a) conventional computers
b) quantum computers
c) Both a) and b)
d) None of these
555. CMOS transistors are the basic building blocks of
a) conventional computers
b) quantum computers
c) Both a) and b)
d) None of these

Superconducting Quantum Interference Device or SQUID or Quantum

Transistors are the basic building blocks of quantum computers.
556. Parallel computing is a computing where :
I. the jobs are broken into discrete parts that can be executed concurrently.
II. Each part of job broken down to a series of instructions.
III. Instructions from each part execute simultaneously on different CPUs.

a) I & II
b) II & III
c) I & III
d) All of them
e) None of these
556. Parallel computing is a computing where :
I. the jobs are broken into discrete parts that can be executed concurrently.
II. Each part of job broken down to a series of instructions.
III. Instructions from each part execute simultaneously on different CPUs.

a) I & II
b) II & III
c) I & III
d) All of them
e) None of these
557. MATCH THE FOLLOWING :
SET 1 SET 2
I. SISD 1. Very efficient for instruction of large amount of data
II. SIMD 2. low power requirement and simpler architecture
III. MISD 3. Great for perform a variety of processor & data intensive tasks
IV. MIMD 4. Excellent for situation where fault tolerance is critical
a) I-2, II-1, III-4, IV-3
b) I-1, II-2, III-3, IV-4
c) I-4, II-3, III-2, IV-1
d) I-1, II-4, III-2, IV-3
557. MATCH THE FOLLOWING :
SET 1 SET 2
I. SISD 1. Very efficient for instruction of large amount of data
II. SIMD 2. low power requirement and simpler architecture
III. MISD 3. Great for perform a variety of processor & data intensive tasks
IV. MIMD 4. Excellent for situation where fault tolerance is critical
a) I-2, II-1, III-4, IV-3
b) I-1, II-2, III-3, IV-4
c) I-4, II-3, III-2, IV-1
d) I-1, II-4, III-2, IV-3
558. The unit responsible for tracking the next instruction to be executed in
I. Instruction memory
II. Memory address register
III. Program counter

a) I & II
b) II & III
c) I & III
d) Only III
e) Only II
558. The unit responsible for tracking the next instruction to be executed in
I. Instruction memory
II. Memory address register
III. Program counter

a) I & II
b) II & III
c) I & III
d) Only III
e) Only II
Program Counter (PC)
 Keep the track of execution of the program.
 It contains the memory address of the next instruction to be fetched.
 Points to the address of the next instruction to be fetched from the main memory
when the previous instruction has been successfully completed.
 Counts the number of instructions.
 Its incrementation depends on the type of architecture being used.
 If we are using 32-bit architecture, it gets incremented by 4 every time to fetch the
next instruction.
559. The disadvantage of write back strategy in cache is that ___________

a) It generates repeated memory traffic.

b) It creates a write mechanism wherever there is a write operation to cache.
c) Portions of main memory may be invalid.
d) It requires local cache memory attached to every CPU in a multi processor
environment.
559. The disadvantage of write back strategy in cache is that ___________
a) It generates repeated memory traffic.
b) It creates a write mechanism wherever there is a write operation to cache.
c) Portions of main memory may be invalid.
d) It requires local cache memory attached to every CPU in a multi processor
environment.

Write Back is also known as Write Deferred.

Disadvantage:
There is data availability risk because the cache could fail and so suffer from data
loss before the data is persisted to the backing store.
This result in the data being lost.
560. In Write Through strategy in cache where :
1) It is a process of writing cache and main memory simultaneously.
2) Main memory and cache memory may have different data.
3) Number of memory write operation in a typical program is more.
4) Main memory is updated with every memory write operation as well as cache
memory is updated in parallel if it contains the word at the specified address.
a) 1 and 3 only
b) 1, 3 and 4
c) 2, 3 and 4
d) All of them
560. In Write Through strategy in cache where :
1) It is a process of writing cache and main memory simultaneously.
2) Main memory and cache memory may have different data. (Write Back)
3) Number of memory write operation in a typical program is more.
4) Main memory is updated with every memory write operation as well as cache
memory is updated in parallel if it contains the word at the specified address.
a) 1 and 3 only
b) 1, 3 and 4
c) 2, 3 and 4
d) All of them
Write Through Method Write Back Method
main memory is updated with every memory write
operation as well as cache memory is updated in only cache location is updated during write
parallel if it contains the word at the specified operation.
address.

Main memory and cache memory may have

Main memory always contains same data as cache.
different data.

Number of memory write operation in a typical Number of memory write operation in a typical
program is more. program is less

When I/O device communicated through DMA When I/O device communicated through DMA
would receive most recent data. would not receive most recent data.

writing cache and data is removed from cache,

writing cache and main memory simultaneously.
first copied to main memory.
561. Whenever a Processor wants to write a word, it checks to see if the address
it wants to write the data to, is present in the cache or not.
If address is present in the cache said to be ________

a) Write Through
b) Write Back
c) Write Hit
d) Write Around
561. Whenever a Processor wants to write a word, it checks to see if the address
it wants to write the data to, is present in the cache or not.
If address is present in the cache said to be ________

a) Write Through
b) Write Back
c) Write Hit
d) Write Around
562. If write occurs to a location that is not present in the Cache can say Write
Miss, we use :

I. Write Through
II. Write Back
III. Write Allocation
IV. Write Around

a) I & II
b) III & IV
c) Only II
d) Only III
e) All of them
562. If write occurs to a location that is not present in the Cache can say Write
Miss, we use :

I. Write Through
II. Write Back
III. Write Allocation
IV. Write Around

a) I & II
b) III & IV
c) Only II
d) Only III
e) All of them
563. Each Block in the cache needs a Dirty bit to indicate :
a) If the data present in the cache was modified
b) If the data present in the cache was not modified
c) Either a) or b)
d) Neither a) nor b)
563. Each Block in the cache needs a Dirty bit to indicate :
a) If the data present in the cache was modified (DIRTY)
b) If the data present in the cache was not modified (CLEAN)
c) Either a) or b)
d) Neither a) nor b)

DIRTY BIT
 If it is clean there is no need to write it into the memory.
 It designed to reduce write operation to a memory.
 Speed:
•SDRAM has higher operation speed make it popular.
SDRAM •SDRAM access time is 6 to 12 nanoseconds (ns)
Clock:
Synchronous Dynamic
SDRAM uses one edge of the clock.
Random Access Memory Data transfer:
SDRAM sends signals once per clock cycle.
It synchronizes itself with
the computer’s system Advantages
clock. •It is faster as compared to the other versions of RAM.
•It is more efficient, which is up to 4 times the
This makes it easy to performance of the other standard DRAMs.
•Has name suggest, it gets synchronized with the system
manage faster, and the
clock.
speed of the SDRAM
measured in MHz instead of Disadvantages
nanoseconds. It can’t use with the older motherboards.
It works in a single data rate, i.e., it can do only tasks per
clock cycle.
565. Which one of the following is NOT a consumable resources ?
a) Interrupts
b) Signals
c) I/O devices
d) Messages
565. Which one of the following is NOT a consumable resources ?
a) Interrupts
b) Signals
c) I/O devices
d) Messages
Consumable resources : resources that can be used only once.
Examples :
a) Interrupts
b) I/O devices
c) Messages
d) I/O buffer
566. Using a larger block size in a fixed block size file system leads to :
(A) better disk throughput but poorer disk space utilization
(B) better disk throughput and better disk space utilization
(C) poorer disk throughput but better disk space utilization
(D) poorer disk throughput and poorer disk space utilization
566. Using a larger block size in a fixed block size file system leads to :
(A) better disk throughput but poorer disk space utilization
(B) better disk throughput and better disk space utilization
(C) poorer disk throughput but better disk space utilization
(D) poorer disk throughput and poorer disk space utilization

 Using larger block size makes disk utilization poorer as more space would be wasted for small data
in a block.
 It may make throughput better as the number of blocks would decrease.
 A larger block size guarantees that more data from a single file can be written or read at a time
into a single block without having to move the disk ́s head to another spot on the disk.
567. A processor needs software interrupt to

(A) test the interrupt system of the processor

(B) implement co-routines
(C) obtain system services which need execution of privileged instructions
(D) return from subroutine

1. A, B & D
2. Only C
3. Only A
4. Only C & D
5. All of them
567. A processor needs software interrupt to

(A) test the interrupt system of the processor

(B) implement co-routines
(C) obtain system services which need execution of privileged instructions
(D) return from subroutine

1. A, B & D
2. Only C
3. Only A
4. Only C & D
5. All of them
A software interrupt
 Caused either by an exceptional condition in the processor itself, or a special
instruction in the instruction set which causes an interrupt when it is executed.

 The former is often called a trap or exception and is used for errors or events
occurring during program execution that are exceptional enough that they
cannot be handled within the program itself.

 An interrupt alerts the processor to a high-priority condition requiring the

interruption of the current code the processor is executing.

 The processor responds by suspending its current activities, saving its state, and
executing a function called an interrupt handler to deal with the event. This
interruption is temporary, and, after the interrupt handler finishes, the
processor resumes normal activities.
568. When will DMA most probably be used ?
a) The performance of the system to be increased
b) Several CPU’s in a multiprocessing system share the same memory
c) The CPU must control a variety of the devices
d) All of the above
e) None of the above
568. When will DMA most probably be used ?
a) The performance of the system to be increased
b) Several CPU’s in a multiprocessing system share the same memory
c) The CPU must control a variety of the devices
d) All of the above
e) None of the above
569. Which statement(s) is/are NOT CORRECT about Direct Access Media
(DMA) ?
a) Allows I/O devices to directly access memory with less participation of
the processor.
b) It needs the new circuits of an interface to communicate with the CPU and
I/O devices.
c) The unit communicates with the CPU through data bus and control lines.
d) All of the above
e) None of the above
569. Which statement(s) is/are NOT CORRECT about Direct Access Media
(DMA) ?
a) Allows I/O devices to directly access memory with less participation of
the processor.
b) It needs the new circuits of an interface to communicate with the CPU and
I/O devices.
c) The unit communicates with the CPU through data bus and control lines.
d) All of the above
DMA controller needs the same old circuits of an
e) None of the above interface to communicate with the CPU and
Input/Output devices.
570. MATCH THE FOLLOWING :
SET 1 (DMA registers) SET 2
I. Address register 1. contains the no of words to be transferred
II. Word count register 2. contains address to specify the desired location in m/m.
III. Control register 3. specifies the transfer mode.

a) I-2, II-1, III-3

b) I-1, II-2, III-3
c) I-3, II-2, III-1
d) I-1, II-3, III-2
570. MATCH THE FOLLOWING :
SET 1 (DMA registers) SET 2
I. Address register 1. contains the no of words to be transferred
II. Word count register 2. contains address to specify the desired location in m/m.
III. Control register 3. specifies the transfer mode.

a) I-2, II-1, III-3

b) I-1, II-2, III-3
c) I-3, II-2, III-1
d) I-1, II-3, III-2
571. _______ in the DMA appear to the CPU as I/O interface
registers.
a) Address register
b) Word count register
c) Control register
d) All of the above
e) None of the above
571. _______ in the DMA appear to the CPU as I/O interface
registers.
a) Address register
b) Word count register
c) Control register
d) All of the above
All registers in the DMA appear to the CPU as I/O
e) None of the above interface registers.
Therefore, the CPU can both read and write into the
DMA registers under program control via the data bus.
572. The CPU initializes the DMA by
1. The starting address of the memory block where the data is available to
read or where data are to be stored to write.
2. sending word count which is the number of words in the memory block to
be read or write.
3. Control to define the mode of transfer such as read or write.
4. Automatically begins the DMA transfer.
a) 1, 2 and 3 b) 1, 2 and 4 c) only 2 and 4
d) Only 1 and 3 e) all of the above
572. The CPU initializes the DMA by
1. The starting address of the memory block where the data is available to read or
where data are to be stored to write.
2. sending word count which is the number of words in the memory block to be read
or write.
3. Control to define the mode of transfer such as read or write.
4. Automatically begins the DMA transfer.
a) 1, 2 and 3 b) 1, 2 and 4 c) only 2 and 4
d) Only 1 and 3 e) all of the above

A control to begin the DMA transfer.

The CPU initializes the DMA by sending the given information through the data bus .
573. In a 8085 microprocessor system with memory mapped I/O.
a) I/O devices have 8 bit addresses
b) I/O devices are accessed using IN and OUT Instructions
c) There can be maximum of 256 input devices and $$2564$ output devices
d) Arithmetic and logic operations can be directly performed with
the I/O data
573. In a 8085 microprocessor system with memory mapped I/O.
a) I/O devices have 8 bit addresses
b) I/O devices are accessed using IN and OUT Instructions
c) There can be maximum of 256 input devices and $$2564$ output devices
d) Arithmetic and logic operations can be directly performed with
the I/O data
Microprocessor:-
A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device that reads
binary instructions from a storage device called memory, accepts binary data as input and processes data
according to those instructions and provide results as output.

Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable of performing ALU
operations and communicating with the other devices connected to it.

Arithmetic and logic unit:-

An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and logic
operations on the operands in computer instruction words.
574. The main difference between RISC and CISC processor is/are
that a RISC processor typically has

a) Has fewer instructions and addressing modes

b) Has more registers
c) Easy to implement using hardwired control logic
d) All of the above
574. The main difference between RISC and CISC processor is/are
that a RISC processor typically has

a) Has fewer instructions and addressing modes

b) Has more registers
c) Easy to implement using hardwired control logic
d) All of the above
575. The program written for RISC architecture needs to take
________ space in memory and It has ______ format instruction.

a) More, fixed
b) Less, fixed
c) More, variable
d) Less, variable
575. The program written for RISC architecture needs to take
________ space in memory and It has ______ format instruction.

a) More, fixed
b) Less, fixed
c) More, variable
Program written for CISC architecture tends to
d) Less, variable take less space in memory.
It has variable format instruction.
576. Which of the following is/are the disadvantage of RISC Processors ?
a) it uses only 20% of existing instructions in a programming event.
b) require more transistors as compared to RISC design.
c) The performance of the machine decreases due to the slowness of the
clock speed.
d) Programmers and compilers often use complex instructions.
576. Which of the following is/are the disadvantage of RISC Processors ?
a) it uses only 20% of existing instructions in a programming event.
b) require more transistors as compared to RISC design.
c) The performance of the machine decreases due to the slowness of the
clock speed.
d) Programmers and compilers often use complex instructions.

a), b) and c) are the disadvantages of CISC.

577. CISC creates a process to manage power usage
that adjusts ______
a) clock speed
b) Voltage
c) Both a) and b)
d) None of these
577. CISC creates a process to manage power usage
that adjusts ______
a) clock speed
b) Voltage
c) Both a) and b)
d) None of these
578.
578.
579.
579.
580.
580.
581.
581.
582. Consider 64 KB 8-way set associative cache with 256-byte block size. Physical
address is 32 bits. What is the number of comparators and size of each comparator
required for tag matching, respectively?

a). (8, 19) b). (8, 18) c). (19, 8) d). (20, 8)
582. Consider 64 KB 8-way set associative cache with 256-byte block size. Physical
address is 32 bits. What is the number of comparators and size of each comparator
required for tag matching, respectively?

a). (8, 19) b). (8, 18) c). (19, 8) d). (20, 8)

Size of the cache: 64 KB

8-way set associative cache Physical address: 32 bits
Size of the block: 256 bytes, so OFFSET needs 8 bits

No of blocks = 64 KB / 256 Bytes = 256

No of sets = 256 / 8 = 32 sets, SET number needs 5 bits

Since the total physical address is 32 bits long, no of tag bits are 19.
Tag(19) Set no(5) Block offset(8)
For K-way set associative cache, number of comparators required = K
∴ For 8-way set associative cache number of comparators = 8 Size of each comparator = number of tag bits
∴ 19 bit comparator
583.
583.
583.
584.
584.
584.

(64)
64 – 1 = 63
585.
585.

B
586.
586.
587.
587.
588.
588.
589.
589.
589.
590.
590.
591.
591.
592.

“97”
592.

1100001

“97”
593.
593.
594. Consider a direct mapped cache of size 256Kbytes, used in a
system with word addressable main memory (1 word = 2 bytes)
system. The size of main memory is 4GB. If the block size is 32
bytes then the size of tag is _____ bits?
(A)15
(B)16
(C)17
(D)18
594.Consider a direct mapped cache of size 256Kbytes, used in a system with word
addressable main memory (1 word = 2 bytes) system. The size of main memory is 4GB.
If the block size is 32 bytes then the size of tag is _____ bits?
(A) 15
(B) 16
(A)15
The main memory address is divided into following 3 parts in direct mapped
(C) 17 cache :
(D) 18 Tag Cache Block number Byte Offset

Given main memory size = 4GB = 4G/2words = 231 words, hence main
memory address = 31 bits
Block size = 32 bytes = 32/2 = 16 words, hence Word offset size = 4-bits

Number of blocks in cache = cache size / block size = 256KB/32B =4K = 212
Hence the block number = 12 bits

Tag bits = 31 – (12+4) = 16 bits

595. Which of the following is true regarding data transfer from IO devices?
(A) Interrupt mode is used to transfer data from IO to memory directly
without using CPU
(B) Programmed IO mode is used to transfer data from IO to memory directly
without using CPU
(C) DMA mode is used to transfer data from IO to memory directly without
using CPU
(D) All of the above
595. Which of the following is true regarding data transfer from IO devices?
(A) Interrupt mode is used to transfer data from IO to memory directly without using
CPU
(B) Programmed IO mode is used to transfer data from IO to memory directly without
using CPU
(C) DMA mode is used to transfer data from IO to memory directly without using CPU
(D) All of the above

DMA (Direct memory access) mode of IO transfer is used for data transfer between IO
and memory directly without CPUs intervention.
596. Consider a system which supports 2 address instruction only . The system has 2m K
bytes of memory . If there are ‘x’ distinct instructions supported by the system then the
size of the instruction is ?
Assume memory is byte addressable .

A.(x+m)bits
B.(x+2m)bits
C.(logx+2m)bits
D. (logx+2m+20)bits
596. Consider a system which supports 2 address instruction only . The system has 2m K
bytes of memory . If there are ‘x’ distinct instructions supported by the system then the
size of the instruction is ?
Assume memory is byte addressable .

A.(x+m)bits
B.(x+2m)bits
C.(logx+2m)bits
D. (logx+2m+20)bits In 2 address instruction we have 2 addresses part.
For x instruction we need log2 x bits and
And for address we need 2m K= 2m+10
Log 2 ( 2m+10 )bits =m+10 for 1 address
2*(m+10)+log x for whole instruction = logx+2m+20
597. The width of the physical address on a machine is 42 bits.The width of the
tag field in 1024KB 16 way set associative cache is _____ bits .
A. 26
B. 27
C. 25
D. 24
597. The width of the physical address on a machine is 42 bits.The width of the
tag field in 1024KB 16 way set associative cache is _____ bits .
A. 26
B. 27
C. 25
D. 24

TAG entry size = (physical address width - cache size width ) + log (set associative)
Tag entry size= 42-20+4=26 bits
598. Consider a 2-level memory hierarchy with a cache. The memory
hierarchy takes 12ns for a read operation when it hits on the cache and takes
200ns for a read operation when it misses on cache. Average memory access
time with cache hit ratio of 85% is?

(A) 12ns

(B) 40.2ns

(C) 42ns

(D)72ns
598. Consider a 2-level memory hierarchy with a cache. The memory
hierarchy takes 12ns for a read operation when it hits on the cache and takes
200ns for a read operation when it misses on cache. Average memory access
time with cache hit ratio of 85% is?

(A) 12ns

(B) 40.2ns

(C) 42ns
Average memory access time = 0.85 *12ns + 0.15 * 200ns
(D)72ns = 10.2 + 30
= 40.2ns
599. Consider a magnetic disk with 16 platters (each platter has 2 recording
surfaces), 1k tracks per surface, 4k sectors per track and 2Kbytes sector
capacity. The disk rotates with 6000 rpm. What is the disk transfer rate?
(A) 400Kbytes/sec
(B) 800Kbytes/sec
(C) 400Mbytes/sec
(D) 800Mbytes/sec
599. Consider a magnetic disk with 16 platters (each platter has 2 recording
surfaces), 1k tracks per surface, 4k sectors per track and 2Kbytes sector
capacity. The disk rotates with 6000 rpm. What is the disk transfer rate?
(A) 400Kbytes/sec
(B) 800Kbytes/sec
(C) 400Mbytes/sec
(D) 800Mbytes/sec For 6000 rotations disk takes time = 60 sec = 60000 milli sec
For 1 rotation disk takes time = 60000/6000 = 10milli sec
1 track capacity = 4k sectors * 2Kbytes = 8Mbytes
In one rotation one track can be transferred, hence
In 10 milli sec Disk can transfer data = 8M bytes
In 1 milli sec disk can transfer data = 8Mbytes / 10 = 0.8Kbytes per milli second
In 1 second disk can transfer data = 0.8Mbytes / 10 -3 = 800Mbytes / second
600. The size of the physical address space of a processor is 2^P bytes. The
word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size
of each cache block is 2^M words. For a direct mapped cache memory, the
length (in number of bits) of the tag field is
a) P–M
b) P – W
c) N - W – M
d) P - N
600. The size of the physical address space of a processor is 2^P bytes. The
word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size
of each cache block is 2^M words. For a direct mapped cache memory, the
length (in number of bits) of the tag field is
a) P–M
b) P – W Physical memory is of size 2^P byte
c) N - W – M Each word is of size 2^W bytes.
d) P - N
Number of words in physical memory = 2^(P-W) So the physical address is P-W bits
Cache size is 2^N bytes.
Number of words in the cache = 2^(N-W)
Block size is 2^M words, so block offset = M bits
No. of blocks in the cache = 2^(N-W-M), so block number = (N-W-M) bits

In the case of a direct mapped cache the physical address is divided into three fields
(TAG bits + Block number + Block Offset)
So we can calculate TAG bits = Physical address - Block number - Block offset
= (P-W) - (N-W-M) - M
=P-W-N+W+M-M=P-N
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