Computer System Architecture

Unit 1 Index

S. No. Topic Page No.

1 Functional Unit Pg 2

2 Basic Operational Concepts Pg 4

3 Instruction Format Pg 6

4 Instruction Cycle Pg 11

5 Addressing Mode Pg 18

6 Subroutines Pg 24

7 Types of Buses Pg 29

8 Common Bus Architecture Pg 34

Hardwired Vs Microprogrammed
9 Pg 36
Control Unit

10 Microinstruction Format Pg 38

SSIPMT Raipur | Computer Architecture Notes 1

CHAPTER – 1
BASIC STRUCTURE OF COMPUTERS
Computer types: -
A computer can be defined as a fast electronic calculating machine that accepts the
(data) digitized input information process it as per the list of internally stored
instructions and produces the resulting information.

List of instructions are called programs & internal storage is called computer
memory.

The different types of computers are

1. Personal computers: - This is the most common type found in homes, schools,
Business offices etc., It is the most common type of desk top computers with
processing and storage units along with various input and output devices.

2. Note book computers: - These are compact and portable versions of PC

3. Work stations: - These have high resolution input/output (I/O) graphics

capability, but with same dimensions as that of desktop computer. These are used in
engineering applications of interactive design work.

4. Enterprise systems: - These are used for business data processing in medium
to large corporations that require much more computing power and storage capacity
than work stations. Internet associated with servers have become a dominant
worldwide source of all types of information.
5. Super computers: - These are used for large scale numerical calculations
required in the applications like weather forecasting etc.,

Functional unit: -
A computer consists of five functionally independent main parts input, memory,
arithmetic logic unit (ALU), output and control unit.

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Input device accepts the coded information as source program i.e. high level
language. This is either stored in the memory or immediately used by the processor
to perform the desired operations. The program stored in the memory determines
the processing steps. Basically the computer converts one source program to an
object program. i.e. into machine language.

Finally the results are sent to the outside world through output device. All of these
actions are coordinated by the control unit.

Input unit: -

The source program/high level language program/coded information/simply data is

fed to a computer through input devices keyboard is a most common type.
Whenever a key is pressed, one corresponding word or number is translated into its
equivalent binary code over a cable & fed either to memory or processor.

Joysticks, trackballs, mouse, scanners etc are other input devices.

Memory unit: -

Its function into store programs and data. It is basically to two types

1. Primary memory

2. Secondary memory

1. Primary memory: - Is the one exclusively associated with the processor and
operates at the electronics speeds programs must be stored in this memory while
they are being executed. The memory contains a large number of semiconductors
storage cells. Each capable of storing one bit of information. These are processed in
a group of fixed site called word.

To provide easy access to a word in memory, a distinct address is associated with

each word location. Addresses are numbers that identify memory location.

Number of bits in each word is called word length of the computer. Programs must
reside in the memory during execution. Instructions and data can be written into the
memory or read out under the control of processor.

Memory in which any location can be reached in a short and fixed amount of time
after specifying its address is called random-access memory (RAM).

The time required to access one word in called memory access time. Memory which
is only readable by the user and contents of which can‟t be altered is called read

only memory (ROM) it contains operating system.

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Caches are the small fast RAM units, which are coupled with the processor and are
aften contained on the same IC chip to achieve high performance. Although primary
storage is essential it tends to be expensive.

2. Secondary memory: - Is used where large amounts of data & programs have to
be stored, particularly information that is accessed infrequently.

Examples: - Magnetic disks & tapes, optical disks (ie CD-ROM‟s), floppies etc.,

Arithmetic logic unit (ALU):-

Most of the computer operators are executed in ALU of the processor like addition,
subtraction, division, multiplication, etc. the operands are brought into the ALU from
memory and stored in high speed storage elements called register. Then according
to the instructions the operation is performed in the required sequence.

The control and the ALU are may times faster than other devices connected to a
computer system. This enables a single processor to control a number of external
devices such as key boards, displays, magnetic and optical disks, sensors and other
mechanical controllers.

Output unit:-

These actually are the counterparts of input unit. Its basic function is to send the
processed results to the outside world.

Examples:- Printer, speakers, monitor etc.

Control unit:-

It effectively is the nerve center that sends signals to other units and senses their states. The actual
timing signals that govern the transfer of data between input unit, processor, memory and output
unit are generated by the control unit.

Basic Operational Concepts

o The primary function of a computer system is to execute a program,
sequence of instructions. These instructions are stored in computer memory.

o These instructions are executed to process data which are already loaded in
the computer memory through some input devices.

o After processing the data, the result is either stored in the memory for further
reference, or it is sent to the outside world through some output port.

o To perform the execution of an instruction, in addition to the arithmetic logic

unit, and control unit, the processor contains a number of registers used for
temporary storage of data and some special function registers.

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o The special function registers include program counters (PC), instruction
registers (IR), memory address registers (MAR) and memory and memory
data registers (MDR).

o The Program counter is one of the most critical registers in CPU.

o The Program counter monitors the execution of instructions. It keeps track on

which instruction is being executed and what the next instruction will be.

o The instruction register IR is used to hold the instruction that is currently

being executed.

o The contents of IR are available to the control unit, which generate the timing
signals that control, the various processing elements involved in executing
the instruction.

o The two registers MAR and MDR are used to handle the data transfer between
the main memory and the processor.

o The MAR holds the address of the main memory to or from which data is to
be transferred.

o The MDR contains the data to be written into or read from the addressed
word of the main memory.

o Whenever the processor is asked to communicate with devices, we say that

the processor is servicing the devices. The processor can service these
devices in one of the two ways.

o One way is to use the polling routine, and the other way is to use an
interrupt.

o Polling enables the processor software to check each of the input and output
devices frequently. During this check, the processor tests to see if any
devices need servicing or not.

o Interrupt method provides an external asynchronous input that informs the

processor that it should complete whatever instruction that is currently being
executed and fetch a new routine that will service the requesting device.

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Instruction Format
Computer perform task on the basis of instruction provided. An instruction in
computer comprises of groups called fields. This field contains different information
as for computers everything is in 0 and 1 so each field has different significance on
the basis of which a CPU decide what to perform. The most common fields are:

 Operation field which specifies the operation to be performed like addition.

 Address field which contain the location of operand, i.e., register or memory
location.

 Mode field which specifies how operand is to be founded.

An instruction is of various lengths depending upon the number of addresses it

contains. Generally CPU organizations are of three types on the basis of number of
address fields:

1. Single Accumulator organization

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2. General register organization

3. Stack organization

In first organization operation is done involving a special register called accumulator.

In second on multiple registers are used for the computation purpose. In third
organization the work on stack basis operation due to which it does not contain any
address field. It is not necessary that only a single organization is applied a blend of
various organizations is mostly what we see generally.

On the basis of number of address, instructions are classified as:

Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions–

A stack based computer do not use address field in instruction. To evaluate a

expression first it is converted to revere Polish Notation i.e. Post fix Notation.

Expression: X = (A+B)*(C+D)

Post fixed: X = AB+CD+*

TOP means top of stack

M[X] is any memory location

PUSH A TOP = A

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PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2. One Address Instructions –

This use a implied ACCUMULATOR register for data manipulation. One

operand is in accumulator and other is in register or memory location. Implied
means that the CPU already knows that one operand is in accumulator so
there is no need to specify it.

Expression: X = (A+B)*(C+D)

AC is accumulator

M[] is any memory location

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 M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

3. Two Address Instructions –

This is common in commercial computers. Here two address can be specified in

the instruction. Unlike earlier in one address instruction the result was stored in
accumulator here result can be stored at different location rather than just
accumulator, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)

R1, R2 are registers

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 M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

4. Three Address Instructions –

This has three address field to specify a register or a memory location. Program
created are much short in size but number of bits per instruction increase. These
instructions make creation of program much easier but it does not mean that
program will run much faster because now instruction only contain more
information but each micro operation (changing content of register, loading
address in address bus etc.) will be performed in one cycle only.

Expression: X = (A+B)*(C+D)

R1, R2 are registers

M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

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 ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Instruction Cycles
Registers Involved In Each Instruction Cycle:

 Memory address registers(MAR) : It is connected to the address lines of the

system bus. It specifies the address in memory for a read or write operation.

 Memory Buffer Register(MBR) : It is connected to the data lines of the

system bus. It contains the value to be stored in memory or the last value read
from the memory.

 Program Counter(PC) : Holds the address of the next instruction to be fetched.

 Instruction Register(IR) : Holds the last instruction fetched.

The Instruction Cycle –

Each phase of Instruction Cycle can be decomposed into a sequence of elementary

micro-operations. In the above examples, there is one sequence each for the Fetch,
Indirect, Execute and Interrupt Cycles.

The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is
always followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle
depends on the state of the system.

We assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC
designates the state of processor in terms of which portion of the cycle it is in:-

SSIPMT Raipur | Computer Architecture Notes 11

00 : Fetch Cycle
01 : Indirect Cycle
10 : Execute Cycle
11 : Interrupt Cycle

At the end of the each cycles, the ICC is set appropriately.The above flowchart
of Instruction Cycle describes the complete sequence of micro-operations, depending
only on the instruction sequence and the interrupt pattern(this is a simplified
example). The operation of the processor is described as the performance of a
sequence of micro-operation.

Different Instruction Cycles:

1. The Fetch Cycle –

At the beginning of the fetch cycle, the address of the next instruction to be
executed is in the Program Counter(PC).

Step 1: The address in the program counter is moved to the memory address
register(MAR), as this is the only register which is connected to address lines of
the system bus.

Step 2: The address in MAR is placed on the address bus, now the control unit
issues a READ command on the control bus, and the result appears on the data
bus and is then copied into the memory buffer register(MBR). Program counter is

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incremented by one, to get ready for the next instruction.(These two action can
be performed simultaneously to save time)

Step 3: The content of the MBR is moved to the instruction register(IR).

Thus, a simple Fetch Cycle consist of three steps and four micro-operation.
Symbolically, we can write these sequence of events as follows:-

Here „I‟ is the instruction length. The notations (t1, t2, t3) represents successive
time units. We assume that a clock is available for timing purposes and it emits
regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all time
units are of equal duration. Each micro-operation can be performed within the
time of a single time unit.

First time unit: Move the contents of the PC to MAR.

Second time unit: Move contents of memory location specified by MAR to MBR.

Increment content of PC by I.

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 Third time unit: Move contents of MBR to IR.

Note: Second and third micro-operations both take place during the second time
unit.

2. The Indirect Cycles –

Once an instruction is fetched, the next step is to fetch source operands. Source
Operand is being fetched by indirect addressing( it can be fetched by
any addressing mode, here its done by indirect addressing). Register-based
operands need not be fetched. Once the opcode is executed, a similar process
may be needed to store the result in main memory. Following micro-
operations takes place:-

Step 1: The address field of the instruction is transferred to the MAR. This is used
to fetch the address of the operand.

Step 2: The address field of the IR is updated from the MBR.(So that it now
contains a direct addressing rather than indirect addressing)

Step 3: The IR is now in the state, as if indirect addressing has not been
occurred.

Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment
to consider the Interrupt Cycle .

3. The Execute Cycle

The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable.
Each of them requires simple, small and fixed sequence of micro-operation. In
each case same micro-operation are repeated each time around.
Execute Cycle is different from them. Like, for a machine with N different
opcodes there are N different sequence of micro-operations that can occur.
Lets take an hypothetical example :-

SSIPMT Raipur | Computer Architecture Notes 14

 consider an add instruction:

Here, this instruction adds the content of location X to register R. Corresponding

micro-operation will be:-

We begin with the IR containing the ADD instruction.

Step 1: The address portion of IR is loaded into the MAR.
Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read.

Step 3: Now, the contents of R and MBR are added by the ALU.

4. The Interrupt Cycle:

At the completion of the Execute Cycle, a test is made to determine whether any
enabled interrupt has occurred or not. If an enabled interrupt has occurred then
Interrupt Cycle occurs. The natare of this cycle varies greatly from one machine
to another. Lets take a sequence of micro-operation:-

SSIPMT Raipur | Computer Architecture Notes 15

Step 1: Contents of the PC is transferred to the MBR, so that they can be saved
for return.

Step 2: MAR is loaded with the address at which the contents of the PC are to be
saved.
PC is loaded with the address of the start of the interrupt-processing routine.

Step 3: MBR, containing the old value of PC, is stored in memory.

Note: In step 2, two actions are implemented as one micro-operation. However,

most processor provide multiple types of interrupts, it may take one or more
micro-operation to obtain the save_address and the routine_address before they
are transferred to the MAR and PC respectively.

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SSIPMT Raipur | Computer Architecture Notes 17
Addressing Modes
The term addressing modes refers to the way in which the operand of an
instruction is specified. The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand is actually
executed.
Addressing modes for 8086 instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory, allowing
you to easily access variables, arrays, records, pointers, and other complex data
types. The key to good assembly language programming is the proper use of
memory addressing modes.

An assembly language program instruction consists of two parts

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SSIPMT Raipur | Computer Architecture Notes 23
Subroutines

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SSIPMT Raipur | Computer Architecture Notes 28
Types of Buses
(Youtube link: https://www.youtube.com/watch?v=7QffiMyMpnM&t=175s)

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Register Transfer – Mux based Bus System
A typical computer has many registers and we need to transfer the information
between these registers. A way to transfer the information is using the common
bus system. In this article we shall discuss the common bus system
using multiplexers.

The construction of this bus system for 4 registers is shown above. The bus
consists of 4×1 multiplexers with 4 inputs and 1 output and 4 registers with bits

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numbered 0 to 3. There are 2 select inputs S0 and S1 which are connected to the
select inputs of the multiplexers.
The output 1 of register A is connected to input 0 of MUX 1 and similarly other
connections are made as shown in the diagram. The data transferred to the bus
depends upon the select lines. A table for the various combinations of select lines
is shown below.

As we can see that when S1S0=00, register A is selected because on 00 the 0 data
inputs of all the multiplexers are applied to the common bus.
Since the 0 data inputs of all the multiplexers receive the inputs from the register
A, thus register A gets selected. Similarly for other combinations of S1S0 other
register are selected.
Note-
No. of multiplexers needed = No. of bits in each register

Common Bus Architecture

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Hardwired v/s Micro-programmed Control Unit
To execute an instruction, the control unit of the CPU must generate the required
control signal in the proper sequence. There are two approaches used for generating
the control signals in proper sequence as Hardwired Control unit and Micro-
programmed control unit.
Hardwired Control Unit –

The control hardware can be viewed as a state machine that changes from one state
to another in every clock cycle, depending on the contents of the instruction
register, the condition codes and the external inputs. The outputs of the state
machine are the control signals. The sequence of the operation carried out by this
machine is determined by the wiring of the logic elements and hence named as
“hardwired”.
 Fixed logic circuits that correspond directly to the Boolean expressions are used
to generate the control signals.
 Hardwired control is faster than micro-programmed control.
 A controller that uses this approach can operate at high speed.
 RISC architecture is based on hardwired control unit

Micro-programmed Control Unit –

 The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
 Control signals are generated by a program are similar to machine language
programs.
SSIPMT Raipur | Computer Architecture Notes 36
 Micro-programmed control unit is slower in speed because of the time it takes to
fetch microinstructions from the control memory.

Some Important Terms –

1. Control Word: A control word is a word whose individual bits represent various
control signals.
2. Micro-routine: A sequence of control words corresponding to the control
sequence of a machine instruction constitutes the micro-routine for that
instruction.
3. Micro-instruction: Individual control words in this micro-routine are referred to
as microinstructions.
4. Micro-program: A sequence of micro-instructions is called a micro-program,
which is stored in a ROM or RAM called a Control Memory (CM).
5. Control Store: the micro-routines for all instructions in the instruction set of a
computer are stored in a special memory called the Control Store.

Types of Micro-programmed Control Unit – Based on the type of Control Word

stored in the Control Memory (CM), it is classified into two types:

1. Horizontal Micro-programmed control Unit:

The control signals are represented in the decoded binary format that is 1 bit/CS.
Example: If 53 Control signals are present in the processor than 53 bits are
required. More than 1 control signal can be enabled at a time.
 It supports longer control word.
 It is used in parallel processing applications.
 It allows higher degree of parallelism. If degree is n, n CS are enabled at a time.
 It requires no additional hardware(decoders). It means it is faster than Vertical
Microprogrammed.
 It is more flexible than vertical microprogrammed

SSIPMT Raipur | Computer Architecture Notes 37

2. Vertical Micro-programmed control Unit:

The control signals re represented in the encoded binary format. For N control
signals- Log2(N) bits are required.
 It supports shorter control words.
 It supports easy implementation of new conrol signals therefore it is more
flexible.
 It allows low degree of parallelism i.e., degree of parallelism is either 0 or 1.
 Requires an additional hardware (decoders) to generate control signals, it implies
it is slower than horizontal micro programmed.
 It is less flexible than horizontal but more flexible than that of hardwired control
unit.

Microinstruction Format
The microinstruction format for the control memory is shown in below figure. The 20
bits of the microinstruction are divided into four functional parts as follows:

1. The three fields F1, F2, and F3 specify micro operations for the computer. The
micro operations are subdivided into three fields of three bits each. The three bits in
each field are encoded to specify seven distinct micro operations. This gives a total
of 21 micro operations.

2. The CD field selects status bit conditions.

3. The BR field specifies the type of branch to be used.

4. The AD field contains a branch address. The address field is seven bits wide, since
the control memory has 128 = 27 words.

3 bits 3 bits 3 bits 2 bits 2 bits 7 bits

F1 F2 F3 CD BR AD

Microinstruction Format: F1, F2, F3: Micro operation field

CD: Condition for branching
BR: Branch Field
AD: Address Field

As an example, a microinstruction can specify two simultaneous micro operations

from F2 and F3 and none from F1.

DR = M[AR] with F2 = 100

PC = PC + 1 with F3 = 101

The nine bits of the micro operation fields will then be 000 100 101.

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The CD (condition) field consists of two bits which are encoded to specify four status
bit conditions as listed in below Table.

CD Condition Symbol Comments

00 Always = 1 U Unconditional Branch
01 DR (15) I Indirect Address Bit
10 AC (15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

The BR (branch) field consists of two bits.

It is used, in conjunction with the address field AD, to choose the address of the
next microinstruction shown in below Table.

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