ESD Full

EEEZG512
Embedded Systems
Design Dept. of Electrical & Devesh Samaiya
BITS Pilani Electronics Engg
Pilani Campus Pilani Campus
BITS Pilani
Pilani Campus
EEE ZG512
Contact Session – I
Purpose of Contact Session
BITS Pilani, Pilani Campus

Pre Contact Hour Content

Overview of RL1.1
● Introduction & Definition of Embedded Systems.
● A system within a system.
● Difference between general purpose computing systems

and embedded computing systems.
● Characteristics of an Embedded System.
● Performance Evaluation.

Embedded System!
EMBEDDED = Placed Inside
Embedded Computing System !
A small computing system embedded inside a bigger electro-mechanical system, doing a specific
job, often with real time constraints.

Think of computer as a component or a machine part !
Just like a motor, bearing or gear….

Hard Real Time !!!!

Computing?

How do we embed?
We need a much smaller version of this!

Tiny Computers!
8- bit Microcontrollers
Intel 8051, Microchip PIC, Atmel AVR, STM8 etc.
16-bit Microcontrollers
MSP430 by Texas Instruments
32-bit Microcontrollers
AVR32, PIC32, ARM7, ARM Cortex M0, M4, M0+ etc.
System on Chip devices along with FPGA fabric interface
They comes in variety of packages and peripheral options...

Overview of RL1.2
● Development Cycle of an Embedded system.

● Hardware / Software Design.
● Small Scale Embedded Systems
○ COTS
○ Battery Operated
○ Board Level Design
○ ASM / C
● Medium Scale Embedded Systems
○ Computationally intensive
○ may involve peripheral library or OS abstraction to hardware
○ C or higher languages
○ Might require distributed computing
● Sophisticated Mission Critical Systems
○ Satisfy real time constraints
○ Safety critical systems
●
USER INPUTS
Requirement
Analysis
Requirement Definitions
Specifications
Functional Specifications
System
Hardware Design Hardware Architecture Architecture Software Architecture
Software Design
Hardware Software
Implementation Implementation
Hardware Testing Software Testing
System Integration
System Validation
Operation & Maintenance

Multidisciplinary Aspects

Firmware!
1. We usually do not write application software.
2. We write firmware and sometimes middleware.
3. We write it in C / ASM.
WHY?
● C Data structures resembles to those used in

Controllers and Processors.
● Efficient compiler, simple construct.
● Efficient Bit manipulation.
● Most widely supported higher level language.

Overview of RL1.2.1
● CPUs in embedded systems.

● RISC and CISC
● Pipeline in RISC and Pipeline Hazards
● Microprocessor and Microcontroller
Which one is more popular in embedded systems

design, why?

Overview of RL1.2.2
● Requirements for a GPP to qualify as an embedded

systems CPU.
○ Low Interrupt latency in the CPU architecture.
○ Support for Atomic Operations.
● DSP Processors.
○ Microprocessot + MAC unit
● Application Specific Processors / System on Chip
○ Security needs
○ Multimedia processing requirements (Cemara I/F, Video Codec)
○ Communication protocol requirements
● How to choose a suitable processor / SoC for your
application?

Cost Range of Embedded
Computing Devices?
Data Source - ST Microelectronics
Data Source - mouser.in

Overview of RL 1.2.3
● Memory types in Embedded Systems

● CPU registers
● Cache Memory (tav with and without multilevel cache)
● Volatile / Nonvolatile memories
● RAM/ ROM/ Hybrid
● FRAM - for fast access non volatile storage
● Flash
● SD Card
● Dynamic Memory Allocation

○ Programs larger than memory
○ Multiple programs in memory
○ Swapping

Overview of RL 1.2.4
● Hit and Miss

● Cache Organization
○ Direct Mapping
○ Set Associative

Design Thinking
Assignment
To Design a discharge capacity tester for Li-ion cells.

● Li-ion cells works in voltage range of 3.5 to 4.2 volts.
● A fully charged cell will be at around 4.2V and a

completely discharged cell would be at around 3.5.
● Depending on the chemistry of the cell, discharge

current can vary. Example, 3500mAH at 10A max
discharge rate.

Design Thinking
Assignment
● To test the discharge capacity of the cells, a constant,

known amount of current must be drawn continuously
from the cell. How to do that?
● At the same time monitor the voltage levels of the cell.
How to do that?
● Keep checking if the current is maintaining the levels or
not.
● Once the voltage drops to a threshold (say 3.5V)
withdraw the load from battery and measure the total
time of the process from fully charged cell to a fully
discharged cell.

Calculation of result?
Suppose you were drawing a current of 1A form the cell

and it took total time of 2 hours to fully discharge this cell.
What is the discharge capacity of cell under test?

Hardware Components!
● Display to show the set discharge current and show the

final result
● Human interface mechanism to set the discharge
current and cut off voltage.
● Microcontroller to drive the dummy electronic load, drive
display, take user inputs and measure current, voltage,
time and final result.
● Electronic Load
● Alarm to indicate end of testing.

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
Contact Session – 2
Pre Contact Hour Content

Design Thinking Assignment
HW1 Discussion
To Design a discharge capacity tester for Li-ion cells.

● Li-ion cells works in voltage range of 3.5 to 4.2 volts.
● A fully charged cell will be at around 4.2V and a

completely discharged cell would be at around 3.5.
● Depending on the chemistry of the cell, discharge

current can vary. Example, 3500mAH at 10A max
discharge rate.

Design Thinking
Assignment
● To test the discharge capacity of the cells, a constant,

known amount of current must be drawn continuously
from the cell. How to do that?
● At the same time monitor the voltage levels of the cell.
How to do that?
● Keep checking if the current is maintaining the levels or
not.
● Once the voltage drops to a threshold (say 3.5V)
withdraw the load from battery and measure the total
time of the process from fully charged cell to a fully
discharged cell.

● Display to show the set discharge current and show the

final result
Most suitable would be a 4 digit seven segment display.
Small in size, easy to drive, visible from distance.
Scanning type Driving by MCU
Inbuilt Driver

● Human interface mechanism to set the discharge current

and cut off voltage.
Tactile switches are best suited for this application.
Cheap, Small, Easy to use. GPIO driven.
Minimum 3 switch required.
1. To increment the current / cutoff voltage
2. To decrement the current / cutoff voltage
3. To select the setting mode to current or cut off

● Dummy Load Design

We need to increment or decrement the discharge current
in steps of 100mA on press of a button. Max value can be
say 5A and minimum would be 100mA. Our dummy load
must satisfy the criteria.

Source - http://www.arachnidlabs.com/blog/2013/02/05/introducing-re-load/

● Microcontroller to drive the dummy electronic load, drive

display, take user inputs and measure current, voltage, time
and final result.
We need a controller which must have -
1. ADC at least 2 channels
2. At least 12 GPIO
3. PWM support
4. Low cost
5. 1x 8/16 Bit Timer preferably with prescaler
6. Cost and availability of development resources
(Software IDE, Library, Human Programmer) to
reduce time to market.
7. Device Package (DIP/ SMD type)
MCU choice!!!
● STM8S003F3P6
● N76E003AT20
● ATmega8A-PU
● and many more…

Overview of RL1.2.5
● Power, Clock and Reset.
● Power
○ Voltage ranges in ES.
○ Power Saving Schemes. (Frequency, Idle and Sleep Modes)
● Clock Source
○ Crystal
○ Ceramic Resonators
○ External IC clock generator
● Reset
○ Power on Reset (H/W), External Reset
○ Invalid instructions
○ Clock Monitor
○ Watchdog Timer

Overview of RL1.2.6
Interrupt Handling, Timers, ADC, DAC, Communication

Interfaces
● Timer
○ Input Capture.
○ Output Compare
○ PWM
● Interrupt Handlers
○ Hardware External Interrupts
○ Internal event driven interrupts
○ Priority
○ Latency
● ADC
● DAC
● Serial and Parallel Communication Interfaces in ES.

Overview of RL1.3.1
Software Components of Embedded Systems

● Operating Systems
○ RTOS
○ Normal OS
● Compiler / Assembler / Linker
● Device Driver
● Scheduling Schemes in RTOS.

user programs
libraries
User Level
Kernel Level
system call interface
file subsystem ipc

process
control
sub scheduler
Buffer cache
system
memory
management
character block
device driver
Kernel Level hardware control
Hardware Level
actual hardware
Block Diagram of the System Kernel

Source: The design of the unix operating system by Maurice J. Bach, figure 2.1
Overview of RL1.3.2
● Challenges in ESD
● Application Specific System on Chip
○ Network Connectivity
○ Encryption Requirements
○ Bluetooth / NFC requirements
○

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
ARM Architecture

What makes a good processor?
• Fast!
• Support for high level language
• Support for Operating System
• Support for system development
• Efficient use of memory resources
• Legacy Support
• Low/ Efficient power consumption

What Processors Do!!!
If we wish to design a faster processor, we must first find out what
they spend their time on?
Instruction Type Dynamic Usage
Data movement 43%
Control flow 23%
Arithmetic operations 15%
Comparisons 13%
Logical operations 5%
Other 1%
Source - Section 1.5.3 ARM System on Chip Architecture by Steve Furber

Processor Design Trade-offs
• Prior to 1980, major focus was on increasing the instruction and
in turn hardware complexity in an attempt to reduce the
semantic gap that compiler has to bridge.
• Memories were much slower than processor.
• This approach lead to CISC.
• All the improvement was in terms of increasing the number of
transistors to incorporate more complex instructions in the
processor.
• Semiconductor industry was leading the development, no
serious attempts were made to increase the capabilities using
architectural aspects.

PIPELINES
Steps in executions of an instruction
1. Fetch in instruction from memory (fetch)
2. Decode it to see what kind of instruction it is (dec)
3. Access any operands required from register bank (reg)
4. Combine the operands to form the result or a memory address
(ALU)
5. Access memory for a data operand, if necessary (mem)
6. Write the result back to the register bank (res)

PIPELINES
An Ideal pipeline situation

READ AFTER WRITE SITUATION

Pipelined Branch Instruction
Behaviour

RISC
• Fixed instruction size with few formats.
• Load store architecture
• Large general purpose register bank
• Single Cycle execution
• Hard wired Instruction decode logic (no microcodes)
• Pipelined execution
Homework - Read paper “The Case for the

Reduced Instruction Set Computer” by
Patterson and Ditzel

Architecture
The ARM architecture has been designed to allow very small, yet
high-performance implementations.
The architectural simplicity of ARM processors leads to very small

implementations, and small implementations allow devices with
very low power consumption.

The ARM is a Reduced Instruction Set Computer (RISC), as it
incorporates these typical RISC architecture features:
➔ large uniform register file

➔ load/store architecture, where data-processing operations only
operate on register contents, not directly on memory contents
➔ simple addressing modes, with all load/store addresses being
determined from register contents and instruction fields only
➔ uniform and fixed-length instruction fields, to simplify
instruction decode.

ARM Instruction Set
➔ 3-address data processing instructions. (2 source operands
registers and result register are all independently specified)
➔ Conditional execution of every instruction
➔ Powerful Load and Store Multiple registers instructions.

ARM Instruction Set Features
➔ Ability to perform a general shift operation and a general ALU
operation in a single instruction that executes in a single clock
cycle.
➔ Open instruction set extension through coprocessor
➔ Dense 16-bit compressed representation of instruction set in the
Thumb architecture.

I/O system
➔ ARM handles I/O peripherals as memory mapped devices with

interrupt support.
➔ Internal registers in these devices appear as addressable
locations within ARM’s memory map and may be read and
written using same load store instructions.
➔ Peripheral can raise interrupt request to CPU via IRQ or FIQ
lines. Both IRQ and FIQ are level sensitive and maskable.
➔ Most peripheral shares IRQ line with only one or two very time
critical peripherals will be allowed to interrupt over FIQ.

3 Stage Pipeline Implementation in ARM
Source - Section 4.1 “ARM System on Chip Architecture” by Steve Furber

ARM7TDMI Core
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0210c/DDI0210B.pdf
Datapath Activities during Data Processing Instructions

ARM Registers
ARM has 31 general-purpose 32-bit registers. At any one time, 16
of these registers are visible. The other registers are used to speed
up exception processing.
All the register specifiers in ARM instructions can address any of

the 16 visible registers.

R14 : Link Register
Register 14 is the Link Register (LR). This register holds the

address of the next instruction after a Branch and Link (BL)
instruction, which is the instruction used to make a subroutine call.
At all other times, R14 can be used as a general-purpose register.

R15 : Program Counter
Register 15 is the Program Counter (PC). It can be used in most

instructions as a pointer to the instruction which is two instructions
after the instruction being executed.
All ARM instructions are four bytes long (one 32-bit word) and are
always aligned on a word boundary. This means that the bottom two
bits of the PC are always zero, and therefore the PC contains only
30 non-constant bits.
The remaining 14 registers have no special hardware purpose. Their

uses are defined purely by software.
Software normally uses R13 as a Stack Pointer (SP).
Processor Modes
Most application programs execute in User mode. While the processor is in User mode,
the program being executed is unable to access some protected system resources or to
change mode, other than by causing an exception to occur.
This allows a suitably written operating system to control the use of system resources

CPSR Register

Status Register Across Family

USER Mode
• When writing user level programs, only the 15 general purpose,
32 bit registers (R0-R14), the PC (R15) and the CPSR is
available to the programmer.
• Remaining registers are used only for system level programming
and for handling exceptions (for example, interrupts, system
calls)

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
ARM assembly Language Programming
ARM instruction types
➔ Data processing instructions : They use and change only

register values.
➔ Data transfer instructions : They copy memory values into
register and vice versa.
➔ Control flow instructions : Causes execution to switch to a
different address, either permanently (branch) or by saving a
return address (branch with link) to resume the original
sequence. Supervisor calls are also falls under control flow
instructions.
Conditional Execution
Every ARM instruction can be executed conditionally.
Data Processing Instructions - Binary Encoding
ADD R2, R2,#1
ADD R4,R5, R5, LSL #2
ADD R10,R15,#8
ADDS R4,R5,R6, LSR R7
Note on Immediate Values
ADD R0, R0, #4
A valid immediate operand n satisfies the following equation
n = i ROR ( 2* r)
i = number between 0 and 255 (inclusive)
r = number between 0 and 15 (inclusive)

Arithmetic Operations
➔ Operand may be unsigned or 2’s complement signed numbers.

➔ Carry in, when used, is the current value of the C bit in CPSR.
Bitwise Logical Operations
AND r0, r1, r2 implies r0[i] = r1[i] AND r2[i] for i ranging from 0 to 31.
Register Movement Operations
Register Movement Operations
Comparison Operations
CMP r1,r2 ;set cc on r1-r2 ;compare

CMN r1,r2 ;set cc on r1+r2 ;compare negated
TST r1,r2 ;set cc on r1 and r2 ; (bit) test
TEQ r1,r2 ;set cc on r1 xor r2 ; test equal
Shifted Register Operands
ADD r3, r2,r1, LSL #3 ;r3 = r2 + 8 x r1
LSL - Logical Shift Left; fill the vacated bits with zeros
LSR - Logical Shift Right; fill the vacated bits with zeros
ASL - Arithmetic Shift Left; same as LSL
ASR - Arithmetic Shift Right; fill the vacated bits with 0 if operand was positive else with 1
ROR - Rotate Right by 0 to 32 places; the bit which falls off the LSB will fill the vacated bits
RRX - Rotate Right extended by 1 place; the vacated bit (bit 31) is filled with the old value of
the C flag and the operand is shifted one place to the right. With appropriate use of the
condition codes (see below) a 33-bit rotate of the operand and the C flag is performed.
Data Transfer Instructions
Single Register Load and Store

LDR R0, [R8] ;R0 := mem32 [R8]
LDR R0, [R1, -R2] ;R0 := mem32 [R1-R2]
LDR R0, [R1, +4] ;R0 := mem32 [R1+4]
LDR R0, [R1, +4]! ;R0 := mem32 [R1+4], R1 := R1+4
LDR R0, [R1], +16 ;R0 := mem32 [R1], R1 := R1+16
LDR R0, [R1, R2, LSR#0x4]!
;R0 := mem32 [R1+(R2 LSR 0x4)]
;R1 := R1+R2 LSR 0x4
Multiple Register Transfer Instruction
LDM/STM instructions allow between 1 to 16 registers to be

transferred to or from memory. Block transfer instructions have got
efficient utilization in
➔ implementing stack for saving and restoring context

➔ moving large blocks of data around memory
LDMIA r1, {r0, r2, r5} ; r0 := mem32 [r1]

; r2 := mem32 [r1+4]
; r5 := mem32 [r1+8]
Stack related LDM/STM instructions
Full Stack - SP points to last occupied address, thus needs

pre-decrementing/ pre-incrementing before the push.
Empty Stack - SP points to next to be occupied address, thus require

post-decrementing (descending) / pre-incrementing(ascending) after
the push.
STMFD / LDMFD ; Full descending stack

STMFA/ LDMFA ; Full ascending stack
STMED/ LDMED; Empty descending stack
STMEA/ LDMEA; Empty descending stack
Lowest register number is always transferred to/from the lowest memory location accessed
.
Binary encoding of multiple register transfer instructions
Saving context
STMFD r13!, {r0 - r2, r14}
Restoring context
LDMFD r13!, {r0 - r2, pc}
Block Data Transfer
Same function as stack instructions but different context.
● STMIA / LDMIA ; Increment after

● STMIB / LDMIB ; Increment Before
● STMDA / LDMDA ; Decrement after
● STMDB / LDMDB ; Decrement before
Example
; R12 points to the start of the source data

; R14 points to the end of the source data
; R13 points to the start of the destination data
loop LDMIA R12!, {R0-R11} ; load 48 bytes

STMIA R13!, {R0-R11} ; and store them
CMP R12, R14 ; check for an end
BNE loop ; and loop until done
SWAP Instruction
SWP Rd, Rm, [Rn] ; tmp = mem32[Rn]

; mem32[Rn] = Rm
; Rd = tmp
Rn tmp
2 3
Rm
Rd
Binary Semaphore Using SWP
spin
mov r1, =semaphore
mov r2, #1
swp r3, r2, [r1] ; hold the bus until complete
cmp r3, #1
beq spin
Exceptions
➔ An exception is any condition that needs to halt the normal

sequential execution of instructions.
➔ Reset, instruction fetch or memory access fails, undefined
instruction, software interrupt or external interrupts.
Exception Handling
The ARM architecture supports a range of interrupts, traps and supervisor calls,
all grouped under the general heading of exceptions. They are all handled in
similar way :
1. The current state is saved by copying the PC into R14_exc and the CPSR into
SPSR_exc (where exc stands for the exception type).
2. The processor operating mode is changed to the appropriate mode. ARM
processor mode can also be changed by changing the CPSR.
3. The PC is forced to a value between 0x00 to 0x1C, the particular value
depending on the type of exception. Usually the address of an exception
handler will be located into those values.
4. It disables IRQs by setting bit 7 of the CPSR and if it’s FIQ, disables further
FIQs by setting bit 6 of CPSR.
When an exception occurs the ARM processor always switches to ARM state.
VECTOR TABLE
➔ A table of addresses that the ARM core branches to when an

exception is raised.
➔ These addresses commonly contain branch instructions to
exception handler routines.
Instructions at vector table addresses
Vector table addresses commonly contain branch instructions of one
of the following types:
❏ B <address> Branch relative to PC

❏ LDR PC, [PC, #offset] Loads the handler address from
memory to PC. Address is an absolute 32-bit value stored close
to the vector table. Delay in branching hence latency but can be
branched to any address in memory.
❏ LDR PC, [PC, #-0xff0] Loads ISR address from
0xFFFFF030. Will be explained with Vectored Interrupt
Controller in next class.
❏ MOV PC, #immediate Copies an immediate value into PC.
But immediate value is limited by constraints discussed earlier.
Exception Return
Once the exception has been handled, the user task is normally
resumed. This requires the handler code to restore the user state
exactly as it was when the exception first arose:
❏ Any modified user registers must be restored from the handler’s

stack.
❏ The CPSR must be restored from the appropriate SPSR.
❏ The PC must be changed back to relevant instruction address in
the user instruction stream.
Exception Return Contd...
❏ If CPSR is restored first, the banked R14 holding the return

address is no longer accessible.
❏ If the PC is restored first, the exception handler loses control of
the instruction stream and can not cause the restoration of CPSR
to take place.
❏ There is a need for an instruction that can perform both of these
tasks atomically as a single instruction.
To return from a SWI or undefined instruction:
MOVS PC, R14
To return from an IRQ, FIQ or prefetch abort
SUBS PC, R14, #4 ; PC = PC - 4

because there is an S at the end of SUB and PC is the destination
register, the cpsr is automatically stored from the spsr register.
To return from an data abort to retry the data access
SUBS PC, R14, #8 ; PC = PC - 8

Link Register Offsets
Exception Priorities
ASM Example Code

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
Keil ARM MDK Demo for ARM assembly
Language Programming
ASM Example Code

Exceptions
➔ An exception is any condition that needs to halt the normal
sequential execution of instructions.
➔ Reset, instruction fetch or memory access fails, undefined
instruction, software interrupt or external interrupts.

Exception Handling
The ARM architecture supports a range of interrupts, traps and supervisor calls,
all grouped under the general heading of exceptions. They are all handled in
similar way :
1. The current state is saved by copying the PC into R14_exc and the CPSR into
SPSR_exc (where exc stands for the exception type).
2. The processor operating mode is changed to the appropriate mode. ARM
processor mode can also be changed by changing the CPSR.
3. The PC is forced to a value between 0x00 to 0x1C, the particular value
depending on the type of exception. Usually the address of an exception
handler will be located into those values.
4. It disables IRQs by setting bit 7 of the CPSR and if it’s FIQ, disables further
FIQs by setting bit 6 of CPSR.
When an exception occurs the ARM processor always switches to ARM state.

VECTOR TABLE
➔ A table of addresses that the ARM core branches to when an
exception is raised.
➔ These addresses commonly contain branch instructions to
exception handler routines.

Instructions at vector table addresses
Vector table addresses commonly contain branch instructions of one
of the following types:
❏ B <address> Branch relative to PC
❏ LDR PC, [PC, #offset] Loads the handler address from
memory to PC. Address is an absolute 32-bit value stored close
to the vector table. Delay in branching hence latency but can be
branched to any address in memory.
❏ LDR PC, [PC, #-0xff0] Loads ISR address from
0xFFFFF030. Will be explained with Vectored Interrupt
Controller in next class.
❏ MOV PC, #immediate Copies an immediate value into PC.
But immediate value is limited by constraints discussed earlier.

Exception Return
Once the exception has been handled, the user task is normally
resumed. This requires the handler code to restore the user state
exactly as it was when the exception first arose:
❏ Any modified user registers must be restored from the handler’s
stack.
❏ The CPSR must be restored from the appropriate SPSR.
❏ The PC must be changed back to relevant instruction address in
the user instruction stream.

Exception Return Contd...
❏ If CPSR is restored first, the banked R14 holding the return
address is no longer accessible.
❏ If the PC is restored first, the exception handler loses control of
the instruction stream and can not cause the restoration of CPSR
to take place.
❏ There is a need for an instruction that can perform both of these
tasks atomically as a single instruction.

To return from a SWI or undefined instruction:
MOVS PC, R14
To return from an IRQ, FIQ or prefetch abort
SUBS PC, R14, #4 ; PC = PC - 4

because there is an S at the end of SUB and PC is the destination
register, the cpsr is automatically stored from the spsr register.
To return from an data abort to retry the data access
SUBS PC, R14, #8 ; PC = PC - 8

Link Register Offsets

Exception Priorities

Software Interrupt Instruction (SWI)
A software Interrupt instruction (SWI) causes a software
interrupt exception, which provides a mechanism for
applications to call operating system calls.

SWI Handler
; Store registers r0-r12 and the link register
STMFD sp!, {r0-r12, lr}
; Read the SWI instruction
LDR r10, [lr, #-4]
; Mask off top 8 bits
BIC r10, r10, #0xff000000
; r10 - contains the SWI number
BL service_routine
; return from SWI handler
LDMFD sp!, {r0-r12, pc}ˆ

Architectural Support for High Level
Languages
High level language?
Being an RISC architecture, it is tricky to design an efficient
compiler for ARM based SoCs.
Everything need to be done using a limited set of instructions,

operands has to be in CPU registers and take care of memory
alignment restrictions, immediate operand values etc.
C!
➔ Data types, Basic and Derived

➔ Floating point arithmetic
➔ Expressions
➔ Conditional Statements
➔ Functions
➔ Dynamic memory allocation
Support for Basic Data Types
ARMv4 based processors can efficiently load and store 8, 16 or 32

bit data. However, most of the ARM data processing operations are
32-bit only.
One should use 32-bit data type and avoid using char or short
wherever possible. If you requires modulo arithmetic of the form
255+1 = 0, then use the char type.
Compiler Output with ‘i’ as char
Compiler output with ‘i’ as integer
Expressions in C
➔ Basic ARM data processing instructions implements most of the

the C integer arithmetic, bit-wise and shift primitives directly.
➔ Key to efficient evaluation of a complex expression is to get the
required values into local registers in the right order and
efficient utilization of local registers.
➔ The 3 address instruction format allows the reuse of registers
and provides flexibility to the compiler in using them.
➔ Shifted operand in data processing instructions allows single
cycle execution of many complex expressions.
Compiler casts the return value to a short type, but does not case the input values.
It assumes that the caller has already ensured that the 32-bit values r0 and r1 are in
the range of short type.
ARM Procedure Call Standard (APCS)
Function Calls
Number of arguments (variables Vs structures)
Compiles to...
Same function using structure as argument
Compiles to...
EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
LPC2xxx
Analog to Digital Demo
ADC in LPC2xxx Series
➔ LPC2148 has two inbuilt ADC modules, ADC0 & ADC1.

➔ Each ADC is of 10 bit resolution, using Successive
approximation conversion technique.
➔ ADC0 has 6 channels and ADC1 has 8 channels. (14 analog
Channels)
➔ Supports maximum clock at 4.5 MHz.
➔ 10 bit conversion time >= 2.44 s
➔ The register we must know about is, ADC Control register
(AD0CR or AD1CR) & ADGDR (ADC Global data register)
ADC in LPC2xxx Series
➔ Optional conversion on transition on input pin or Timer Match

signal.
➔ Measurement range 0 V to VREF (3V typical)
➔ Basic clocking for the A/D converters is provided by the APB
clock. A programmable divider is included in each converter, to
scale this clock to the 4.5 MHz (max) clock needed by the
successive approximation process.
➔ A fully accurate conversion requires 11 of these clocks.
STEP-1 Enable ADC Pins using PINSEL
Pin function Select register 0 (PINSEL0 - 0xE002 C000)
PINSEL0= PINSEL0| (3<<8) ; // AD0_6
PINSEL0= PINSEL0| (3<<10) ; // AD0_7

STEP-2 Configure ADC Peripheral Clock
Related Register - ADCR A/D Control Register. The ADCR
register must be written to select the operating mode before A/D
conversion can occur
REF : UM10139 NXP

STEP-2 Configure ADC Peripheral Clock
Related Register - ADCR A/D Control Register. The ADCR

register must be written to select the operating mode before A/D
conversion can occur
#define CLKDIV 6
// Dividing PCLK by CLKDIV

AD0CR = AD0CR|(0x0000FF00&(CLKDIV<<8));
STEP-3 Enable ADC
Related Register - ADCR 21st Bit PDN
#define PDN 1<<21
AD0CR = AD0CR|PDN; // ADC is operational

STEP-4 Select ADC Channel and its mode
REF : UM10139 NXP

REF : UM10139 NXP

STEP-5 Read Converted Data
Related Register - (AD0GDR - 0xE003 4004 , AD1GDR - 0xE006 0004
REF : UM10139 NXP

STEP-5 Read Converted Data
#define DATA_MASK 0x0000FFC0;
// wait to finish conversion

while(!(AD0GDR&(0x80000000)));
val = AD0GDR;
val = val & DATA_MASK;
return(val>>6);
Timer Demo -1 Accurate Delay Function
● 32-bit Timer/Counter with a programmable 32-bit Prescaler.

● Counter or Timer operation
● Up to four 32-bit capture channels per timer, that can take a
snapshot of the timer value when an input signal transitions.
● A capture event may also optionally generate an interrupt.
● Four 32-bit match registers that allow:
○ Continuous operation with optional interrupt generation on match.
○ Stop timer on match with optional interrupt generation.
○ Reset timer on match with optional interrupt generation.
Timer Demo -1 Accurate Delay Function
➔ Up to four external outputs corresponding to match registers,

with the following capabilities:
◆ Set low on match.
◆ Set high on match.
◆ Toggle on match.
◆ Do nothing on match
STEP- 1 Understanding Timer Modes
REF : UM10139 NXP

STEP- 1 Understanding Timer Modes
REF : UM10139 NXP

STEP- 2 Deriving the Data for desired task
EEEZG512
Embedded Systems Design
Devesh Samaiya
Dept. of Electrical & Electronics Engg
BITS Pilani
BITS Pilani
Pilani Campus
EEE ZG512
Serial Peripheral Interface
LPC2xxx SoC
Introduction
SPI is a full duplex serial interface.
It can handle multiple masters and slaves being connected to a given bus.
Only a single master and a single slave can communicate on the interface during a given
data transfer.
During a data transfer the master always sends 8 to 16 bits of data to the slave, and the
slave always sends a byte of data to the master.
Ring Buffer
SPI data to CPOL, CPHA relationship
SPI CPOL, CPHA Significance (AT93C46 EEPROM)
http://ww1.microchip.com/downloads/en/DeviceDoc/doc5140.pdf
The Read (READ) instruction contains the address code for the memory location to be read.
After the instruction and address are decoded, data from the selected memory location is
available at the serial output pin DO. Output data changes are synchronized with the rising
edges of serial clock SK.
SPI CPOL, CPHA Significance (W25Q64 FLASH)
https://www.winbond.com/resource-files/w25q64fw_revk%2007012
READ instruction (03h) is initiated by driving the CS pin low and shifting out instruction (03h)
and 24-bit address (A23-A0) on DI pin.The instruction code and address bits are latched on the
rising edge of the CLK input. Data is shifted out on DO at falling edge of the CLK pin.
016%20sfdp.pdf
SPI0 Registers in LPC2148
MASTER OPERATION
The following sequence describes how one should process a data transfer with the SPI block when it
is set up to be the master. This process assumes that any prior data transfer has already completed
1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI data
transfer.
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
5. Read the SPI status register.
6. Read the received data from the SPI data register (optional).
7. Go to step 3 if more data is required to transmit.
SLAVE OPERATION
The following sequence describes how one should process a data transfer with the SPI block when it
is set up to be a slave. This process assumes that any prior data transfer has already completed. It is
required that the system clock driving the SPI logic be at least 8X faster than the SPI.
1. Set the SPI control register to the desired settings.

2. Write the data to transmitted to the SPI data register (optional). This can only be done
when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI status register.
5. Read the received data from the SPI data register (optional).
6. Go to step 2 if more data is required to transmit.
Interfacing Example
Interfacing Example
Source - https://www.diodes.com/assets/Datasheets/74HC595.pdf
2
I C Protocol
devesh.samaiya@pilani.bits-pilani.ac.in
I2C
Developed by Philips Semiconductor (now NXP) as a simple bidirectional two wire bus
protocol for efficient inter-IC data communication. Originally, the I2 C bus was designed to
link a small number of devices on a single card, such as to manage the tuning of a car radio
or TV.
This bus is called the Inter IC or I2C-bus. All I2C-bus compatible devices incorporate an
on-chip interface which allows them to communicate directly with each other via the
I2C-bus.
Features
➔ Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
➔ Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
➔ It is a true multi-master bus including collision detection and arbitration to prevent
data corruption if two or more masters simultaneously initiate data transfer.
➔ Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.
Pg. 4 https://www.nxp.com/docs/en/user-guide/UM10204.pdf
SDA & SCL Signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free, both lines are HIGH.
SDA & SCL Signal Levels
➔ Due to the variety of different technology devices (CMOS, NMOS, bipolar)
that can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and
‘1’ (HIGH) are not fixed and depend on the associated level of VDD.
➔ Input reference levels are set as 30 % and 70 % of VDD; VIL is 0.3VDD and
VIH is 0.7VDD.
START & STOP conditions
➔ All transactions begin with a START (S) and are terminated by a STOP (P).
➔ A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START
condition.
➔ A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
DATA Validity
➔ The data on the SDA line must be stable during the HIGH period of the clock.
➔ The HIGH or LOW state of the data line can only change when the clock signal on
the SCL line is LOW .
➔ One clock pulse is generated for each data bit transferred.
Byte format
➔ Every byte put on the SDA line must be eight bits long.
➔ The number of bytes that can be transmitted per transfer is unrestricted.
➔ Each byte must be followed by an Acknowledge bit.
➔ Data is transferred with the Most Significant Bit (MSB) first.
➔ If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, for example servicing an internal interrupt, it can
hold the clock line SCL LOW to force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data and releases clock line
SCL.
ACK / NACK
➔ The acknowledge takes place after every byte. The acknowledge bit allows the
receiver to signal the transmitter that the byte was successfully received and another
byte may be sent. The master generates all clock pulses, including the acknowledge
ninth clock pulse.
➔ The transmitter releases the SDA line during the acknowledge clock pulse so the
receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
➔ When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to abort
the transfer, or a repeated START condition to start a new transfer.
ACK / NACK
There are five conditions that lead to the generation of a NACK:
1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledge.
2. The receiver is unable to receive or transmit because it is performing some real-time

function and is not ready to start communication with the master.
3. During the transfer, the receiver gets data or commands that it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver must signal the end of the transfer to the slave transmitter.
Slave address and R/W’ bit
After the START condition (S), a slave address is sent. This address is seven bits long
followed by an eighth bit which is a data direction bit (R/W) — a ‘zero’ indicates a
transmission (WRITE), a ‘one’ indicates a request for data (READ).
Master Transmitter
Master Receiver
Master Transceiver
Arbitration
Arbitration, refers to a portion of the protocol required only if more than one master is
used in the system.
A master may start a transfer only if the bus is free. Two masters may generate a START
condition on the bus at the same time. Arbitration is then required to determine which
master will complete its transmission.
Arbitration
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks
to see if the SDA level matches what it has sent.
This process may take many bits. Two masters can actually complete an entire transaction
without error, as long as the transmissions are identical.
The first time a master tries to send a HIGH, but detects that the SDA level is LOW, the
master knows that it has lost the arbitration and turns off its SDA output driver. The other
master goes on to complete its transaction.
I2C Protocol Summary
I2C in LPC2xxx
➔ Standard I2C compliant bus interfaces that may be configured as Master or Slave.
➔ Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
➔ Programmable clock to allow adjustment of I2C transfer rates.
➔ Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
I2C Bus configuration
I2C Operating Modes
➔ In a given application, the I2C block may operate as a master, a slave or both.
➔ If processor wishes to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave operation is not interrupted.
➔ If bus arbitration is lost in the master mode, the I2C block switches to the slave mode
immediately and can detect its own slave address or general call address in the same
serial transfer.
Master Transmitter Mode
➔ I2EN must be set to 1 to enable the I2C function.

➔ If AA bit is 0, the I2C interface will not acknowledge any address when another
device is master of the bus. It basically not the master itself but not a slave
either.
➔ STA, STO, SI bts must be 0. The SI bit is cleared by writing 1 to the SIC bit in
the I2CCONCLR register.
Master Transmitter Mode Contd.
➔ The I2C interface will enter the master transmitter mode when software sets the STA
bit. The I2C logic block will send the START condition as soon as the bus is free.
➔ After the START condition is transmitted, the SI bit is set, and the status code in the
I2CSTAT register is 0x08.
➔ This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit.
➔ After slave+r/w transmission and acknowledgement reception the SI bit is set again,
and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or
0x68, 0x78, or 0xB0 if the slave mode was enabled.
Transfer Rate Calculation
LAB Experiment on I2C
Interfacing I2C EEPROM device, 24Cxx series.
24Cxx I2C EEPROM Interfacing
USB
devesh.samaiya@pilani.bits-pilani.ac.in
Universal Serial Bus
➔ Universal serial bus (USB) is a communication protocol for
connecting variety of peripheral devices to the host computer.
➔ The aim of the USB interface was to find a solution to the
mixture of connection methods to the PC, in use at the time.
➔ We had serial port, parallel port, keyboard, mouse, midi,
joystick ports and so on, none of these were plug and play.
Features
➔ Single standardized interface socket.
➔ Plug and play capabilities (hot swapping)
➔ Provides power to low consumption devices.
➔ Allows many devices to be used without requiring manufacturer specific, individual
device drivers to be installed.
➔ Allows all kind of peripheral devices to communicate with the computer using a
single standard protocol and connection method.
One connector to rule them all
So the USB was developed as a new means to connect a large
number of devices to the PC, and eventually to replace the 'legacy'
ports.
USB Connectors
USB Host & Devices
➔ USB is based on a so-called 'tiered star
topology' in which there is a single host
controller and up to 127 'slave' devices.
➔ A device can be plugged into a hub, and
that hub can be plugged into another
hub and so on. However the maximum
number of tiers permitted is six.
Device Classes
http://www.usb.org/developers/defined_class
Master Slave
➔ USB is a master slave protocol.
➔ Host is the master and all the communication on the bus is initiated by the Host.
➔ There can be no communication directly between 2 USB devices.
➔ A device cannot initiate a transfer, but must wait to be asked to transfer data by the
host. The only exception to this is when a device has been put into 'suspend' (a low
power state) by the host then the device can signal a 'remote wakeup'.
Bus enumeration
➔ The host regularly polls hubs for their status.
➔ When a new device is plugged into a hub, the hub advises the host of its
change of state.
➔ The host controller in turn issues a command to enable and reset the port.
➔ Device responds and host collects information about the device.
➔ Based on the retrieved information, the host operating system determines the
device driver to be used for the device.
➔ The process of detection and identification of USB devices by a host is called
bus enumeration.
Transactions
REF : http://www.usbmadesimple.co.uk/ums_3.htm
Packet Formats 1/4
Packet ID (PID) : The first byte in every
packet is a Packet Identifier (PID) byte.
This byte needs to be recognised quickly
by the USB engine and so is not included
in any CRC checks. It therefore has its
own validity check. The PID itself is 4
bits long, and the 4 bits are repeated in an
complimented form.
Packet Formats 2/4
Token Packet : Used for SETUP, OUT and IN packets. They are always the first packet in
a transaction, identifying the targeted endpoint, and the purpose of the transaction
SYNC PID ADDR ENDP CRC5 EOP
8 bits 7 bits 4 bits 5 bits
USB transaction token packet format

Packet Formats 3/4
Data Packet : Used for DATA0, DATA1, DATA2 and MDATA packets. If a transaction
has a data stage this is the packet format used.
SYNC PID DATA CRC16 EOP
8 bits (0-1024) x 8 16 bits

bits
USB transaction data packet format

Packet Formats 4/4
Handshake Packet : Used for ACK, NAK, STALL and NYET packets. This is the packet
format used in the status stage of a transaction, when required.
SYNC PID EOP
8 bits
USB transaction handshake packet format

Data Flow Types
Data flow type Description

Control Transfer Mandatory to use Endpoint 0 IN and OUT.
Bulk Transfer Error free high volume throughput when

bandwidth is available
Interrupt Transfer Error free, low throughput, regular opportunity

for status updates etc.
Isochronous Transfer No error check, fixed bandwidth guaranteed

Endpoints
➔ USB device communication is based on pipes (logical
channels).
➔ Pipes are connections from the host controller to a logical
entity on the device, known as Endpoint.
➔ USB device can have up to 32 active endpoints - 16 into
the host controller and 16 out of the host controller..
➔ Each endpoint can transfer data in one direction only.
An endpoint has characteristics that determine the type of transfer service required
between the endpoint and the client software. An endpoint describes itself by:
➔ Bus access frequency/latency requirement

➔ Bandwidth requirement
➔ Endpoint number
➔ Error handling behavior requirements
➔ Maximum packet size that the endpoint is capable of sending or receiving
➔ The direction in which data is transferred between the endpoint and the host
Types of USB Endpoints
A USB endpoint can be one of four different types that describe how the data is
transmitted on it: (Why do we need 4 different types of endpoints)
CONTROL
INTERRUPT
BULK
ISOCHRONOUS
CONTROL ENDPOINT
➔ Control endpoints are used to allow access to different parts of the USB
device.
➔ They are commonly used for configuring the device, retrieving information
about the device, sending commands to the device, or retrieving status reports
about the device.
➔ Every USB device has a control endpoint called "endpoint 0" that is used by
the USB core to configure the device at insertion time.
➔ These transfers are guaranteed by the USB protocol to always have enough
reserved bandwidth to make it through to the device.
CONTROL TRANSFER
It is divided into three stages.
1. The SETUP stage carries 8 bytes called the Setup packet. This defines the request,
and specifies whether and how much data should be transferred in the DATA stage.
2. The DATA stage is optional. If present, it always starts with a transaction containing a
DATA1. The type of transaction then alternates between DATA0 and DATA1 until all
the required data has been transferred.
3. The STATUS stage is a transaction containing a zero-length DATA1 packet. If the
DATA stage was IN then the STATUS stage is OUT, and vice versa.
Control transfers are used for initial configuration of the device by the host, using Endpoint 0 OUT and Endpoint 0
IN, which are reserved for this purpose. They may be used (on the same endpoints) after configuration as part of the
device-specific control protocol, if required.
CONTROL TRANSFER
REF : http://www.usbmadesimple.co.uk/ums_3.htm
SETUP PACKET
Possible bRequest types in control transaction
INTERRUPT ENDPOINT
➔ They have nothing to do with interrupts.
➔ Interrupt endpoints transfer small amounts of data at a fixed rate every time the
USB host asks the device for data.
➔ These endpoints are the primary transport method for USB keyboards and
mice.
➔ They are also commonly used to send data to USB devices to control the
device, but are not generally used to transfer large amounts of data.
➔ These transfers are guaranteed by the USB protocol to always have enough
reserved bandwidth to make it through.
BULK ENDPOINTS
➔ Bulk endpoints transfer large amounts of data.
➔ These endpoints are usually much larger (they can hold more characters at
once) than interrupt endpoints.
➔ They are common for devices that need to transfer any data that must get
through with no data loss. These transfers are not guaranteed by the USB
protocol to always make it through in a specific amount of time.
➔ If there is not enough room on the bus to send the whole BULK packet, it is
split up across multiple transfers to or from the device. These endpoints are
common on printers, storage, and network devices.
ISOCHRONOUS ENDPOINT
➔ Isochronous endpoints also transfer large amounts of data,

but the data is not always guaranteed to make it through.
➔ These endpoints are used in devices that can handle loss
of data, and rely more on keeping a constant stream of
data flowing.
➔ Real-time data collections, such as audio and video
devices, almost always use these endpoints.
Device, Config, Interface & Endpoints
Device, Interface & Endpoints
USB devices are quite complex and are made up of lots of
different logical units. The relationships among these units can
be simply described as follows:
➔ Devices usually have one or more configurations.

➔ Configurations often have one or more interfaces.
➔ Interfaces have zero or more endpoint
➔ Every device is identified using a Device Descriptor structure. Host will fetch
this descriptor from device to know about the nature of the device.
➔ Possible configurations of the device are identified using a configuration

descriptor and host will enquire this to gather more information about device.
➔ Interfaces usually have one or more settings which are specified in the
Interface descriptor.
➔ Finally Interfaces have zero or more endpoint and each endpoint is described
using Endpoint descriptor structure.
USB
DEVICE DESCRIPTOR
STRUCTURE
USB Configuration Descriptor Format
USB Interface Descriptor
USB
ENDPOINT
DESCRIPTOR
FORMAT
USB Frames and Microframes
➔ USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
packet each and every 1ms period.
➔ USB also defines a high-speed microframe with a 125 μs frame time
➔ SOF packets are generated (by the host controller) every 1ms for full-speed
links.
Image source: USB

2.0 Specifications
Summary
➔ USB is a 4 wire bus that supports communication between a host and a number of
(127 max) peripherals.
➔ The host controller allocates the USB bandwidth to the attached device through a
token based protocol.
➔ Bus supports hot plugging, un-plugging and dynamic configuration of the device.
➔ All transactions are initiated by the host.
➔ Each device can have maximum of 16 logical and 32 physical endpoints.
Summary
4 types of transfer are defined for the endpoints: control, interrupt, isochronous and bulk.
➔ Control transfers are used to configure the device.

➔ Interrupt transfers are used for periodic data transfer.
➔ Bulk transfer is used when rate of transfer is not critical but it has to be error free.
➔ Isochronous transfers have guaranteed delivery but no error check or correction.
USB is a host controlled protocol. Irrespective of whether the data transfer is from device
to host or host to device, transfer sequence is always initiated by the host.
During data transfer from device to the host, the host sends an IN token to the device,
following which the device responds with the data.
USB device peripheral in LPC2148
• Fully compliant with USB 2.0 Full Speed specification
• Supports 32 physical (16 logical) endpoints
• Supports Control, Bulk, Interrupt and Isochronous endpoints
• Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time
• RAM message buffer size based on endpoint realization and maximum packet size
• Supports Soft Connect feature and Good Link LED indicator
• Supports bus-powered capability with low suspend current
• Support DMA transfer with the DMA RAM of 8 kB on all non-control endpoints (LPC2146/8 only)
• One Duplex DMA channel serves all endpoints
• Allows dynamic switching between CPU controlled and DMA modes
• Double buffer implementation for Bulk & Isochronous endpoints
LPC2148: USB Device Controller
➔ The device controller enables 12 Mb/s data exchange with a USB host controller.
➔ It consists of register interface, serial interface engine, endpoint buffer memory and
DMA controller.
➔ The serial interface engine decodes the USB data stream and writes data to the
appropriate endpoint buffer memory.
➔ The status of a completed USB transfer or error condition is indicated via status
registers. An interrupt is also generated if enabled.
➔ The DMA controller when enabled transfers data between the endpoint buffer and the
USB RAM.
Pre-fixed Endpoint Configuration
Pre-fixed Endpoint Configuration
USB Peripheral Device Block
Data flow from Host to Device
➔ The USB device protocol engine receives the serial data from the USB analog
transceiver and converts it into a parallel data stream.
➔ The parallel data is sent to the RAM interface which in turn transfers the data to the
endpoint buffer.
➔ The endpoint buffer is implemented as an SRAM based FIFO. Each realized endpoint
will have a reserved space in the RAM.
➔ So the total RAM space required depends on the number of realized endpoints,
maximum packet size of the endpoint and whether the endpoint supports double
buffering.
Data Flow
➔ For non-isochronous endpoints, when a full data packet is received without any
errors, the endpoint generates a request for data transfer from its FIFO by generating
an interrupt to the system.
➔ Isochronous endpoint will have one packet of data to be transferred in every frame. So
the data transfer has to be synchronized to the USB frame rather than packet arrival.
So, for every 1 ms there will be an interrupt to the system.
➔ The data transfer follows the little endian format. The first byte received from the
USB bus will be available in the least significant byte of the receive data register.
Data Flow from Device to Host
➔ For data transfer from an endpoint to the host, the host will send an IN token to that
endpoint. If the FIFO corresponding to the endpoint is empty, the device will return a
NAK and will raise an interrupt to the system.
➔ On this interrupt the CPU fills a packet of data in the endpoint FIFO. The next IN
token that comes after filling this packet will transfer this packet to the host.
➔ The data transfer follows the little endian format. The first byte sent on the USB bus
will be the least significant byte of the transmit data register.
Software Interface
Software interface of the USB device block consists of a register view and the format
definitions for the endpoint descriptors.
A few important registers
USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)
Each physical non-isochronous endpoint is represented by one bit in this register to
indicate that it has generated the interrupt.
USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)
➔ All non-isochronous OUT endpoints give an interrupt when they receive a packet
without any error.
➔ All non-isochronous IN endpoints will give an interrupt when a packet is successfully
transmitted or a NAK handshake is sent on the bus provided that the interrupt on
NAK feature is enabled.
➔ Isochronous endpoint transfer takes place with respect to frame interrupt. The
USBEpIntSt is a read only register.
➔ All these interrupts can be enabled or disabled using USBEpIntEn and USBEpIntClr
registers respectively
USB Realize Endpoint register (USBReEp - 0xE009 0044)
➔ Though fixed-endpoint configuration implements 32 endpoints, it is not a must that all
have to be used. If the endpoint has to be used, it should have buffer space in the
EP_RAM.
➔ The EP_RAM space can be optimized by realizing a subset of endpoints.
➔ This is done through programming the Realize Endpoint register. Each physical
endpoint has one bit as shown below. The USBReEp is a read/write register
Virtual COM Port Device (Vendor Specific)
Virtual COM port driver allows your PC to recognize and communicate with the remote
target as a COM port regardless the under-layer hardware connection between the PC and
target system.
For example, if the LPC2148 is programmed as a COM port device, actual connection is
through USB but it will appear to the PC as a COM port. When the USB cable is
connected, the target looks like a real serial port communicating with the PC Hyper
Terminal Software on the Windows platform.
Also called USB to serial converter. (Remember CH340, CP2102 ?)

USB Operation on the device side
The operation of the USB device driver can be simply defined in three phases:
1. Reset,
2. Enumeration, and
3. Operation phase.
USB reset phase
➔ The USB device will be in the reset phase after power-on reset.
➔ When the USB device is attached to the PC USB host, the host will issue a reset
signal.
➔ When a USB reset signal is detected on the bus, on the device side, the DEV_STAT
bit in the Device Interrupt Register is set and a USB interrupt will be generated.
➔ The USB device will process the RESET interrupt and set itself to the default
configuration state. The initial address of the USB device is set to zero at reset phase.
➔ After the reset signal is released and RESET interrupt has been processed, the device
will enter the enumeration phase.
USB enumeration and standard requests
➔ During the enumeration phase, the host performs a bus enumeration to identify the
attached devices by sending a series of requests on the control pipe (endpoint 0 OUT)
using standard device request to get the device information and configuration, and
then, assign a unique address to it.
➔ Based on the information it gets, if necessary, send SET_FEATURE,
SET_CONFIGURATION, and/or SET_INTERFACE requests to reconfigure the
device.
➔ The device responds to the host requests on its default control pipe (endpoint 0 IN).
Endpoint configuration for virtual COM port
In the virtual COM port device driver implementation, more than one interface descriptors
can be created to accommodate multiple virtual COM ports.
Under each interface descriptor, vendor specific class code (0xFF) has been chosen.
Endpoint configuration for virtual COM port
Interface number EP Number (Physical Description
Endpoint, type)
0 EP1 IN (3, Interrupt) Report modem status of the device

in UART0 or virtual COM port 0
0 EP2 OUT (4, Bulk) Data transfer from host to the

device on UART0 or virtual COM
port 0
0 EP2 IN (5, Bulk) Data transfer from device to the

host on UART0 or virtual COM port
0
1 EP4 IN (9, Interrupt) Report modem status of the device

in UART1 or virtual COM port 1
1 EP5 OUT (10, Bulk) Data transfer from host to the

device on UART1 or virtual COM
port 1
1 EP5 IN (11, Bulk) Data transfer from device to the

host on UART1 or virtual COM port
1
Virtual COM Port protocol
In order to establish the COM port communication, after the USB Reset phase and entering
the enumeration phase, the USB host is responsible for sending the COM port information
such as COM port baud rate, data bits, stop bits, hardware handshaking to the USB device.
To do so, USB host uses the vendor specific request to set up the virtual COM port on the
USB device.
Virtual COM Port Setup
Based on the vendor specific request from the host, the USB device will configure the
on-chip COM port accordingly. Once the configuration is accomplished, the data from the
USB host can be transmitted or received to/from the on-chip COM port seamlessly via the
virtual COM port.
SETUP PACKET
The first byte of the setup packet represents “Request Type”. The Request Type identifies
the characteristics of the request shown as follows:
In the second byte, “Request” field specifies the particular request for configuring the
UART device followed with a value shown as follows:
UART Channel Selection
Bit 7, 6, and 5 of the “Request” is used to represent the channel number of UART as
shown on the following table.
Vendor Specific Device Request Example
As seen in the second column of above table, 0x41 indicates the direction of the setup
request is from host to device (bit 7 is 0), the type is “vendor” (bit 6 and 5 is 10b), and the
recipient is “interface” (bit 4 through 0 is 00001b). Finally, the SETUP request is to set the
baud rate of the COM port 0 at 9600.
The index and length fields in the vendor specific interface request table are defined but not
used. They are reserved for future expansion.
Initialization
➔ After the power up, the USB initialization should include below steps:
➔ Turn on USB PCLK
➔ Configure 48Mhz PLL1 for USB clock
➔ Setup Vectored Interrupt Controller (VIC) for USB
➔ Set up minimum numbers of USB registers including index and packet size register
for Control OUT (0) and Control IN (1) endpoints.
➔ Set USB Device Interrupt Enable register
➔ Use protocol engine commands SET_ADDRESS to reset device address to zero, and
SET_DEVICE_STATUS to make a soft connection
LPC2148 USB Command Code register (USBCmdCode - 0xE009 0010)
➔ This register is used for writing the commands.

➔ The commands written here will get propagated to the Protocol Engine and will be
executed there.
➔ After executing the command, the register will be empty, and the “CCEMTY” bit of
the Interrupt Status register is set high.
LPC2148 USB Command Data register (USBCmdData - 0xE009 0014)
➔ This is a read-only register which will carry the data retrieved after executing a
command.
➔ When this register is ready, the “CD_FULL” bit of the Device Interrupt Status register
is set. The CPU can poll this bit or enable an interrupt corresponding to this to sense
the arrival of the data.The data is always one-byte wide
LPC2148 Protocol Engine Commands
➔ The protocol engine operates based on the commands issued from the CPU.
➔ These commands have to be written into the Command Code register
➔ The read data when present will be available in the Command Data register after the
successful execution of the command.
When the CPU has written data into an IN buffer, it should set the buffer full flag by
the Validate Buffer command. This indicates that the data in the buffer is valid and
can be sent to the host when the next IN token is received
Set Address (Command: 0xD0, Data: write 1 byte)
➔ The Set Address command is used to set the USB assigned address and enable the
(embedded) function.
➔ The address set in the device will take effect after the status phase of the setup token.
(Alternately, issuing the Set Address command twice will set the address in the
device).
➔ At power on reset, the DEV_EN is set to 0. After bus reset, the address is reset to
0x00. The enable bit is set to 1. The device will respond on packets for function
address 0x00, endpoint 0 (default endpoint).
Configure Device (Command: 0xD8, Data: write 1 byte)
A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled and
respond even if the device is not configured, in the default state.
Refer to section 14.9 in UM10139 document for all the different command codes and their purposes.
LPC2148 USB LAB Demo :Class Specific Drivers
➔ To implement a CDC (Communication Device Class) with subclass 0x02
device.
➔ Windows has inbuilt USB Serial driver called USBSer.sys.
➔ USBSer.sys enumerates with the attached device as per the USB CDC
subclass 2 protocol.
➔ Our device must be programmed to respond to those requests.
So, for class specific device drivers, our device must respond to both standard requests and
class specific requests. It must provide class specific descriptors when asked to and
respond to class specific request coming via setup packet.
USB CDC Class
The Communication Device Class (CDC) supports a wide range
of devices that can perform telecommunications and networking
functions. Examples for communications equipment are:
● Telecommunications devices, such as analog phones and
modems, ISDN terminal adapters, digital phones, as well as
COM-port devices
● Networking devices, such as ADSL and cable modems, as well
as Ethernet adapters and hubs
CDC Subclasses
Class Specific Descriptors
Class-Specific Device Descriptor
This descriptor contains information applying to the entire communication device. The
Communication Device Class does not currently use any class-specific descriptor
information at the Device level.
Class-Specific Configuration Descriptor

The Communication Device Class currently does not use any class-specific descriptor
information at the Configuration level
Functional Descriptors
Functional descriptors describe the content of the class-specific information within an
Interface descriptor. Functional descriptors all start with a common header descriptor,
which allows host software to easily parse the contents of class specific descriptors. Each
class-specific descriptor consists of one or more functional descriptors.
Functional Descriptors Contd.
ACM Functional Descriptor : bmCapabilities
Class Specific Requests
REF: USB CDC SPECIFICATION

VCOM Init function
Descriptors in Demo Code
Human Interface Devices
Class
USB - HID Class
➔ All data exchanged resides in structures called reports.
➔ The host sends and receives data by sending and requesting reports in control or
interrupt transfers. The report format is flexible and can handle just about any type of
data.
➔ A HID must have an interrupt IN endpoint for sending Input reports.
➔ A HID can have at most one interrupt IN endpoint and one interrupt OUT endpoint. A
device that requires more interrupt endpoints can be a composite device with multiple
HID interfaces. An application obtains separate handles for each HID in the device
➔ The interrupt IN endpoint enables the HID to send information to the host at
unpredictable times. For example, there’s no way for the host computer to
know when a user will press a key on the keyboard, so the host’s driver uses
interrupt transactions to poll the device periodically to obtain new data.
HID Class Descriptor
HID Report Descriptor 1/3
A report descriptor is a class-specific descriptor. The host
retrieves the descriptor by sending a Get Descriptor request
to the interface with the wValue field containing 22h in the
high byte.
The Usage Page item (06h) specifies the general function of

the device, such as generic desktop control, game control,
or alphanumeric display. In the example,descriptor, the
Usage Page is the vendor-defined value FFA0h.
The Usage item (09h) specifies the function of an individual

report in a Usage Page. For example, Usages available for
generic desktop controls include mouse, joystick, and
keyboard.
● The Collection (Application) item (A1h) begins a group of
items that together perform a single function, such as
keyboard or mouse. Each report descriptor must have an
application collection
● The Collection contains three reports. Each report has

these items: A vendor-defined Usage applies to the data
in the report. A Logical Minimum and Logical Maximum
specify the range of values that the report can contain.
● The Report Size item indicates how many bits are in each
reported data item. In the example, each data item is eight
bits. The Report Count item indicates how many data
items the report contains. In the example, each report
contains two data items
● In the final item, the first byte specifies whether the report
is an Input report (81h), Output report (91h), or Feature
report (B1h). The second byte contains additional
information about the report data, such as whether the
values are relative or absolute.
An End Collection item (C0h) closes the Application Collection.

The main item type
A Main item defines or groups data items within a report descriptor.
Table below shows supported values for Input, Output, and Feature items. Each
item has a 1-byte prefix followed by 1 or 2 bytes that describe the report data.
Similar tables
are there for
output and
feature report
data.
Data | Constant. Data means that the contents of the item are modifiable (read/write).
Constant means the contents are not modifiable (read-only).
Array | Variable. This bit specifies whether the data reports the state of every control
(Variable) or just reports the states of controls that are asserted, or active (Array).
Reporting only the asserted controls results in a more compact report for devices such as
keyboards that have many controls (keys) but where only one or a few controls are
asserted at the same time.
Absolute | Relative. Absolute means that the value is based on a fixed origin. Relative
means that the data indicates the change from the last reading. A joystick normally reports
absolute data (the joystick’s current position), while a mouse reports relative data (how far
the mouse has moved since the last report).
Example from USB Lab
HID Specific Requests
That’s all !
Motion, Mechanisms &
Interfacing Motion Related Devices
➔ Linear
➔ Rotational
Linear motion can be generated using rotational motion using arrangement of gears.
Solenoid based magnetic devices can also be used to generate short range linear motion.
Linear Motor
Kind of Motors usually found in electronic systems
DC Motors
Useful when continuous rotation at high torque, high RPM is required.
Stepper Motors
Useful for applications where precise angular motion is required in equal size steps.
Comes in variety of torque and step angles.
Servo Motors
Feedback based motor control, used to design highly accurate movements.
DC Motor Interfacing
➔ Works on DC voltages with RPM proportional to applied voltage.
➔ Direction can be controlled by changing the polarity of applied voltage.
➔ Require high current to drive and act as inductive load.
DC Motor Interfacing
➔ Microcontroller pins can not supply current required to drive different variety of DC
motors. Depending on the RPM and torque of the motor it may require current of up
to 10s of Amps to drive.
➔ Special motor driver circuits are required to drive these motors.
➔ Driver can control direction and speed of the motor.
➔ How to design motor drivers?
Direction Control
Speed control using PWM
Stepper Motor
Translates electrical pulses into mechanical movement. Provides precise motion control
but no awareness of shaft position. Open loop control. You can control how many step you
want to rotate but you can not control the absolute angle of the shaft from where the
rotation will begin.
Servo Motor
➔ DC motor with shaft position feedback.
➔ Closed loop control.
Typical Servo control PWM pulse
Touch Panels
● Single touch (resistive) or multitouch (capacitive)
● Resistive touch screen are easy to interface. Can be driven using 2 or more
ADC channels.
● Capacitive touch panels are more complex to interface and often required
specialized driver ICs for integration into the system.
Proximity Touch Buttons

Numeric Keypad
Alphanumeric LCD Interfacing
Design Example - 1
Currency Note Acceptor +
Validator for vending machines
Design Example - 1
Design Breakdown
● Mechanical System Control

● Validation Algorithm
● Validation Hardware (Sensor + Computing)
● Communication
● Mechanical Enclosure Design
Design Example - 1
➔ Mechanical System Control
◆ To pull the notes into the detector
◆ Rotatory mechanism with friction wheels
◆ Pull out unacceptable / non validated notes.
◆ Store the notes into cash box.
Design Example - 1
Design Breakdown
How to identify the bank note?
How to ensure future compatibility?

Design Example - 1
Design Breakdown

Length, Width, Color?
What else?
How to ensure future compatibility?

Support end user Programmability!!!
Design Example - 1
Design Breakdown

Length, Width, Color?
What else?
Optical Profile !!!

Each currency note has security points on
it. Some are UV visible, IR visible or visible
to a certain frequency of light ray.
Design Example - 1
Design Breakdown

➔ How to obtain the optical profile?
➔ Put a pair of UV. IR, Visible light

sensors on top and bottom of acceptor
opening.
➔ Light Emitter on top and photosensitive

receiver on bottom.
Design Example - 1
Design Breakdown

User can do the optical profiling for a new type of
note and store it in the device memory as a
template. A user software interface is required
for that. And must be done a few times for
accuracy.
User will define the denomination in the software

and that value will be assigned to that optical
profile.
Now every time a currency note is inserted,

denomination with exact match to stored profile
will be communicated to the rest of the system.
Design Example - 1
Design Breakdown
● Communication
Device need to communicate to the host computer for programming

and configuration. PC supported protocols like Ethernet, USB, Wifi ,
Bluetooth should be used for that.
It also need to send the denomination value or rejection or notes to

the host microcontroller or embedded computer internal to the
machine. Board to board or IC to IC communication protocols should
be used for that. Example, RS232, SPI, IRDA, I2C etc.
Design Example - 2
SaReGaMa Carvaan like Music
Players
Design Example - 2 Customized MP3 players
Design Breakdown
● Human Interface Mechanisms

● Music Selection
● Tone Control and Audio Drive
Human Interface Mechanisms
● LCD display
● User Buttons
● Dial Wheel
● Remote Control IR
● Bluetooth App control
● LCD display - GPIO / I2C / SPI

● User Buttons - GPIO / EXINT
● Dial Wheel - Rotary Encoder / EXTINT
● Remote Control IR - EXTINT / TIMER
● Bluetooth App control - Bluetooth Audio Receiver
● Dial Wheel - Rotary Encoder / EXTINT

● Remote Control IR - EXTINT / TIMER

● Variety of standard IR remote protocols are there.
● RC5, NEC etc. (https://www.vishay.com/docs/80071/dataform.pdf)
● They rely on accurate timing measurement to
detect a particular input.
Design Breakdown
● Music Selection
There are MP3 playback ICs

that supports song seek via
title, folder etc.
Can also perform tone control,

EQ, Bass, Volume etc.
Design Breakdown
● Music Selection
Example - JQ6500
WTV020-SD etc.
Can store mp3 files into SD card /

flash and seek files via folder
names. Can provide play time,
number of files etc.
Design Breakdown
Example - JQ6500
SPK+ SPK- Can

provide direct drive
to small speakers.
For larger speakers

ADCL ADCR along
with external
amplifier is needed
Example - JQ6500
More design thinking projects?
Look around you!

Thank you!
Wish you all the best
M1 – Introduction to Embedded Systems
 Dedicated computer/processor based system built for
application/product
 System within a system
Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 2

 An embedded system is a special-purpose system -
the computer is completely encapsulated by the
device it controls
 Unlike a general-purpose computer- an embedded
system performs one or a few pre-defined tasks-
usually with very specific requirements
 Since the system is dedicated to specific tasks-
design engineers can optimize it, reducing the size
and cost of the product

 What are we designing ?
 What is the behavior ?
 What are the inputs?
 What are the outputs?
 What are the constraints ?

 Single functioned
 Complex Algorithms
 User Interface
 Tightly Constrained –Power, Cost, Memory
 Reactive and Real-Time
 Multi-rate

 Response
 Throughput
 Reliability – MTBF,MTTR
 Maintainability
 ISP & IAP
 Testability & Debug-ability

 Evolvability
 Portability
 Time-to-prototype and Market

M1 – Introduction to Embedded Systems
Requirement Analysis
Specifications
System Architecture
Hardware Design Software Design
Hardware Implementation Software Implementation
Hardware Testing Software Testing
System Integration
System Validation
Operation & Maintenance

 Ensuring Sound Specifications
 Formulating arch for system
 Partitioning H/W & S/W
 Iterative approach in H/W - S/W design

 Based on Complexity

 Small-Scale Embedded System
 Single 8/16 bit Microcontroller
 Less complex hardware and software
 Board level design
 Battery-operated

 Medium-Scale Embedded System
 16/32 bit Microcontroller/RISC,DSP/ASSP/IP
 May involve use of RTOS
 Distributed System – bus/networks
 Encryption/ Decryption/DCT
 Real-Time Scheduling Algorithms

 Sophisticated Embedded System
 Multi-processor system
 Safety Critical applications
 H/w S/w Co-design
 RTOS

FPGA/ASIC Memory
Sensors ADC CPU DAC Actuators
Diagnostic Human I/f

Port
Software
M1: Introduction to Embedded Systems
FPGA/ASIC Memory

Port
Software
 Processors
 Timers
 SCI
 Interrupt Controller
 Parallel Ports
 Memory
 Data
 Program
 Power supply
 Reset- Oscillator circuits
 Application Specific Circuits

 Software
 Application Specific Software – series of tasks
 Constraints- available memory, available processing power, power
dissipation limit
 RTOS
 Supervise application s/w
 Allocate resources
 Context switching
 Latencies – meet the deadlines
 Scalable

GPP
Performance
/ Power DSP, ASIPs Flexibility
Efficiency
FPGA
ASIC

 General Purpose Processor- µp
 Stream 1 – 68HCxx – Motorola
 Stream 2 – 80x86 – Intel
 Stream 3 – SPARC – Sun
 Stream 4 – Power PC – IBM
 Stream 5 - ARM

Goal: Multiply data in mem A with B- put it
back in A A
CISC: Mem
B
MUL A,B
C
RISC:
LDA R0,A
R0 R1
LDA R1,B
R2 R3
MUL R0,R1
STR A,R0
x,,+,-

Time = Time x cycles x Instructions
Program cycle Inst Program
RISC CISC

 Instruction:
 Fetch
 Decode
 Execute
1. ADD R2,R1,R3
2. SBR R2,R3,R2
3. STR R2,b

IF1 ID1 IE1 IF2 ID2 IE2 IF3 ID3 IE3
9 cycles
IF1 ID1 IE1
IF2 ID2 IE2
IF3 ID3 IE3
5 cycles
Pipeline Hazards
 c
 Processor has limited capability
 Enhanced i/o Functions
 Appln Specific units [DTMF/MODEM]
 Stream 1 – 68HC11xx, HC12xx, HC16xx
 Stream 2 - 8051
 Stream 3 – PIC16F84 – Microchip
 Stream 4 – ARM based Microcontrollers

 CISC or RISC ?
 µp or µc ?
 µc
 used when program is small/ less complex instructions
 located in internal memory
 µp
 used when program is large/ large no. of computations have to be
carried out
 RISC – used when intensive computations have to be done

 For a GPP to Qualify as an Embedded Processor
 Architecture must be optimized for RT op
 Support atomic operations
 Used for complex real –time functions

 RISC CPU + CISC special unit
 I960 – CPU+ Interrupt +DMA

Read value
Inc value
Write value

Read value
Suspend
Task1
Inc value
Read value
Inc value
Restore
Task1
Write value
Write value

 An operation during which a processor can simultaneously read a
location & write it in the same bus operation
 This prevents any other processor or I/O device from writing or
reading memory until the operation is complete
 Atomic implies indivisibility & irreducibility
 An atomic operation must be performed entirely or not performed
at all

 µp core + MAC
 Provides fast discrete –time signal processing streams
 Stream 1 - TMS 64xx – Texas
 Stream 2 – SHARC – AD
 Stream 3 – 5600xx – Motorola

 Specific tasks such as MPEG coding
 I2 chip – TCP/UDP – IP, ARP, Ethernet,10/100
 Faster than s/w solution using GPP

 RTOS-less solution
 IIM 700 - serial –to – Ethernet converter
 ASSP is used as an additional processing unit – instead of

embedded s/w - AES

 Speech signal compressing & coding
 Communication unit
 Keyboard display i/f
 Image Processing
 Multiple processors are used when a single processor cannot

meet the needs of different tasks

 Instruction Set
 Max- bits in operand (Size of the processor) – 8/16/32
 Clock frequency in MHz
 Processing speed in MIPS
 Dhrystone – uses a bench mark program
 1 MIPS = 1757 Dhrystones – VAX 11/780

FPGA/ASIC Memory

Port
Software
 RAM
 Internal/External
 Flash Memory/EEPROM
 External/Internal
 System Ports
 ROM/PROM
 Cache

Address
Data Memory
CPU
Inst/Data
Control

IADDR
IDATA Inst
Memory
ICONTROL
CPU
DADDR
DDATA Data
Memory
DCONTROL

Memory
RAM Hybrid ROM
EEPROM NVRAM Flash
SRAM DRAM EPROM PROM

 ROM
 EEPROM
DRAM with
 SRAM Address
clock
Page
 DRAM – FPM
Location
 SDRAM 64 k
64 pages
 SIMMs 1K
 DIMMs 0 002
 SODIMMs
 PCMIA

 Programs larger than memory
 Multiple processes in memory
 Multiple programs in memory
 Swapping
 Overlays
 Program – segment – main & overlay

Memory mapped I/O
Instructions
RAM
NVRAM
Stack
System

 Stuck at ‘0’
 Stuck at ‘1’
 Bridge
 Signature Analysis - ROM

Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are repeatedly required to run
programs- working set
Sequential locality of reference – spatial & temporal
Cache
Cntlr
Cache hit/miss
L2 Cache
L1 Cache
CPU

tmain 0.1µs
tL1 10 ns
 tmain – access time for main memory tL2 25 ns
 tL1 – access time for primary cache h1 90%
h2 7%
 h1 – hit ratio of primary cache tav =
 tL2 – access time for primary cache 0.9x 10ns
 h2 – hit ratio of secondary cache but not primary +0.07x25ns
+(1-0.9-0.07) x 0.1µs
 If system has only L1 cache
tav = 13.75 ns
 tav ?
 If system has L1 and L2 cache
 tav?
 tav = h1tL1 + (1-h1)tmain
 tav = h1tL1 + h2tL2 + (1-h1 -h2)tmain

Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are repeatedly required to run
programs- working set
Sequential locality of reference – spatial & temporal
Cache
Cntlr
Cache hit/miss
L2 Cache
L1 Cache
CPU

 Compulsory Miss/Cold Miss
 Capacity Miss
 Conflict Miss

 Direct Mapped
 Set Associative

MDR
Cache
MAR

MAIN
Page 0 Block 0 4 bytes
4k
Block1
4k
Block N Block 0 TAG
Block1
Block 0
Block1 Block N
Page 1
Block N
CACHE
Block 0
Page 2 No. of Blocks = 1K
Block1
Block N

Valid Tag Data
cache block 1
cache block 2
cache block 3
cache block 4
cache block 5
Address
Tag Index Offset
Dirty Bit Value

Hit
Write Through
Write Back

001 Address Data
100 000 0101
010 001 1111
101 010 0110
011 0000
100 1000
101 0001
110 1010
111 0100
00 -1 1000
-
01 0
-1 0001
1111
-
10 -0 0110
-
11 - -
Block Tag Data

Address Data
001
000 0101
100
001 1111
010
010 0000
101
011 0110
100 1000
101 0001
110 1010
111 0100
0 10
- 1000
- -01 -0000
1 -00 0101
- -10 -0001
Block S0 Tag S0 Data S1Tag S1Data
Set Associative Cache

 Cache
 64K x 32
 128 - 0.5 K blocks
 Two sets
 Main Memory
 256 K x 32
 512 Blocks - m
 64 Groups –n
 Group No m mod n

Block Group
0 64 128 384 448 0
1 65 129 385 449 1
2 66 130 386 450 2
63 127 192 447 511 63
0 1 2 3 4 5 6 7

Block
Tag
bank 1 bank 2 bank n
bank select
data

 Unified Cache
 Instruction/Data Cache
 Strong ARM – 16 KB, 32 way cache – each block is 32 bytes
 C5510 – 16KB instruction cache – 2 way

 Specific operation range
 Range of voltages
 5.0 ± 0.25 V
 3.3 ± 0.3
 2.0 ± 0.2
 1.5 ± 0.2 V
 Additionally EEPROM/ RS232 C – 12 V

 Usual pattern of Power Distribution
 2 pins of VDD + VSS
 Distributes power to all sections and reduces interference

 Ext I/O
 Timers
 Clock + Reset
 ADC
 VDD VSS AGnd, AREF, AIP
 Some Devices use charge pumps – no external power supply

 Propagation delay in gates α 1/V
 Power consumed in a CMOS circuit α V2
 An ES has to perform tasks continuously
 Power saving important
 Wait State/ Stop state
 2.5 mW /100 KHz

 Offers three low power modes of operation
 Run
 Normal Consumes Max Power
 Idle
 Saves power by stopping the CPU clock
 Sleep
 Turns off all units except – Power -0
 Keeps Power unit thro’ I/O power supply line
 Low speed clock available for power manager

400 mW
Run
10 µs 90 µs
10 µs
160ms
Idle Sleep
90 µs
50 mW 0.16 mW

 Clock source
 Crystal – highest stability – inspite of temp drifts
 Internal Ceramic Resonator – reasonable stability
 External IC based Oscillator – more driving power required

 Activated only for a few clock cycles
 System reset – CPU in synch with the reset of rest of the devices
 Sources of reset
 Power on reset
 Reset
 RC
 IC
 S/w Instruction /COP/CM

temp
40
Sense
10ms
t
Control

 RTC/Timers/Counters
 At least one counter in every ES

 Most Embedded Systems are Real-Time
 No. of Interrupts
 h/w
 event driven
 Priority
 Latency
 Default Priorities
 COP Watchdog
 External Interrupts
 Timer
 Serial I/f
 ADC

 ADC – multi-channel
 Vref + , Vref-
 DAC- PWM

 Parallel
 Serial
 Synchronous
 Asynchronous

 Synchronous
 SPI,USB
 Clock sent explicitly by Master – Slave
 Clock Signal
 Data modulated with Clock
 Synch Pulse
 Asynchronous
 Peer- to- Peer
 Clock Implicit

 Encoders
 Decoders
 Multiplexers
 PAL
 GAL
 PLDs, CPLD,
 FPGA
 Drivers

FPGA/ASIC Memory

Port
Software
FPGA/ASIC Memory

Port
Software
Appln Layer
RTOS
Hardware

 S/w particular to an application
 Processor of ES- handles inst/data
 Final stage ROM Image

 Boot-up program
 Stack/addr pointers
 Appln tasks
 ISR
 RTOS
 i/p data
 Vector address

 Configuring devices
 Device drivers for specific processors
 Small –Scale ES

Assembler
Machine code
ALP [any loc]
.obj
Bytes for Machine code
Library [MC] linked program [any loc]
Re-locating .exe
Linker
Addr [loader] Locater
Data Bytes Programmer
c
.s19/hex

 Device Types
 Physical e.g. Keyboard/Display
 Virtual e.g. File/ Pipe
 Each device has three components

 Control Registers
 Status Register H/w of
 Device Mechanism Device
 (I/p Buffer, O/p Buffer)

 s/w for controlling/ receiving/ sending data
 Made up of 3 functions
 Initializing Device
 Calling the ISR
 Resetting status bits after ISR
 If Underlying h/w as hidden as possible OS Functions

 API- then defines the h/w
 Device usable – when h/w in the system is changed

 Codes for detecting the presence of devices initializing and
testing
 Allocates address and checks for collision
 Address Allocation can be – pre-defined, relocatable

 Each Task has a distinct memory location
 Tasks – made up of one or more procedure
 Scheduling by OS - takes care of constraints
 RTOS kernel important func - schedule transitions of task
 Ready state - Running State
 Block state - Running State

 Tasks can enter into ready state at any time
 At a time only one task will be in running state
 Scheduling Algo
 RMS
 EDF
 LLF
 RTOS also controls inter-process communication

 How much h/w is required?
 How do we meet deadlines?
 How do we minimize power consumption?
 How do we design for upgradeability ?
 Does it work?
 Complex Testing
 Limited observability and controllability
 Restricted Development Environment

 Design method - Optimize performance
 Tools for ESD
 Split-up design work
 Process has to optimise
 Manufacturing cost
 Performance
 Power Consumption
 User I/f

Requirements Every step
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration

 Generally final step in Embedded System Design
Embedded System Design - RL1.3.1 © K.R.Anupama &

5
Meetha.V.Shenoy
 Embedding an GPP
 ARM7,ARM9 + Special Circuits

 Large no. of programmable gates
 Set of gates - Macro Cell
 Each cell - several i/p / several o/p
 All cells inter connect - Arrays
 Algo FT, IFT, LT, ILT, encryption/ decryption, DCT

RAM ROM EEPROM
ASIP
Timer/Int I/o I/f
FSK Mod
Charge Pump Antenna

M2: Small Scale Embedded System Design Example
DESIGN PROCESS
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration
EMBEDDED SYSTEM DESIGN – RL2.1.1 © K.R.ANUPAMA & MEETHA.V.SHENOY

2
MICROWAVE OVEN
8051RE2
EMBEDDED SYSTEM DESIGN – RL2.1.1 © K.R.ANUPAMA & MEETHA.V.SHENOY 3

MICROWAVE OVEN – USER REQUIREMENTS
Simple Microwave Oven

No Grill

USER REQUIREMENTS – OVEN OPERATION
Start/ Quick Start

Stop
Power Control
Time
Weight
Auto Cook Features

USER REQUIREMENTS – FRONT PANEL
Display Time / User Options
Oven Lock
Buttons
Weight
Power Level
Time
10 Min
1 Min
10 Sec
Auto Cook
Chilled
Beverage
Frozen
Start/Quick Start
Stop
USER REQUIREMENTS – INSIDE OVEN
Rotating Plate
Microwave Vents
Weight Sensor

SPECIFICATIONS – HOW DOES COOKING
IN MICROWAVE HAPPEN ??
Heats food - bombarding it with electromagnetic radiation in the
microwave spectrum
Causes polarized molecules in the food to rotate and build up thermal
energy in a process known as dielectric heating

SPECIFICATIONS – ORDER OF USER
INPUT
Any Auto Cook
Weight
Power Level
Time

SPECIFICATIONS –SETTING AUTO COOK
User can press any auto cook option
Beverage – Auto Cook Time 1.07 - 20 % Power Level
Frozen – Auto Cook Time 11.50 – 40 % Power Level
Chilled – Auto Cook Time 5.15 – 40% Power Level
Weight will always be auto weight

SPECIFICATIONS – SETTING WEIGHT
• Each press of button 100g button adds 100g in weight – maximum
weight cannot exceed 1.2 Kg
• Or Auto Weight button can be used – This option detects weight to
accuracy of 100g
• Default - Auto weight

SPECIFICATIONS – SETTING POWER LEVEL
 User can cook at 5 different Power levels: 100%, 80%, 60%, 40 %
20%
 Every press of the Power Button decrements the power level by 20 %
 1 Press - 100%; 2 Presses – 80% ; 3 Presses – 60%; 4 Presses – 40
% ; 5 Presses – 20%
 6 Presses – Brings the power level back to 100 %
 The Default power level is 100%

SPECIFICATIONS – SETTING TIME
Time is set as multiples of 10 Mins, 1Min, 10 Secs. For e.g. if the
cooking time is 12 Minutes and 40 secs- the 10 Minutes button has to
be pressed once, 1 Minute Button has to be pressed Twice and 10
seconds button has to be pressed four times

SPECIFICATIONS - DISPLAY
When user is setting power level or Time, the value being pressed
should be displayed, and when user presses the Start button, the
cooking process begins and the time left for cooking to complete is
displayed.

SPECIFICATIONS- LOCK & STOP
 Once the cooking begins the door gets locked and
should open only when cooking process is terminated.
 Internal Illumination is provided as long as door is closed
 User can terminate cooking anytime by pressing the
STOP button
 When Stop button is pressed once cooking is aborted,
timer is stopped, not cleared; cooking can be resumed
by pressing Start
 When stop is pressed twice, cooking is aborted and
timer is also cleared
 When cooking time elapses, a buzzer is sounded;
pressing the Stop Button stops the buzzer

SPECIFICATIONS – QUICK START
A Quick Start mode is available where timer or power need not be
set - just Start button needs to be pressed, the default power value
and auto weight is taken and time is set as 30 secs, for ever press of
the start button time is incremented by 30 seconds

SPECIFICATIONS- COOKING
Microwave Cooking Apparatus Consists of:
A high voltage power source- commonly a simple transformer - which
passes energy to the magnetron
A cavity magnetron- which converts high-voltage electric energy to
microwave radiation
A waveguide (to control the direction of the microwaves)

SPECIFICATIONS COOKING POWER
LEVELS
Transformer – Linear – Complete ON/OFF Switching
Power Level is varied by controlling the amount of time for which the
Magnetron is turned on.
Time of cooking is broken up into 10 sec slots, if power is 60% then
for 6 secs the microwave is on and rest of the 4 secs the microwave is
off

SPECIFICATIONS – MICROWAVE TURN
TABLE
The turntable in a microwave oven is driven by an AC single phase
synchronous motor which may start in either direction at random and
continues to travel in that direction until stopping.
The reason for using a turntable in a microwave oven is that the
microwave energy is not evenly distributed across the oven. The
turntable allows the food to receive an equal amount of energy by
turning across the uneven microwave field. The microwave energy is
turned to heat within the food.
It actually does not matter in which direction the turntable rotates in
order to evenly cook the food.
Standard Driver available to which a PWM of 16 KHz and 50 %
duty cycle is to be provided

DESIGN PROCESS
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2

MICROWAVE OVEN

No Grill

MODULAR DEVELOPMENT
 Module 1: User Interface – Key & Display
 Module 2: Timer – Start, Stop, Restart, Halt
 Module 3: Oven Functions – Magnetron, Turn Table , with Weight
Sensor
 Module4: Door Lock Control

MODULE 1
 Keys
 Auto cook -3 keys
 Weight/ Auto Weight
 Power Level
 Timer
 10 Min
 1 Min
 10 sec
 Display – 6 ; 7 –segment displays – Numeric Characters

MODULE 3
 Magnetron Control – ON & OFF according to power level
 Turn Table Control
 Weight Sensor ON/OFF

MODULE 4
 Relay Mechanism – Lock & Unlock Door – Electromagnetic Relay

ARCHITECTURE
User Key Magnetron –
Timer ON & OFF
& Display
Turn Table
Open/Close
Door

Timer CPU
Magnetron Control
Memory
Turn Table Control

Panel I/O
Door Control
Hardware Architecture

DESIGN PROCESS
Requirements
Specifications Top Down

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module1

MICROWAVE OVEN

No Grill

MODULAR DEVELOPMENT
 Module 1: User Interface – Key & Display
 Module 2: Timer – Start, Stop, Restart, Halt
 Module 3: Oven Functions – Magnetron, Turn Table , with Weight
Sensor
 Module4: Door Lock Control

MODULE 1
Keys Ports
 Start/Stop  INT0/INT1
 Auto cook -3 keys  P1.0- P1.2
 Weight -2  P1.3 – P1.4
 Power Level  P1.5
 Timer  P1.6
 10 Min
 P2.0- 2.2
 1 Min
 10 sec

KEYBOARD INTERFACE
P1.0
P1.1
P1.2
P1.3
P1.4
KBD
P1.5
IE1
P1.6
P1.7

KEYBOARD INTERFACE
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KLS7 KLS6 KLS5 KLS4 KLS3 KLS2 KLS1 KLS0

VCC
R
10
S1 A
MODULE 1 - DISPLAY
LT a
RBO
RBI
5V h
A
B
C Vcc Port4, Port 5, Port 2.4-2.7, Port 3.4,3.5
D
GND
7447

MICROWAVE OVEN
8051RE2 – Module 4

MODULE 4 - RELAY
Solid state relay – RS 275-310

Turning ON/OFF Lock
P3.6

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module3

MICROWAVE OVEN -INTERNALS
Rotating Plate
Microwave Vents
Weight Sensor

MODULE 3
 Turn Table
 !6 KHz – 50 % duty cycle

255-125+1
24MHz
THX
4 MHz
CCLK
6
32 KHz
TLX
3.125x10-5
TX
Enable TFX
(TCON)
TMOD
INTX
Gate’
TRx (TCON)
TIMER0
TMOD
C/T Gate M1 M0 C/T Gate M1 M0
TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

MODULE -
MAGNETRON
Solid state relay – RS 275-310
Turning ON/OFF Lock
P2.4

MODULE – WEIGHT SENSOR
Load Cell 0 -2Kg
Analog Output – Obtained via a Wheatstone Bridge
Output is calibrated to vary every 20mv for 100g
Connected to a serial RS232C - ADC

RS232 ADC
9600 - 115200 Baud

default 115200 Baud

RS232C
FE/SM0 SM1 SM2 REN TB8 RB8 T1 R1
BRR TBCK RBCK SPD SRC
BRL – 24 MHz - 243

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module2

(65536- RCAPH:L)
4MHz
R2CAPH:L = 20,000
2 MHz 45536 = b1e0H
FCLK
2
Counter 100 Hz
TX
Enable
T2CON
T2CON
T2CON

TIMER2
T2CON
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL’
T2MOD
T2OE DCEN

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – System Integration

4.0 0.0
4.3 0.7
4.4 1.0 BV
4.7 1.1 CH
5.0 1.2 FR
5.7 1.3 WT
1.4 AW
1.5 PL
3.7
1.6 T
Lock 3.6
1.7 TT
3.5
2.0 10M
3.4
2.1 1M
Start 3.3
2.2 10S
Stop 3.2
2.3
TXD 3.1 MAG
2.4
Load Cell RXD 3.0
2.7
X1
24M
X2
supply 8051RE2
INTERRUPTS
 INT0,INT1  INT0, INT1
 KBE  Timer2
 TIMER0  Timer0
 TIMER2  KBE
 SCI  SCI

INTERRUPTS
IE0
EA EC ET2 ES ET1 EX1 ET0 EX0
IE1
SCI2 SPI TWI KBD

INTERRUPTS
IPL0
IPH0

INTERRUPTS
IPL1
SCI2 SPI TWI KBD
IPL2
SCI2 SPI TWI KBD

INTERRUPTS
 INT0, INT1
 Timer2
 Timer0
 KBE
 SCI

DESIGN PROCESS
MICROWAVE OVEN
8051RE2 – Software

4.0 0.0
4.3 0.7
4.4 1.0 BV
4.7 1.1 CH
5.0 1.2 FR
5.7 1.3 WT
1.4 AW
1.5 PL
3.7
1.6 T
Lock 3.6
1.7 TT
3.5
2.0 10M
3.4
2.1 1M
Start 3.3
2.2 10S
Stop 3.2
2.3
TXD 3.1 MAG
2.4
Load Cell RXD 3.0
2.7
X1
24M
X2
supply 8051RE2
MAIN ROUTINE
 Initialise the following data parameters to the default value
Power Level 10
Weight 0
Auto Weight 1
Timer 0
10 MIN 0
1 MIN 0
10 SEC 0
Start 0
Stop 0
Cook Time 0
Count 100
Magnetron 0
PowerLevel’ 0
MAIN ROUTINE
 Enable Port 1 for Input with Interrupt with Low Select
 Enable INT0 and INT1
 Initialise Timer 2 for Auto Reload and enable interrupt but do not
start the timer
 WAI

KEY PRESS
 Interrupt on KBE
 Find if auto cook key is pressed
 If auto cook – load cook time, power level and weight for the auto
cook.
 If Weight – Increment parameter weight by 100
 If Auto weight – Enable RS232C of 8051 ED2
 Detect weight from load cell and write it into parameter weight.
 If Power level decrement Power level by 2 – if Power level equal to 0
reset to 10
 If Timer read port 2
 Calculate cook time

KEYPRESS - START
1. If Start is pressed and all parameters are at default set cook time
to 30 seconds close door and turn on magnetron.
2. If already cooking; on increment cook time by 30 seconds.
3. If start is pressed user defined parameters
 Start Timer 2
 Start timer 0 for auto reload – Initialise TL0, TH0 to 131
 Close Lock
 Start magnetron

KEYPRESS - STOP
 Stop magnetron
 Stop Timer 0
 If stop pressed once – hold cook time
 If stop pressed twice – clear cook time
 Release Lock

TIMER0
 Toggle Port 1.7

TIMER 2
Decrement count for second
If second is complete decrement cook time
If cook time zero stop magnetron and Timer0. Release Lock
If cook time has not reached zero – check if power level is 10
 If power level is not 10 check if magnetron is on
 If on decrement power level – if power level is zero stop magnetron
 If Magnetron is off – check power level‘ – decrement power level’ if
zero – turn on magnetron.

The ARM Cores
M3: Embedded Architectures- 1: RISC Architecture -
ARM
ARM- Characteristics
• Soft Processor – IP core processors
• 32- bit RISC
RL 3.1.1 Embedded System Design © K.R.Anupama &

• Load Store Architecture
• Fixed- Length 32-bit instructions
• 3-address instruction format
 Inst dst,src1,src2
Meetha.V.shenoy
• Register window
• Delayed branches
• Single cycle instructions
2
Register Windowing
Input
Registers

Local
Registers m( a+x(n!))
Output Input
Registers Registers
Local n!
Main
Registers Sub2
y = r*m( a+x(n!))
Output Input
Meetha.V.shenoy
Registers Registers
Sub1 Local
Registers
Output
Registers
3
• 32- bit RISC
• Pipelined – 3 stage

 Fetch
 Decode
 Execute
• PC – points to inst being fetched
• Von-Neumann Architecture
• Memory Access – only load/store/swap
• Data is aligned
Meetha.V.shenoy
• Two Instruction sets
 32-bit ARM
 16-bit THUMB – Instruction Compression
4
ARM Cores
ARMv4 ARMv5TE ARMv6 ARMv7-A

SIMD ARMv7-R
ARMv4T ARMv5TEJ Thumb2
Trust zone
Neon
E-Enhanced ARMv7-M
J-Jazelle DBX
Meetha.V.shenoy
next 5
•
•
•
•
SISD
MISD
SIMD
MIMD
Flynn’s Taxonomy

6
Meetha.V.shenoy
SISD

7
Meetha.V.shenoy
SIMD

8
Meetha.V.shenoy
A: I1 A,B
SIMD B: I1 C,D
Data Bus A

Data Bus A
ALU MAC Shifter ALU MAC Shifter
Meetha.V.shenoy
A B
9
MISD

Meetha.V.shenoy
10
MIMD
back

Meetha.V.shenoy
11
Features ARM7TDMI ARMcortexM3
Arch ARMv4T (Princeton) ARMv7M (Harvard)
Pipeline 3-stage 3-stage-branch

speculation
Interrupts IRQ/FIQ NMI+1-240 h/w
Int-Latency 24-42 24

Sleep None Integrated
Memory No Yes
Protection
Speed 0.95 DMIPS/MHz (A) 1.25 DMIPS/MHz
0.74 DMIPS/MHz (T)
Power 0.28mW/MHz 0.19mW/MHz
Meetha.V.shenoy
12
ARM- Programmer’s
Model & Operating
Modes
ARM
• 32- bit RISC
• Pipelined – 3 stage
 Fetch

 Decode
 Execute
• PC – points to inst being fetched

• Von-Neumann Architecture
• Memory Access – only load/store/swap
• Data is aligned
Meetha.V.shenoy
• Two Instruction sets
 32-bit ARM
 16-bit THUMB – Instruction Compression
• Bi-Endian
2
•
•
•
ARM
Thumb
Switching - BX
Operating States

3
Meetha.V.shenoy
Operating Modes
• 7 modes of operation
Privileged
• User Mode – default – executes applns
modes

• FIQ – Fast Interrupt
• Interrupt
• Supervisor mode – protected mode –OS
• Abort Mode
• System Mode – privileged user mode
Meetha.V.shenoy
• Undefined Mode
4
Registers
• ARM has 37 registers
 31 – GPRS, 6 SR
• Not all registers – available to programmers

• In ARM state – 16 GPR 1/2 SR are accessible
• In each of privileged modes – separate banks of registers
are accessible
• r0 - r15
• r15 – Program Counter –valid bits [31:2] –ARM state
• r14 – Link Register
Meetha.V.shenoy
• r13 – Stack Pointer
• CPSR – CCR/Flags
• In privileged modes – SPSR
5
r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6

r7 r7 r7 r7 r7 r7
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
r10 r10_fiq r10 r10 r10 r10
r11 r11_fiq r11 r11 r11 r11
r12 r12_fiq r12 r12 r12 r12
r13 r13_fiq r13_svc r13_abt r13_irq r13_und
Meetha.V.shenoy
r15(PC) r15(PC) r15(PC) r15(PC) r15(PC) r15(PC)
CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
User FIQ Supervisor Abort IRQ Undefined 6

r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6

r7 r7 r7 r7 r7 r7
r15(PC) r15(PC) r15(PC) r15(PC) r15(PC) r15(PC)
CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
User FIQ Supervisor Abort IRQ Undefined
Meetha.V.shenoy
Thumb State Registers
7
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6

r7 r7
r8
Mapping between r9
Thumb & ARM r10
r11
r12
r13 r13
Meetha.V.shenoy
r14 r14
r15(PC) r15(PC)
CPSR CPSR
SPSR SPSR
8
Program Status Registers
7 0
I F T M4 M3 M2 M1 M0
A3 A2
- A1- A0 - - - - E A
B3 B2 B1 B0
- GE1- GE0
GE3 GE2 - - GE3 GE2 GE1 GE0

31 N Z C V Q - - J
24
M4- M0 Mode
All insts in ARM state are
10000 User executed conditionally
10001 FIQ
10010 IRQ
Meetha.V.shenoy
10011 Supervisor
10111 Abort
11011 Undefined
11111 System 9
ARM- Instruction Set
-1
ARM
Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte

• Mode3: Load/Store half-word/signed byte
• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor
Meetha.V.shenoy
2
31-28 27 26 25 24-21 20 19-16 15-12 11-0
Cond 0 0 I opcode S Rn Rd Operand 2
ADD {condn} {S} Rd, Rn, <Oprnd2>

EQ #32 bit
NE Rm LSL #5bit
CS

Rm LSR #5bit
CC
Rm ASR #5bit
MI
Rm ROR #5bit
PL
Rm
VS
Rm LSL Rs
VC
HI Rm LSR Rs
Meetha.V.shenoy
LS Rm ASR Rs
GE Rm ROR Rs
LT
LE No Condition Taken as AL
AL 3
ADD R2, R2,#1
ADD R4,R5, R5, LSL #2
ADD R10,R15,#8
ADDS R4,R5,R6, LSR R7

R4 = 00 00 00 02 + 00 00 00 10
R2 = 20 02 10 55 R2 = 20 02 10 56
R10 = 00 A0 B1 08
R5 = 00 00 00 02
R4 = 00 00 00 02 + 00 00 00 08
R15 = 00 A0 B1 00
R6 = 00 00 00 02
Meetha.V.shenoy
R7 = 00 00 00 03
4
Arithmetic & Logical
Instructions
Arithmetic Logical

• ADD • AND
• ADC • ORR
• SUB • EOR
• SBC • BIC
• RSB
Meetha.V.shenoy
• RSC
5
31-28 27 26 25 24 23 22 21 20 19- 15- 11-0
16 12
Cond 0 1 1 P U B W L Rn Rd Addr mode
LDR/STR {condn} {B} {T} Rn, Rd, <Addr Mode>

EQ
NE
CS

+/-
CC
MI size
PL
0 x post
VS
1 0 pre
VC
1 1 Pre+W
HI
Meetha.V.shenoy
LS
GE
LT
LE
AL 6
LDR R1, [R0]
Address in R0
LDR R8, [R3, #4]
Address = [R3]
LDR R12, [R13, #-4] R3 = R3 +4
STR R2, [R1, #0x100] Address = [R13]
R13 = R13 -4
LDRB R5, [R9]
Address = [R1]
STRB R4, [R10, #0x200] R1 = R1 +0100H

Address in R9
Address = [R10]
R10 = R10 +0200H
Meetha.V.shenoy
7
Address = [R1]
LDR R11, [R1, R2] R1 = R1 + R2
STRB R10, [R7, -R4] Address = [R7]
R7 = R7 + R4
LDR R11, [R3, R5, LSL #2]
Address = [R13]
LDR R1, [R0, #4]! R13 = R13 + R5 * 4
LDR R3, [R9], #4 R0 = R0 +4
Address = [R0]+4
STR R2, [R5], #8

LDR R0, [R1], R2 Address = [R9]+4
STRB R7, [R6, #-1]!
Meetha.V.shenoy
8
Transfer btwn memory & reg
LDR/LDRB/LDRH/LDRSH
STR/STRB/STRH/STRSH
ADR

Meetha.V.shenoy
9
ARM- Instruction Set
– 2 & Pipelining
ARM
Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte

• Mode3: Load/Store half-word/signed byte
• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor
Meetha.V.shenoy
2
x = (a+b)-c;
ADR r4,a
LDR r0,[r4]

ADR r4,b
LDR r1,[r4]
ADD r3,r0,r1
ADR r4,c
LDR r2,[r4]
SUB r3,r3,r2
Meetha.V.shenoy
ADR r4,x
STR r3,[r4]
3
31-28 27 26 25 24 23 22 21 20 19-16 15-0
Cond 1 0 0 P U 0 W L Rn Reg List
LDM/STM {condn} <addr mode> Rn, <Reg List>
Examples

LDMIA R0, {R5 - R8}
STMDA R1!, {R2, R5, R7 - R9, R11}
STMFD R13!, {R2-R9}
STMEA R13!, {R2-R9}
Meetha.V.shenoy
Addressing Mode – IA, IB, DA, DB, FD, FA, EA,ED
4
0x204 20304050
0x200 21314151
0x1fc 22324252
0x1f8 23334353
0x1f4 24344454

0x1f0 25354555
0x1ec
0x1e8
0x1e4
0x1e0
Meetha.V.shenoy
Stack Empty
Fully Descending
Descending
5
0x204
0x200
0x1fc
0x1f8
0x1f4
0x1f0 24344454

0x1ec 23334353
0x1e8 22324252
0x1e4 21314151
0x1e0 20304050
Meetha.V.shenoy
Stack Empty
Fully Ascending
Ascending
6
Branch instructions
conditional branch forwards /backwards up to 32MB
branch /jump can also be generated by writing a value to R15
31-28 27 26 25 24 23-0
Cond 1 0 1 L 24- immediate value

B/BL {condn} ,<Immediate Value>
Examples
B label
BCC label
BEQ label
MOV PC, #0
Meetha.V.shenoy
BL func
MOV PC, LR
LDR PC, #func
7
Pipeline in ARM
• 3 stages of pipeline
• Fetch-Decode-Execute

• Normal Instruction require three clock cycles –
inst exec latency
• 1 cycle/instruction does not hold good for all insts
• Multiple load instruction
• Several cycles during execution phase
Meetha.V.shenoy
8
add r0,r1,r2 fetch decode execute
sub r2,r3,r6 fetch decode execute
cmp r2,r4 fetch decode execute

Meetha.V.shenoy
9
add r0, r1,r2 fetch decode execute
ldmia r0,{r1,r3} fetch decode execute execute
add r0,r2,r3 fetch decode
sub r0,r0,r7 fetch

Data stall
Meetha.V.shenoy
10
stall
bne nxt fetch decode execute execute execute

sub r2,r3,r6 fetch decode execute
sub r1,r2,r5 fetch decode

nxt: add r0,r2,#3 fetch decode execute
2 holes
Meetha.V.shenoy
11
bne nxt fetch decode execute
nop fetch decode execute
nop fetch decode execute
sub r2,r3,r6

-----
nxt: add r0,r2,#3 fetch decode execute
Delayed Branching
Meetha.V.shenoy
12
ARM- Exceptions
ARM
ARM-Exceptions
• Handled by entering into different operating modes
• Exception Entry

 Preserves the address of next instruction into LR
 Copies the CPSR into SPSR
 CPSR modes bits set to appropriate operating mode
Meetha.V.shenoy
2
Interrupts/ Address Entry F I
Exceptions Mode
Reset 0x 0000 0000 Supervisor 1 1
Undefined 0x 0000 0004 Undefined U 1
SWI 0x 0000 0008 Supervisor U 1

Pre-fetch 0x 0000 000C Abort U 1
Abort
Data Abort 0x 0000 0010 Abort U 1
IRQ 0x 0000 0018 IRQ U 1
FIQ 0x 0000 001C FIQ 1 1
Meetha.V.shenoy
3
Main Program
ADR r4,a
LDR r0,[r4]
LDR r4,[r2] FIQ
LDR r1,[r4]
ADD r3,r0,r1
r15 r14_fiq
CPSR SPSR_fiq

CPSR (Mode) - FIQ
Enters FIQ
r14_fiq - 4 r15
SPSR_fiq CPSR
Meetha.V.shenoy
4
r0
r1
r2
r3
r4
r5
r6

r7
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12 LR_FIQ r12_fiq
r13 r13_fiq
Meetha.V.shenoy
r14 back-up
r14_fiq
r15(PC)
CPSR
back-up
SPSR_FIQ SPSR_fiq
User FIQ 5
FIQ
• nFIQ pin –low
• Why FIQ – all high regs are banked – reduces int

latencies
• ARM checks for low level at the end of each instruction
• FIQ – disabled in privileged mode – F -1
Meetha.V.shenoy
6
FIQ - actions
• Actions Taken on FIQ
• R14_fiq = Address of next inst to be executed +4

• SPSR_fiq = CPSR
• CPSR[4:0] = FIQ mode
• T bit = 0 F=1 I=1
• PC = Address of FIQ ISR
Meetha.V.shenoy
• Exit From FIQ
• SUBS PC, R14,#4
7
IRQ
• nIRQ pin –low

• Actions Taken on IRQ
• R14_irq = Address of next inst to be executed +4
• SPSR_irq = CPSR
• CPSR[4:0] = IRQ mode
• T bit = 0 I=1
• PC = Address of IRQ ISR
Meetha.V.shenoy
• Exit From IRQ
• SUBS PC, R14,#4
8
Supervisor Mode
• Entry-SWI
• Actions Taken on SWI

• R14_svc = Address of SWI + 4
• SPSR_svc = CPSR
• CPSR[4:0] = Supervisor mode
• T bit = 0 I=1
• PC = Address of Supervisor Routine
Meetha.V.shenoy
• Exit From Supervisor
• MOVS PC, R14
9
Undefined
• Inst than cannot be handled by ARM/co-processor
• Actions Taken on Undefined

• R14_und = Address of Instruction + 4
• SPSR_und = CPSR
• CPSR[4:0] = Undefined mode
• T bit = 0 I=1
• PC = Address of Undefined Routine
Meetha.V.shenoy
• Exit From Undefined
• MOVS PC, R14
10
ARM- Exceptions -
Abort
ARM
ARM-Exceptions
• handled by entering into different operating modes
• Exception Entry

 Preserves the address of next instruction into LR
 Copies the CPSR into SPSR
 CPSR modes bits set to appropriate operating mode
Meetha.V.shenoy
2
Abort- Prefetch
• Current inst cannot be completed
• ABORT i/p checks for abort at the end of every memory

access
• Allows implementation of demand-paged virtual

memory system
• Proc is allowed to generate arbitrary address
• Data at address not available - MMU generates abort
Meetha.V.shenoy
3
1
5
4
3
2
0
7
4
2
i
i
i
v
v
v
Page Table
7
2
0
F
A
Physical Memory
A
D
E
B
Disk
F
C

4
Meetha.V.shenoy
40 ADR R1,A A: ADR R1,A
ADR R2,B
44 ADR R2,B
LDR R0,[R1]
48 LDR R0,[R1]
LDR R1,[R2]
4C LDR R1,[R2]
B: ADD R2,R1,R0
50 ADR R7,D
ADD R2,R1,R0
ADR R1,C

54 R8,E
ADR R1,C
STR R2,[R1]
58 LDR R11,[R7]
STR R2,[R1] Abort
MMU
Meetha.V.shenoy
Physical Memory
5
Abort handler
• Works out the causes of abort
• Load the inst that caused the abort

• Check whether the inst modifies – base reg
• Determine the offset from inst
• Restore base reg - original value - applying opposite

offset
• Two Types of Abort

 Pre-fetch
Meetha.V.shenoy
 Data
6
Pre-fetch Abort
• ARM marks it
• Takes action only when it enters into execute pipeline

stage
• If inst is not executed – fails condition code/branch-

abort does not take place
• Abort handler takes over in case of abort
• Exits to original state and inst is tried again
Meetha.V.shenoy
7
Prefetch Abort
• Actions Taken on Pre-fetch Abort
• R14_abt = Address of aborted inst +4

• SPSR_abt = CPSR
• CPSR[4:0] = Abort mode
• T bit = 0 I=1
• PC = Address of Abort ISR
Meetha.V.shenoy
• Exit From Pre-fetch Abort
• SUBS PC, R14,#4
8
Data Abort
• Action depends on inst type
• LDR/STR- restores base reg

• SWP
 read access – suppress write access and write to destn reg
 Write access – supress write to destn reg
• LDM/STM
• Abort in middle of data t/f –rest of regs not affected
• If base reg was part of reg to be loaded – returned to
Meetha.V.shenoy
original state
9
00 FE
00 ADR R0,0
CA
04 ADR R1,B DE
08 LDMIA R0!, {R1,R2,R3} 45
0C ADD R1,R1,R2 04 11
78
0F ADD R3,R1,R3 12

13
34
R1 – 45DECAFE
R0 – 0000 0004 AA
5A
R2 –00000000
R2- 5A341278
R0 –00000000
R0- 0000 0008
Meetha.V.shenoy
MMU
Abort
10
How does it distinguish between
Pre-fetch & Data Abort?
• Pre-fetch abort occurs in fetch stage
• Data abort occurs in execute state

Meetha.V.shenoy
11
Data Abort
• Actions Taken on Data Abort
• R14_abt = Address of inst that caused abort +8

• SPSR_abt = CPSR
• CPSR[4:0] = Abort mode
• T bit = 0 I=1
• PC = Address of Abort ISR
Meetha.V.shenoy
• Exit From Data Abort
• SUBS PC, R14,#8
12
AMBA
M4: Embedded Architectures- 2: ARM based LPC23xx
Some Common Bus Terminologies
• Bundle
• Handshake
• Timing Diagram
• Changing States
• Stable States
• Timing Constraints
• Wait states
• Burst transfer
• Disconnected/Split Transfers
RL4.1.1 Embedded System Design © K.R.Anupama &

2
Meetha.V.shenoy
Option Performance Cost
Bus width Separate Multiplexing

addr/data
Data width Wider Narrower
Transfer Size Multiple words Single word
Bus Master Multiple Single
Split Yes No
Transaction
Clocking Synch Asynch

3
Meetha.V.shenoy
Low-Speed
CPU Device
Low Speed Bus
Bridge
High Speed Bus
Low-Speed
Device
High-Speed
Memory
Device

4
Meetha.V.shenoy
1000
CPU Speed
100
10
DRAM Speed
1975 1980 1985 1990 1995 2000 2005 2010

UART
ARM
Bridge
AHB/ASB APB
Timer
Memory DMAC

6
Meetha.V.shenoy
INTRODUCTION TO LPC
23XX
Features - LPC23xx series - ARM-
based microcontrollers
• 10/100 Ethernet MAC
• USB 2.0 Full Speed interface
• 4 UARTs
• 2 CAN channels
• 1 SPI interface
• 2Synchronous Serial Ports (SSP)
• 3 I2C interfaces
• 1 I2S interface,
• 1 MiniBus

2
Meetha.V.shenoy
Members of the 23xx family
• LPC2364/65/66/67/68
• LPC2377/78
• LPC2387
• LPC2388

3
Meetha.V.shenoy
Features
• ARM7TDMI-S processor, running at up to 72 MHz
• FCCO = (2 × M × FIN) / N
• Up to 512 kB on-chip Flash Program Memory with ISP& IAP
• Upto 64 kB of SRAM on the ARM local bus - high performance CPU

access
• 16 kB Static RAM for Ethernet i/f
• 8 kB Static RAM for USB i/f

4
Meetha.V.shenoy
Clk Generation
Main Osc
PLL cpu
Int RC mux mux clk div
RTC clksrcreg

5
Meetha.V.shenoy
Low Power Mode of operation
• Single 3.3 V power supply (3.0 V to 3.6 V).
• 3 Three reduced power modes:
• Idle
• Sleep
• Power-down
• Done using PCON
• 4 external
interrupt inputs- In addition every PORT0/2 pin can be
configured as an edge sensing interrupt
• Any of the ext ints along with USB,CAN or Ethernet BOD, RTC can
wake up the processor from power down

6
Meetha.V.shenoy
Brown out Detection
3.3
2.9
2.65
Int
Reset
Enable - PCON

7
Meetha.V.shenoy
RC Osc
GPIO ARM7TDMI Vec Int Cntlr
SRAM Flash PLL
P0,P1,
P2,P3, AHB2 AHB1
P4 AHB Bridge AHB Bridge
16 KB Ethern 8 KB USB+4k
SRAM et AHB-AHB Bridge SRAM SRAM+DMA
MAC+
DMA GP DMAC
AHB-APB Bridge
2k Battery RAM RTC

EINT0-3
P0,P2 External Int I2S
Timer (0-3) SPI,SSP0
6x
PWM1 PWM1 SSP1
P0,P1
Legacy GPIO SD/MMC
8x AD
ADC UART0,2,3
AOUT
DAC UART1
Watch Dog Timer CAN1,2
System control RL4.1.2 Embedded System Design © K.R.Anupama & I2C

8
Meetha.V.shenoy
AHB peripherals(256M)
APB peripherals(256M)
Reserved(512M)
Reserved
Bank(1) 64kb
Bank(0) 64kb
8K Boot Block
Reserved
Memory Map
16kb Ethernet RAM
8kb USB RAM
Reserved
32K SRAM
Reserved Memory
Space
512RL4.1.2
KBEmbedded
NV Memory
System Design © K.R.Anupama &
Meetha.V.shenoy
9
LPC 23XX- GPIO
Features
• GPIO PORT0 & PORT1
• accessible
• group of reg providing enhanced features accelerated port access
• legacy group of reg
• PORT2/3/4 are accessed as fast ports only.
• Accelerated GPIO functions
• GPIO regs are relocated to the ARM local bus so that the fastest possible
I/O timing can be achieved

2
Meetha.V.shenoy
Features
Mask reg allow treating sets of port bits as a group
All GPIO registers are byte and half-word addressable
Entire port value can be written in one instruction
Bit-level set and clear
Direction control of individual bits
D31 D30 D29 D28 D27 D26 D25 D24

D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0

3
Meetha.V.shenoy
Interrupt generating digital ports
• PORT0 & PORT2 provide an interrupt for each port pin
• Each int can be programmed to generate an int on a rising edge, a
falling edge, or both
• Asynch
• GPIO0 & GPIO2 ints share the same VIC slot with EI3

4
Meetha.V.shenoy
Total pins -112
• Port 2
• Pin 14-31 NA
• Port 3
• Pin 8-22 NA
• Pin 27-31 NA
• Port 4
• Pin 16-23 NA
• Pin 26-27 NA

5
Meetha.V.shenoy
Port 0 & 1 How do they func ?
• Use as GPIO/ Fast I/O - SCS Reg Bit 0 – GPIOM
• Pin Select Registers
• Every pin has alternate functions
• 00 – GPIO P0.0
RD
TXD3 PIN0.0
SDA
• Pin Mode Registers – Select Pull-up/Pull down

6
Meetha.V.shenoy
How to use GPIO?
• Regs – Legacy –Only for port0/1
• IOxPIN
• IOxSET
• IOxCLR
• IOxDIR

7
Meetha.V.shenoy
How to use FGPIO?
FIOxPIN
FIOxPIN0-3
FIOxPINL / FIOxPINU
FIOxSET
FIOxSET-3
FIOxSETL / FIOxSETU
FIOxCLR
FIOxCLR-3
FIOxCLR / FIOxCLRU
FIOxDIR
FIOxDIR0-3
FIOxDIRL / FIOxDIRU
FIOxMASK
FIOxMASK0-3
FIOxMASKL / FIOxMASKU

8
Meetha.V.shenoy
Input with Interrupt
• IntEnR
• IntEnF
• IntStatR
• IntStatF
• IntClr
• IntStatus
Int2S Int0S

9
Meetha.V.shenoy
LPC 23XX- TIMER
Features
• Four Timer/Counters
• 4 channels/Timer
• A minimum of 2 capture i/ps & 2 Match o/ps are pinned out for all 4
timers
• Choice of several pins for each
• 32 bit Timer/Counter with programmable 32 bit Prescaler
• Counter / Timer operation

2
Meetha.V.shenoy
Example
• Program LPC 23xx to count the no. of objects crossing a particular
point within a period of 1 second. Also find the time interval
between two objects

3
Meetha.V.shenoy
INPUT CAPTURE

4
Meetha.V.shenoy
Channel 0 CAP0.0
Channel 1 CAP0.1
Channel 2
Channel 3
Timer 0

5
Meetha.V.shenoy
Input Capture EDGB:EDGA
CLK
32-bit
000A
0005
Counter
H PT
Edge
Capture
000A
0005HReg Detector
CF
CI Interrupt Logic
Interrupt Request

6
Meetha.V.shenoy
Program for Input Capture
Turn on Timer 0/1/2/3
PCONP
Bit1 :PCTIM0
Enabled on Reset
Bit2 :PCTIM1
Bit22 :PCTIM2
Bit23 :PCTIM3
PINSEL Registers

7
Meetha.V.shenoy
Input Capture 0.0 P1.26 AltF3, P3.23 AltF2
Input Capture 0.1 P1.27 AltF3, P3.24 AltF2
Input Capture 1.0 P1.18 AltF3




8
Meetha.V.shenoy
Clock for Timer 0/1/2/3
PCLK Selection Register 0 0 0 CCLK/4
Bit2-3 :PCLK_TIMER0
0 1 CCLK
Bit4-5 :PCLK_TIMER1
PCLK Selection Register 1 1 0 CCLK/2
Bit12-13 :PCLK_TIMER2
1 1 CCLK/8
Bit14-15 :PCLK_TIMER3

9
Meetha.V.shenoy
Pre Scale for Timer 0/1/2/3
TxPR
TxPC
TxC

10
Meetha.V.shenoy
Select Clock for Timer/Counter
Counter Control Register for Timer 0/1/2/3
CCxR
CIS1 CIS0 CM1 CMO

CAP x.0 0 0 0 0 Rising Edge
PCLK
CAP x.1 1 0 0 1 Rising edge

CAP
Resv 0 1 1 0 Falling edge

CAP
Resv 1 1 1 1 Both edges

CAP
11
Meetha.V.shenoy
PCLK SEL 0:1 CPR
1/2/4/8 Pre-Scale+1
CCLK
Counter
CAP
CCR

12
Meetha.V.shenoy
Capture Registers for Timer 0/1/2/3
TxCCR
CA1I CAP1FE CAP1RE CA0I CAP0FE CAP0RE
Program Interrupt Unit

13
Meetha.V.shenoy
TxCR
TR TE

14
Meetha.V.shenoy
TxIR
IC3 IC2 IC1 IC0 IM3 IM2 IM1 IM0
Ack Interrupt

15
Meetha.V.shenoy
Capture Registers for Timer 0/1/2/3
TxCR0-TxCR3

16
Meetha.V.shenoy
OUTPUT COMPARE

17
Meetha.V.shenoy
Features
4 32 bit match registers that allow
Continuous op with optional int generation on match
Stop timer on match with optional int generation
Reset timer on match with optional int generation
Up to 4 external o/ps corresponding to match regs
Set low on match
Set high on match
Toggle on match
Do nothing on match
18
Meetha.V.shenoy
Output Compare
Reset/Continue/Stop
on Match
CLK
32-bit
0005
0004
0003
0002
0000
0001
counter
OL0
OL1 PT
PTx
32-bit comparator CF Logic
Match
0005Reg
CI INT
Logic

Interrupt
Meetha.V.shenoy
19
Output Compare 0.0 P1.28 AltF3, P3.25 AltF2
Output Compare 1.0 P1.22 AltF3



Output Compare 3.1 P0.11 AltF3Design © K.R.Anupama &
RL4.1.4 Embedded System
20
Meetha.V.shenoy
Program for Output Compare
Match Registers for Timer 0/1/2/3
TxMR0-TxMR3
TxMCR
MR2S MR2R MR2I MR1S MR1R MR1I MR0S MR0R MR0I
MR3S MR3R MR3I

21
Meetha.V.shenoy
Program for Output Compare
External Match Registers for Timer 0/1/2/3
TxEMCR
EMC1 EMC0 EM3 EM2 EM1 EMO
EMC3 EMC2

22
Meetha.V.shenoy
Program LPC 23xx to count the no. of
objects crossing a particular point within a
period of 1 second. Also find the time
interval between two objects.

23
Meetha.V.shenoy
LPC 23XX- WATCH DOG
Feed Sequence WDTC
Feed Ok
WDFEED
Feed Error
RTC Osc 32-bit down cntr
PCLK 4
Internal
RC OSC
WD CLK Sel Shadow bit
WDINT WDTOF WDRESET WDEN

Int
Reset
Feed Sequence FFH
Feed Ok
AA
55HH
Feed Error
RTC Osc 00
FFH
PCLK 4
Internal
RC OSC
WD CLK Sel Shadow bit
WDINT
1 WDTOF
1 WDRESET WDEN
Int
Reset
CLK Select
PCLKSELREG0 0:1
WDCLKSELECT Reg WDSEL
WDTCReg
Minimum value = 256
Minimum Time out – TwCLK*4*256

Maximum Time out – TwCLK*4*232
WDMOD
WDTV Reg
LPC 23XX- VIC
Features
• Vectored Int Cntlr
• Mapped to AHB addrs space for fast access
• Supports 32 vectored IRQ int
• 16 programmable int priority levels

• Fixed h/w priority within each programmable priority level
• H/w priority level masking
• Any i/o can be assigned as an FIQ int
• s/w int generation

2
Meetha.V.shenoy
FIQ
32 Int . Vectored
sources Int Controller
.
.
IRQ

3
Meetha.V.shenoy
Interrupt Sources
Bit 31 30 29 28 27 26 25 24
Src I2S I2C2 UART3 UART2 Timer3 Timer2 GPDMA SD/MMC
Bit 23 22 21 20 19 18 17 16
Src CAN1&2 USB Ether BOD I2C1 AD0 EINT3 EINT2
Bit 15 14 13 12 11 10 9 8
Src EINT1 EINT0 RTC PLL SSP1 SPI1 / I2C0 PWM1

SSP0
Bit 7 6 5 4 3 2 1 0
Src UART1 UART0 Timer1 Timer0 ARM ARM - WDT

Core1 Core0

4
Meetha.V.shenoy
Soft Int Clr Int Enable Clr
FIQ
Soft Int Int Enable FIQ Status
Int 0-31
IRQ Status
Raw Int
Int Select

5
Meetha.V.shenoy
H/w & S/w Mask
bits
s/w priority mask
IRQ
A Status 0 Latch VIRQ0
S/w priority Mask0 Priorit Priority
H/w priority Mask0 y Mask Logic IRQ
Logic
Vector Priority0 VIRQ1
Vector Address 0
Vector
Select
IRQ
Status 1
Vect Addr
or
Addr
IRQ ess
Status 31
6
Meetha.V.shenoy
VIC Interrupt Selection Registers
(32-bit Reg)
Classifies each Interrupt as IRQ/FIQ

7
Meetha.V.shenoy
Software Interrupt Register
VICSoftInt -32 –bit Register
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
ORED
Peripheral interrupts
VICSoftIntClr
Clearing S/w Interrupt bits
VICIntEnClr
8
Meetha.V.shenoy
Vector Address Registers
VICVR0 – VICVR31

9
Meetha.V.shenoy
Software Priority Mask Register
VIC Protection Enable Register

1 Bit – To indicate whether the int register can be
accessed in User Mode

10
Meetha.V.shenoy
Vector Priority Registers
VICVPR0 – VICVPR31
P3 P2 P1 P0

11
Meetha.V.shenoy
Vector Enable Register
Each Bit for enabling each channel

12
Meetha.V.shenoy
Status registers
IRQ Status Register
FIQ Status Register
VICRawIntr

13
Meetha.V.shenoy
Status registers
VIC Address Register

14
Meetha.V.shenoy
External Interrupt
Registers
EXTINT
EXTMOD
EXT POL
EINT3 EINT2 EINT1 EINT0

15
Meetha.V.shenoy
LPC 23XX- ADC /DAC
ADC

2
Meetha.V.shenoy
Features
• 10 bit successive approximation
• I/p multiplexing among 6 pins or 8 pins.
• Power down mode
• Measurement range 0 to 3 V
• 10 bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple i/ps
• Optional conversion on transition on i/p pin or Timer Match signal
• Individual result regs for each A/D channel

3
Meetha.V.shenoy
VREF
AD0
AD1
AD2
AD3 ADC
AD4
AD5
AD6 VDDA
AD7 VSSA
ADC clock
10-bit data

4
Meetha.V.shenoy
PCONP: 8
PCLKSEL0: 25-24
PINSEL

5
Meetha.V.shenoy
AD0INTEN
ADGINTEN
ADINEN
Program Interrupt Unit

6
Meetha.V.shenoy
AD0CR
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
CLKDIV
PDN CLKS Burst
EDGE START
000 No Start ADC clock < 4.5 MHz
001 SOC
010 SOC – EINT0
011 SOC-CAP0.1
100 SOC-MAT0.1
101 SOC-MAT0.3
110 SOC-MAT1.0
111 SOC-MAT1.1
7
Meetha.V.shenoy
AD0STAT
CHD7 CHD6 CHD5 CHD4 CHD3 CHD2 CHD1 CHD0
CHO7 CHO6 CHO5 CHO4 CHO3 CHO2 CHO1 CHO0
ADINT

8
Meetha.V.shenoy
10-bit data 15:6
AD0DR0:AD0DR7 30-Overrun
AD0GDR 31- Done
26:24- CH No.
Ack Interrupt

9
Meetha.V.shenoy
DAC

10
Meetha.V.shenoy
Features
10 bit DAC
Buffered output
Power down mode
Selectable speed vs. power
VREF
AOUT
VDDA
VSSA
10-bit data
11
Meetha.V.shenoy
DAC always on
PCLKSEL0 23:22
PINSEL1, PINMODE1

12
Meetha.V.shenoy
DACR
DATA
BIAS
0 - 1s
1 - 2.5s

13
Meetha.V.shenoy
LPC 23XX- SPI & SSP
SPI

2
Meetha.V.shenoy
Features
• Synchronous, Serial, Full Duplex Communication
• SPI master or slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 to 16 bits per transfer
• Single Master/Slave

3
Meetha.V.shenoy
MOSI
MISO
Master
Slave SPI
SPI
SCLK
SS
PCONP: 8 (On reset enabled)

PCLKSEL0 :16,17
4
Meetha.V.shenoy
SCLK CPOL =0
SCLK
CPOL =1
SS
CPHA =0
MOSI
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
CPHA =1
MOSI
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

5
Meetha.V.shenoy
Master Slave
SPCR SPCR
SPIE LSBF M CPOL CPHA BITE SPIE LSBF M CPOL CPHA BITE
1 0 1 0 0 0 1 0 0 0 0 0
BITS BITS
X X X X X X X X
2 1
3
SPDR
MOSI
Shift Reg Shift Reg
SPICLK(0:7) 1 SPDR 3
SPSR
SPF WCOL ROVR MODF ABRT
SPSR
SPICLK(0:7)
SPIR
SPIF SPF WCOL ROVR MODF ABRT
4 SPIR
6
2
Meetha.V.shenoy
SPIF
PCONP: 12 – Default on
PCLKSEL0: 16-17
PINSEL

7
Meetha.V.shenoy
S0SPCCR – even no.  8
SPCR
SPDR

8
Meetha.V.shenoy
SPIR
SPSR

9
Meetha.V.shenoy
SSP 0/1

10
Meetha.V.shenoy
Features
• Synchronous Serial Communication
• Master or slave operation
• 8 frame FIFOs for both transmit and receive
• 4 to 16 bits frame
• DMA transfers supported by GPDMA
• 2 I/f SSP0,SSP1
• Supports three formats-TI,SPI,Microwire

11
Meetha.V.shenoy
MOSI/DX/SO
MISO/DR/SI
Master
Slave SPI
SPI
SCLK/CLK/SK
CS/FS/SS
PCONP: 10,21 (On reset enabled)

PCLKSEL1 :10,11 PCLKSEL0 :20,21
12
Meetha.V.shenoy
SCLK
FS
DX/DR
Bit4 Bit3 Bit2 Bit1
FS
DX/DR Bit4 Bit3 Bit2 Bit1 Bit4 Bit3
TI Format

13
Meetha.V.shenoy
SK
SS
SO
Microwire Format

14
Meetha.V.shenoy
SSPxCR0
CPHA CPOL FRF DSS
SCR
SSPxCR1
SOD MS SSPE LBM
SSPxCPR 7:1 (2-254 – even)

CLK = PCLK/SSPxCPRx[SCR+1]
SSPxDR
15
Meetha.V.shenoy
SSPxSR
BSY RNF RFE TNF TFE

16
Meetha.V.shenoy
SSPxRISR
TXRIS RXRIS RTRIS RORRIS

SSPxIMR
TXIM RXIM RTIM RORIM
SSPxMISR INT
TXMIS RXMIS RTMIS RORMIS
SSPxICR
RTIC RORIC

17
Meetha.V.shenoy
SSPxDMACR
TDMAE RDMAE

18
Meetha.V.shenoy
LPC 2
23XX- I C 2
&I S
I C–
2 0/1/2

2
Meetha.V.shenoy
Features
• Moderate Speed 100kbps- 400 kbps
• Serial Data Line (SDL) /Serial Clock Line (SCL)
• Synchronous
• Master/Slave PE 2
(Slave)
PE 1 Data
(Master)
Clock
PE 3
(Slave)

3
Meetha.V.shenoy
Ack bit Stop bit
start bit R/W Ack bit
address data
D0 D1 – D7 D8 D9 D10 – D17 D18D19

4
Meetha.V.shenoy
Features
• Configured as Master, Slave, Master/Slave
• Arbitration
betwn simultaneously txing masters without
Programmable clock
• Bidirectional data t/f between masters & slaves
• Serial clock synch allows devices with different bit rates to
communicate via one serial bus
• Serial clock synch- can be used as handshake mechanism to
suspend & resume t/f
• SDA0/1/2- SCL0/1/2

5
Meetha.V.shenoy
I2C Types of Data T/f
• Master transmitter to a slave receiver
• 1st byte txed by master - slave addr
• Next follows a no. of data bytes
• Slave returns an ack bit after each rxed byte

6
Meetha.V.shenoy
I2C Data Type
• Slave transmitter to a master receiver
• 1st byte – slave address - txed by the master
• Slave returns ack bit
• Next follows data bytes txed by the slave to master
• Master returns ack bit after all received bytes other than the last byte
• Last received byte, a “not ack” is returned
• Master generates SCL , START & STOP conds
• T/f ends with STOP condn /repeated START condn

7
Meetha.V.shenoy
I2C Operating Modes
Appln – I2C may operate - master/ slave/ both
Master Mode
Slave
Bus No
free?
Yes
Master
Yes Arbit
lost?
No
8
Meetha.V.shenoy
I2C Operating Modes
Appln – I2C may operate - master/ slave/ both
Slave Mode
Addr
=mine
Yes
?
No
No Addr
=bcas
t?
Yes
Int
9
Meetha.V.shenoy
Master Transmission
S Slave addr 0 A Data A A P
Master Receive
S Slave addr 1 A Data A A P
Master Receive  Master Transmit

S S addr 1 A Data A A S S addr 0 A Data A A P

10
Meetha.V.shenoy
Arbitration Loss
Master Tx
Master Rx
Wired AND Logic –SDA - Arbitration
Wired AND Logic- SCL - Synchronization

11
Meetha.V.shenoy
M1
M2
Bus
Arbitration Loss
Arbitration
12
Meetha.V.shenoy
CL1
CL2
SCL
Synchronization Process

13
Meetha.V.shenoy
Address Register 8
I2ADR
I/p Comparator
SDA Filter
O/p
Stage Shift Register ACK I2DAT
APB Bus
Bit cntr/ PCLK
I/p Timing
SCL Filter Arbt/
Sync &
O/p
Stage
Control INTR
Serial
Clock
Generato
I2CONSET
r
I2CONCLR Control/CLK Reg 16
I2SCH:I2SCL
Status Status Decoder 8
Reg RL4.2.4 Embedded System Design © K.R.Anupama &
Meetha.V.shenoy I2STAT 14
2
IS

15
Meetha.V.shenoy
Features
• Std commn i/f for digital audio appns
• Defines a 3-wire serial bus - data, clock, word select
• One master- always the master
• Separate transmit & receive channel

• Capable of handling 8, 16, and 32 bit word sizes
• Mono and stereo audio data supported

16
Meetha.V.shenoy
Features
• Sampling frequency range 16 - 96 kHz. (16, 22.05, 32, 44.1, 48, 96
kHz)
• 2 -8 byte FIFO data buffers
• Generates int req when buffer levels cross boundary

• Two DMA requests
• Controls include reset, stop & mute options
• Supports NXP Inter IC Audio format for 8, 16 & 32 bits audio data
both for stereo & mono modes

17
Meetha.V.shenoy
SCK
WS
SD
Left channel data Right channel data
TX_SCK, TX_WS, TX_SD

RX_SCK, RX_WS,RX_SD
18
Meetha.V.shenoy
SD
SCK Audio o/p
Tx Unit WS
SD
SCK Audio i/p
WS
Rx Unit

19
Meetha.V.shenoy
Data Formats
Mono -8 bit
data4 data3 data2 data1
Stereo-8bit
data2r data2l data1l data1r
Mono-16bit
Stereo-16bit
data2r data2l data1l data1r
Mono-32bit
20
Meetha.V.shenoy
Digital Audio Output/Input Register
ws_sel reset stop mono Size
Mute WS_Size
TxFIFO Reg
RxFIFO Reg
TxCLK Reg/ RxCLK Reg – 0:9
Sample Rate – 48 KHz
Then value of clock - 48KHz x 2x16

21
Meetha.V.shenoy
LPC 23XX- CAN
Features
• Serial commn protocol
• Efficiently supports distributed real-time control with a very high

level of security
• CAN has been subdivided into different layers
◊ (CAN-) object layer
◊ (CAN-) transfer layer
◊ physical layer

2
Meetha.V.shenoy
Appln Layer
Object Layer
•Message Filtering
•Message & Status Handling
Transport Layer
•Fault Confinement
•Error Detection & Signaling
•Message Validation
•Ack
•Arbitration
•Message Framing
•T/f rate & Timing
Physical Layer
•Signal level & Bit Repsn
•Tx medium
3
Meetha.V.shenoy
Message Transfer is done in frames
Frame Types
Data Frame
Remote Frame
Error Frame
Overload Frame
Frames are separated by IFS
Bit – Dominant/Recessive

4
Meetha.V.shenoy
Frame Format ACK EOF
Arbitration Control Data CRC
CRC
SOF de-limiter

5
Meetha.V.shenoy
Arbitration Field
I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 RTR
Control Field
R R DL3 DL2 DL1 DL0

6
Meetha.V.shenoy
CAN Features in LPC 23xx
• 2 CAN controllers & buses
• Supports 11-bit/29-bit identifier
• Double Rx Buffer & Triple Tx Buffer
• Programmable Error Warning Limit & Error Counters with
read/write access
• Arbitration Lost Capture
• Error Code Capture with detailed bit position
• Listen Only Mode
• Reception of "own" messages
• RD1/2,TD1/2

7
Meetha.V.shenoy
CAN core
APB Bus I/f mngmnt block
Logic Error
mngmnt RXD
Logic CAN Txr
VIC
TXD
Tx Buffers Bit
Common 1,2,3 Timing
Status Logic
Regs
Bit
Acceptan Rx Buffers stream
ce Filter 1,2 processor

8
Meetha.V.shenoy
LPC 23XX- USB
Features
• Bus between a host system & a no. of interconnected systems
• Designed
• Allow peripherals to be connected using a single standardized i/f

socket
• To improve plug-and-play capabilities - hot swapping
• Providing power to low-consumption devices
• Many devices to be used without requiring manufacturer specific
individual device drivers to be installed

2
Meetha.V.shenoy
USB Signalling
• USB supports four data rates
• Low Speed - (1.1, 2.0) rate of 1.5 Mbit/s
• Mostly used for Human Interface Devices (HID) such as keyboards, mice &
joysticks
• Full Speed (1.1, 2.0) rate of 12 Mbit/s
• Full Speed was the fastest rate before the USB 2.0 specification
• Many devices fall back to Full Speed
• Hi-Speed (2.0) rate of 480 Mbit/s
• Super-Speed (3.0) rate of 4.8 Gbit/s

• Due to the inclusion of a fiber optic link that works with traditional copper
connectors

3
Meetha.V.shenoy
USB Signals
• USB cable has four lines
• + 5V
• Gnd
• Two for data (D+, D-)
• NRZI – NRZ with zero stuffing when there are more than 6 one’s
• Sync field – sync tx and rx clocks

4
Meetha.V.shenoy
USB Interface
Device Host Device

Root Hub
hub2 hub1 Device
Device Device Device hub3
Device Device

5
Meetha.V.shenoy
Device Classes
• Devices can be full-custom devices requiring a full-custom device
driver or may belong to a device class
• These classes defn an expected behavior in terms of device & i/f
descriptors so that the same device driver may be used
• An OS is supposed to implement all device classes so as to provide
generic drivers for any USB device

6
Meetha.V.shenoy
Class Usage Description Examples
Use class info in the
00h Device -
I/f Descriptors
01h I/f Audio speaker, microphone, sound card
02h Both Communications ethernet adapter, modem
Human Interface
03h I/f keyboard, mouse
Device (HID)
05h
06h
07h I/f Printer
USB flash drive, memory card reader,
08h I/f Mass Storage
digital audio player
09h Device USB hub
(This class is used together with class 02h -
0Ah I/f Commn-Data
Communications and CDC Control.)
0Bh I/f Smart Card

7
Meetha.V.shenoy
Class Usage Description Examples
0Dh I/f Content Security
0Eh I/f Video webcam
DCh Both Diagnostic Device
E0h I/f Wireless Controller Wi-Fi adapter, Bluetooth adapter
EFh Both Miscellaneous ActiveSync device
FEh I/f Application Specific IrDA Bridge
FFh Both Vendor Specific

8
Meetha.V.shenoy
Device Recognition
3.3 V
Host/ D+ D+
Device
Hub D- D-
Full Speed

9
Meetha.V.shenoy
Device Recognition
3.3 V
Host/ D+ D+
Device
Hub D- D-
Low Speed

10
Meetha.V.shenoy
Data Transfer types
• Controlled data transfer
• Bulk data transfer
• Interrupt driven data transfer
• Iso- synchronous data transfer

11
Meetha.V.shenoy
USB transaction consists of three
packets
• Token packet (header)
• Optional Data packet (info)
• Status packet (ack)
• SOF – 11-bit frame sent every 1ms ± 500ns FS /125µ 0.0625 µs
Sync PID ADDR ENDP CRC5 EOP

Sync PID Data CRC16 EOP
Sync PID EOP

Sync PID Frame No. CRC5 EOP

12
Meetha.V.shenoy
Pipes & Endpoints
• A single phy USB device may consist of several logical sub-devices
• Referred to as device functions
• Each individual device may provide several functions
Host Controller
Logic Pipes
End Points
Devices
13
Meetha.V.shenoy
Pipes & Endpoints
• A USB device can have - 32 active pipes- 16 into/ 16 out of host
cntlr
• Endpoint can t/f data in one direction only- each pipe is uni-
directional
• Endpoints grouped into i/fs - each i/f is associated with a single
device func
• Exception - endpoint zero- used for device config - not associated
with any i/f

14
Meetha.V.shenoy
USB Functions
• Bus is Host Centric- host may send data to end-point buffer any
time
• Device cannot write to the bus – so writes to end-point buffer and
waits for bus to read
• Host cntlr polls the bus for traffic - in a round-robin fashion- no USB
device can t/f data on the bus without an explicit req from the host
cntlr
• Pipes have a set of params defn
• Type of data t/f
• Dir of data flow
• Max pkts/buffer size

15
Meetha.V.shenoy
V Bus
DMA USB
Bus master I/f Connect
Engine
USB ATX
EP_RAM D+
AHB Bus
Serial I/f
Reg I/f Access
Engine D-
Control
USB Up
LED
EP_RAM
(4k)

16
Meetha.V.shenoy
LPC 23XX- GPDMA
Features
• Two DMA channels
• GPDMA provides 16 peripheral DMA req lines

• Single DMA and burst DMA request signals
• DMA burst size is set by programming the GPDMA
• Memory-to-memory, memory-to-peripheral, peripheral-to-

memory & peripheral-to-peripheral t/f s
• Scatter or gather DMA is supported through the use of linked lists

2
Meetha.V.shenoy
Features
• Hardware DMA channel priority
• AHB slave DMA programming i/f
• AHB bus master for transferring data
• 32 bit AHB master bus width

• Incrementing /non-incrementing addring for src & dst
• Internal four-word FIFO /channel

3
Meetha.V.shenoy
Features
• Supports 8, 16, and 32 bit wide transactions
• Big-endian and little-endian support
• Int to the processor can be generated on a DMA completion/ DMA
error
• Int masking
• Raw int status

4
Meetha.V.shenoy
DMA Block Diagram
AHB Control
AHB Bus Slave Reg &
I/f Logic
DMA req DMA AHB

Channel
req/ Master AHB Bus
DMA res Reg &
res I/f
Logic
I/f
DMA int Int

Req

5
Meetha.V.shenoy
Programming a DMA channel
• Choose a free DMA ch with the priority reqd
• Clear
any pending int on the ch to be used by writing to the
DMACIntTCClr Register /DMACIntErrClr
• Src addr - DMACCxSrcAddr Reg
• Destn addr - DMACCxDestAddr Reg
• Write the addr of the next Linked List Item (LLI) into the
DMACCxLLI Reg - if the t/f consists of a single packet of data then
0 must be written into this reg

6
Meetha.V.shenoy
RC Osc
GPIO ARM7TDMI Vec Int Cntlr
SRAM Flash PLL
P0,P1,
P2,P3, AHB2 AHB1
P4 AHB Bridge AHB Bridge
16 KB Ethern 8 KB USB+4k
SRAM et AHB-AHB Bridge SRAM SRAM+DMA
MAC+
DMA GP DMAC
AHB-APB Bridge
2k Battery RAM RTC

EINT0-3
P0,P2 External Int I2S
Timer (0-3) SPI,SSP0
6x
PWM1 PWM1 SSP1
P0,P1
Legacy GPIO SD/MMC
8x AD
ADC UART0,2,3
AOUT
DAC UART1
Watch Dog Timer CAN1,2
System control RL4.3.3 Embedded System Design © K.R.Anupama & I2C

7
Meetha.V.shenoy
System Modeling -
UML
M7: Embedded Software Design
UML
 Modeling System Behavior & Relationships
 Static Behavior
 Outside view of system
 System Interaction
 Dynamic Behavior
 Concurrency
 Persistence
 Thread of control
 System behavior whiles task execute
 Interaction between system
Common UML Diagrams
 Class
 Use Case
 Component
 Communication
 State Chart
 Timing
 Sequence
 Activity
 Object
 Package
 Composite Structure
 Interaction
 Deployment
Use Cases
 Outside view of the system
 Public i/f of module/system
 What is system behavior as user sees it
 Main components of system
 User interaction with main components
 Can be hierarchical
Actors
 Executes use case
 Supporting Actor
 Active
 Passive
Use Cases
How system can be used
Various Behaviors of the system
Encapsulates event/actions that must occur to implement intended behavior
of the system
Stated and expresses from point of view of user
All services offered to the user
Each use case has a textual component fully describing it
Very powerful tool during requirement phase
Use case diagram has to be as simple as possible
University Reg Program – use
cases
Student
Prof Info
Info
Create
Course Info Course
Catalog
Use Case - Relationships
General Browse
<<extends>> <<extends>>
Specialized Search
Use Case - Relationships
case2 Give Price
<<uses> <<uses>
Locate
case1
Book
Actors & Use Cases
Gives
money
ATM Customer
Data Acquisition System
 Measures Voltage
 Measure Temp
 Data – Initial Analysis done and sent for further processing
 Analysis result sent back
UML
Measure
Volts
Data
Analysis
Measure Data
Actor0 Temp Processing
Textual Description – Measure Volts
User
Select measure volts mode
Select measurement range
System
If range specified
Configure to specified gain
Make Measurement
If in range – display results
If exceed range – display largest value & flash display
If auto range
Configure to midrange gain
Make Measurements
If In range- display result
If above/below range – adjust gain repeat measurement
Textual Description
 Normal Activity
 Exceptional Conditions
Class Diagram
 Help Indentify/Formulate – Modules
 Describe object/modules
 Relationship between objects
 Public i/f to object
 Properties – op that instances of the object can perform
 Indentifies any constraints the appln imposes on these op
Class Diagram
Object Name
- Properties
+ Operations()
Class Relationships
 Parent – Child/ Inheritance/Generalization
 Interface
 Wrapper around one piece of functionality
 Allows to present diff set of capabilities to public view
 Containment
 One object made up of several others
 Whole part relationship
 Aggregation
Owned module may be used out of aggregation
 Composition
Ownership is very strong
Inheritance/Generalization
Driver
+port number: unsigned char
+buffer address: int
+status: unsigned char
+ Read(): Boolean
+Write(): Boolean
Serial Parallel
+ Read(): Boolean + Read(): Boolean

+Write(): Boolean +Write(): Boolean
Interface
Voltmeter
<<interface>>
Measure Pressure
+ Measure(): Float
+ Measure(): Float
-Covert (): Float
Containment -Aggregation
Statistical Analysis 0-n Algorithms Algorithm
+buffer: int
Containment -Composition
Schedule Interval
1-n
Dynamic Modeling
 Recognizing inter-module interaction
 Ensuring proper order of task execution
 Understanding what activities can be done in parallel
 Schedule alternate paths of execution
 Indentify tasks that are active and what are not
Interaction Diagram
Interaction among tasks – messages
 Events
 Rendezvous
 Message
Receipt of a message results in action
Actions
 Call & Return
 Create & Destroy
 Send
Call & Return
:Task i :Task j
action()
return()
Create & Destroy
:Task i :Task j
<<create>>
<<destroy>>
Send
:Task i :Task j
action()
Sequence Diagrams
 Objects
 Lifeline
 Focus of Control
 Messages
Sequence Diagram – Time Interval
Measurement
Measur Get Exec
Convert Display
e Task Attrib Meas
measure ()
get range ()
range()
get edge ()
edge()
send data ()
result()
send data ()
formatted data()
Display data ()
ok()
done()
Fork& Join
Parent
Child 0
Child 2
Child 1
Parent
Branch & Merge
Activity 0
When:[guard codn]
Activity 1
Activity 2
Activity 3
Activity 4
Activity Diagram
Activity 0
Activity 1
When:[guard codn]
Activity 5 Activity 3
Activity 2
Activity 4
Activity 6
Activity 7
Activity 8
Measure
Time
Get range
Get edge
Open meas
window
Close meas Update
window Display
Read count
Min value convert Max value
Flash Flash
State Chart Diagrams
Same as state diagrams with some extensions
Transitions
event
State2 State7
State2
State2 State7
Guard Condition
State2 State9
Event [guard]
State10
Composite States
Substate0 Substate1
Event [guard]
Substate 3 Substate 2
astate
Concurrent States
astate
State8 State9
State10 State11
Control & Data Graphs
Program Model - CDFG
Data Operations
Control Operations
a b c d e
w=a+b
x= a–c
+ + -
y= x+d x1
x= a+c +
z= y+e x2 w y
Single assignment form
w = a+b
x1 = a – c +
y = x1 + d
x2 = a + c z
z = y+e
if (codn1)
basic_block1();
else
basic_block2(); T basic_block1()
cond1
basic_block3();
switch(test1){
case c1:basic_block4();break; F
case c2:basic_block5();break; basic_block2()
case c3:basic_block6();break;
}
basic_block3()
test1
basic_block5() basic_block6() basic_block7()

UML Example
System design
Digital Counter
System Description
 Measure
 Frequency
 Period
 Time Interval
 Events
 Measurement Range
 3 for signals
 2 for events
 Remote Operation support should be provided

for future expansion
 Can work on battery/power-line
System Inputs
 Frequency
 High 50.000 MHz
 Mid 50.000KHz
 Low 100.000Hz
 Period
 High 1.0000ms
 Mid 10.000ms
 Low 1.000 sec
System Inputs
Time Interval
 High 1.0000ms
 Mid 10.00ms
 Low 1.000sec
Events
 Fast 200 events/min
 Slow 2000 events/hr
All inputs
 Digital
 0-4.5 V DC
Resolutions
 Frequency
 1 MHz
 1 KHz
 10 Hz
 Period/Time Interval
  0.001ms
  0.01ms
  0.001s
User Interface
MHz/ ms/min
KHz Start
Hz/sec/hr
Freq Period Intervl Events

Fr Range Stop
Pwr Reset
Use Case – Local Mode
Measure
Freq
Measure
Period
Measure
Interval
Count
User Events
Reset
Use Case – Remote Mode
Measure
Freq
Measure
Period
Measure
Interval
Count
User Events
Reset
Measure Frequency
 Frequency measured continuously
 Start Trigger
 Exceeds allowable maximum – flash maximum
 Exceeds allowable minimum – display ‘0’ and flash
 Within bounds – display
Use Case – Measure Freq
Select
Mode
Select
Range
Select
User Trigger
Textual Description – Measure Freq
User
Select measure freq mode
Select measurement range
Select measurement Trigger
System
Configure to specified range and trigger
Make Measurement
If in range – display results
If below range – display zero value & flash display
Measure Period
 Period measured continuously
 Start Trigger
Use Case – Measure Period
Select
Mode
Select
Range
Select
User Trigger
Measure Interval
 Interval measured within a window
 Start Trigger
 Stop Trigger
Use Case – Measure Interval
Select
Mode
Select
Range
Select Start
User Trigger
Select Stop
Trigger
Count Events
 Event done continuously
 Start Trigger
Use Case – Count Events
Select
Mode
Select
Range
Select Edge
User
Other Specifications
 Automatic Power Line Voltage Regulation
 Temperature Staability 0 -50C
 < 6 x10-6
 Aging Rate
 90 day
 < 3x10-8
 6 month
 <6 x10-7
 1 year
 <25 x10-6
Other Specifications
Safety : IEC-1010
MTBF : 10,000 hrs
Measure Frequency
Get range
Get edge
Open meas
window
Close meas
window Update Display
Read count
Flash Flash
Measure Period
Get range
Get edge
Open meas window
Close meas window Update Display
Read count
Flash Flash
Measure Interval
Get range
Get start edge
Open meas window
Get stop edge

Update Display
Close meas window
Read count
Min value Max value

convert
Flash Flash
Compilers,
Assemblers &
Debuggers
Embedded Code
Rich functionality
Run at the required rate
Fit within a certain amount of memory
Meet power consumption requirements
Robust, Reliable and Maintainable
Source
code
Pre-
processor Compiler Assembler
Object
code
Linker
.s19/ hex
Loader
Preprocessor
Builds Temporary File – Translation unit
Header File - # include
# define, #ndef
Unresolved external references
Compiler
Cross compiler
Important to understand how a high-level language program

instructions
Control inst seq that handle ints
Control placement of data and insts in mem
Applns are performance sensitive
Compilation = translation + optimization

Compiler
Statement Translation
a*b + 5*(c - d)
Flow Graph for Statement
Translation
a b c d
1 - 2
* w 5
x
* 3
y
4 +
z
Register Allocation
w=a+b
x= c+w
y= c+d
Registers – not sufficient -spill

a
b
c
d
w
x
y
1 2 3
w=a+b
x= c+w
y= c+d
Color Graphs
Smallest no. of colors to represent all variables
a b
w
d
x
c
y
w=a+b
x= c+w
y= c+d
Compiler
Optimization Tech
Dead Code Elimination
Procedure Inlining
Expression Simplification
a * b + a*c = a*(b+c)
Instruction Selection
Scheduling
Choose the order in which

instructions are executed
Scheduling problems  Resource
Table
Instructions can be scheduled to
avoid pipeline bubbles
Pipeline bubbles  Software
Pipelining
Loop Transformations
Loop Unrolling
Loop Fusion
Loop Distribution
Array Padding
for (j = 0; j<M; j++)
for (i =0; i<N; i++)
a[j][i] = a[j][i]+ b[j][i]*c
Compiler support
Inst i Inst i+1 Latency
FP ALU op FP ALU op 3
FP ALU op Store 2
Load double FP ALU op 1
Load double Store double 0
Example Code
for (i = 1000; i > 0; i = i-1) Loop: L.D F0,0(R1)
x[i] = x[i] + s; ADD.D F4,F0,F2
S.D F4, 0(R1)
DADDUI R1,R1,# -8
BNE R1,R2,Loop
Delays
Loop: L.D F0,0(R1) 1
stall 2
ADD.D F4,F0,F2 3
stall 4
stall 5
S.D F4,0(R1) 6
DADDUI R1,R1,#-8 7
stall 8
BNE R1,R2,Loop 9
stall 10
Scheduled Program
Clock cycle issued
loop: L.D F0, 0(R1) 1
Stall 2
ADD.D F4,F0,F2 3
Stall 4
Stall 5
S.D F4, 0(R1) 6 OLD
DADDUI R1,R1,#-8 7
Stall 8
BNE R1,R2, loop 9
Stall 10
Clock cycle issued

loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3 NEW
2-cycle Stall 4
latency BNE R1,R2, loop 5
S.D F4, 8(R1) 6
Compiler Tasks
Clock cycle issued
loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3
Stall 4
BNE R1,R2, loop 5
S.D F4, 8(R1) 6
 OK to reorder DADDUI and ADD.D

 OK to reorder S.D and BNE
 OK to reorder DADDUI and S.D, but requires
0(R1)  8(R1)
Loop Overhead
Clock cycle issued
loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3
Stall 4
BNE R1,R2, loop 5
S.D F4, 8(R1) 6
 6 is the minimum due to dependencies & pipeline latencies

 Actual work of the loop is just 3 instructions:
 L.D, ADD.D, S.D
 Other instructions are loop overhead:
 DADDUI, BNE
Loop unrolling
Loop: L.D F0,0(R1)
ADD.D F4,F0,F2
S.D F4,0(R1)
L.D F0,-8(R1)
ADD.D F4,F0,F2
S.D F4,-8(R1)
L.D F0,-16(R1)
ADD.D F4,F0,F2
S.D F4,-16(R1)
L.D F0,-24(R1)
ADD.D F4,F0,F2
S.D F4,-24(R1)
DADDUI R1,R1,#-32
BNE R1,R2,Loop
Loop unrolling
Loop: L.D F0,0(R1)
L.D F6,-8(R1)
L.D F10,-16(R1)
L.D F14,-24(R1)
ADD.D F4,F0,F2
ADD.D F8,F6,F2
ADD.D F12,F10,F2
ADD.D F16,F14,F2
S.D F4,0(R1)
S.D F8,-8(R1)
DADDUI R1,R1,#-32
S.D F12,16(R1)
BNE R1,R2,Loop
S.D F16,8(R1)
Compiler Tasks for
Unrolled Scheduled Version
OK to move S.D after DADDUI and BNE if S.D offset is adjusted

Determine that unrolling is useful because loop iterations are
independent
Use different registers to avoid name hazards
Eliminate extra test and branch instructions and adjust iteration
code
OK to move L.D and S.D instructions in unrolled code (requires
analyzing memory addresses)
Keep all the real dependencies, but reorder to avoid stalls
Compilers
 Programs need not always be

compiled then executed
 On –the fly translation
 Interpreters
 JIT
 Interpreters- translates program
statements one at a time
 JIT comes in between Interpreters and
compilers
Assembler
LABEL1 1000
Creates Symbol Table LABEL2 1008
Program Location Counter (PLC) LABEL3 1010
ORG $1000
PLC -1000
LABEL1 ADR r4,c
PLC -1004 LDR r0,[r4]
LABEL2 ADR r4,b
LDR r1,[r4]
LABEL3 SUB r0,r0,r1
Linker
Allows program to be stitched together from smaller pieces
Lib - preassembled
Labels
defined and used in same file
defined and used in different files
Entry Point
External Reference
Proceeds in two steps
absolute address of start of each obj file
specified by user
merges all symbol tables relative address – absolute address
DLL
Makefiles
Files to compile
Standard and custom lib
Name of executable
Whether debug info
hw:hw.o
gcc hw.o –o hw
hw.o:hw.c
gcc –c hw.c
Debug & Release Builds
Debugging tool
Larger Executable
Tasks & Task Management
RL8.1.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy 1
 Embedded program – collection of Firmware Modules
 Firmware Module executes – Process/Task
 Control ensures that task execution satisfies –set of

timing constraints - RT
RL8.1.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy 2

 Multi –tasking/ Concurrent Processing
 Tasks
 Exchange/share data
 Synchronization
 Sharing resources (processor)
 Schedule

 Process created – allocated resources by OS
 Process stack
 Registers including PC
 I/O ports
 Ntk connections
 File Descriptors
 Resources are not generally shared

Current Value of PC, Present Value of
data in memory/ registers

Duration btwn when task enters to
termination

 Scheduling  Scheduling
 Execution  Execution
 Threads within a  Resource Ownership
process share
resources

 Threads are easier to create than processes since they
don't require a separate address space
 Multithreading requires careful programming since
threads share data structures that should only be
modified by one thread at a time
 Unlike threads- processes don't share the same
address space
 Threads are considered lightweight because they use
far less resources than processes
 Processes are independent of each other- Threads
share the same address space are interdependent, so
caution must be taken so that different threads don't
step on each other.
 A process can consist of multiple threads

Single process – Single process –
single thread multi thread
Multiple process – Multiple process –

single thread multi thread
9
RL8.1.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy
 Interleaved
 Blocked
 Simultaneous

 Address space allocated to a single process is
limited
 Thread/process – access memory out of
range –stopped
 Privilege levels
 Processor Modes of operation
 Access violation – exception
 Process – spawn child process – resources ??

 Factors
 Info
 Place/places – source
 Identifiers – named variables, pointer variables
 Control & sync of actions – movement of info
 Shared variables
 Messages
 Buses

Global Variables
 Adv – Backup
 Disadv – two tasks may try to modify simultaneously

Shared Buffer
Producer T0 T1 Consumer
Bool Full()
Bool Empty()

Ping pong Buffer /Shared Double
B0
T0 T1
B1
16
Ring Buffers T0 - head
T1- Tail

MailBox
T0 T1
post pend

 IPC
 How is link established?
 Can link be associated with multiple tasks?
 How many links between a pair of tasks
 What is link capacity, and are there any
buffers?
 What is message size?
 Links unidirectional – bidirectional?

T0 Network T1
send receive
B0 B1

Meetha.V.Shenoy 20
MailBox
Network Network
T0 T1
send recieve
B0 B1

 Zerocapacity – rendezvous/ Idle IRQ
 Bounded Capacity
 Unbounded Capacity – Continous RQ

 Foreground Background
 Process that interact with user or other I/O
devices
 Remainder

 Schedules
 Dispatch
 Ensure commn & Syncg

 TCB /PCB
 The identifier of the process
 Register values for the process - program counter and stack
pointer values for the process.
 The address space for the process
 Priority
 Process accounting information, such as when the process was
last run, how much CPU time it has accumulated, etc.
 Pointer to the next PCB
 I/O Information

 Static
 Usually used in Embedded Systems
 Dynamic

 Context – important info regd task state
 When task is stopped/blocked/pre-empted –

context must be saved
 On return – context is restored

 Duplicate Hardware
 TCB
 Stacks
 Stack Frame/Activation Record

Task Synchronization
M8: Embedded Software – Tasks & Task
Management
RL8 .2.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy
• Share Logical Address space

Cooperating Tasks
• Concurrent access to common
data T1
T0
• Data Inconsistency
• Aberrant/unexpected behavior
3
Co-operating Tasks
Producer Consumer
while(1) while(1)
if not full if not empty
add item get item
inc count dec count
else else
wait for space wait for item
endwhile endwhile
4
Problem ??
• Simultaneous access of count
• 3 different values at any instant of time
• Critical Section – Mutually exclusive access
5
Non-CS
Synchronization
Entry Section
• Mutually exclusive Critical Section
• Condition
Exit Section
Non-CS
6
Requirements – Soln
• Mutual exclusion
• Deadlock
• Bounded Waiting
7
Soln 1: Flags
• Each Task has a flag
• Atomic procedure await
await (codn)
{
statements
} variable
8
Flags
Producer Consumer
While(1) While(1)
if not full if not empty
add item get item
await(!T1Flag) {T0 await(!T0Flag) {T1
Flag= true} Flag = true}
inc count dec count
T0Flag = False T1Flag = False
else else
wait for space wait for item
endwhile endwhile
9
Soln 2 Token Passing

• Similar to token passing protocols
10
Problems
• Task process not wanting to co-operate can hold
token forever
• Task/Process with token crashes
• Token corrupted/lost
• Task with token terminates without giving up token
• Task added/removed
11
Solution
• Add Task for token management
• Every time a task enters/leaves – registers with
token management
• Disadvantages
▫ No. of tasks increase
▫ IPC reqd for new task
12
Soln 3 – Manage interrupts

• Disallow interrupts
▫ Entry sec – disable int
▫ CS
▫ Exit sec – enable int
• Disadv
▫ Loops in CS – too long
• Soln
▫ Disable ints below a certain level
▫ Works for single processing environment
13
Soln 4: Semaphores
• Semaphores: Introduced by Dijkstra in 1960s
• Semaphores have two purposes

▫ Mutex: Ensure threads don’t access critical section at
same time
▫ Scheduling constraints: Ensure threads execute in
specific order
14
Semaphores
• Variables that can be accessed only thro’ atomic op
• wait – p(s)
• signal – v(s)
• p(s) – test & set
• v(s) - reset
15
Semaphores – Critical resources

Producer Consumer
{ {
…. ….
wait(s) wait(s)
critical section critical section
signal(s) signal(s)
…. ….
} }
16
Semaphores
wait(s) signal(s)
{ {
while(s); s = false;
s = true; }
}
17
Spin Lock & Busy Waiting

• Lock on resource – spin lock
• Waits for Lock to open – busy waiting
• Binary Semaphore - mutex
18
Semaphores – Counting
• Takes value 0 – N-1
• List of associated processes
• Process executes wait instruction – semaphore not available
• Task blocks itself
▫ Block – waiting queue of semaphore (task waiting)
▫ Control Transferred to scheduler
• Restarted when signal op is executed
▫ Wake –up
▫ Task in ready state – ready queue
19
Semaphores
wait(s) signal(s)
{ {
s = s+1; s = s -1;
if(s >1) if (s>1)
{ {
add process to waiting remove process from
queue; waiting queue;
block; wakeup(p);
} }
} }
20
Semaphore implementation
typedef struct {
int value;
queue tlist;
} semaphore;
21
How to use semaphores – example 1

• Mars Rover – data management of an extensible digital imaging
system
• Data collected from cameras, IR scans, atmospheric analysis,
topographic mapping
• Data collected into a set of buffers – uploaded via satellite to earth
22
Buffer 0
Buffer 1
Buffer n-2
Buffer n-1
23
Requirements
• Imaging System – Producer
• Satellite System – Consumer
• Count no. of free/full buffers
• Controlled access to individual buffers for read/write
24
Algorithm - Producer
• Producer checks if any buffer is empty
• If empty – waits for exclusive access to buffer pool.
• Access gained – data added – then exit
25
Algorithm - Consumer
• Consumer checks whether any buffer has data
available
• If yes waits for exclusive access
• Buffer pool – available consumer gets data and
exits
26
Semaphores
• mutex (1)
• empty (n-1)
• full (0)
27
Camera Satellite
while(1) while(1)
…. wait(full);
produce an item wait(mutex);
…. ….
wait(empty); remove item from
wait(mutex); buffer;
…. ….
add item to buffer; signal(mutex);
…. signal(empty);
signal(mutex); ….
signal(full); consume item
…. ….
endwhile
endwhile
28
Semaphores
wait(empty) signal(empty)
sem_wait (semaphore *S) sem_signal (semaphore *S) {
{ S->value++;
S->value--; if (S->value <= 0) {
if (S->value < 0) { remove thread t from
add this process to S->tlist;
S->tlist;
wakeup(t);
block();
}
}
}
29
Classic Synch Problem

30
Modified Rover
• Imaging System can gather data simultaneously
• Data can be uploaded using several links
• Data object shared by several concurrent processes
▫ Readers – Writers
 Readers access data simultaneously
 Writer and reader try simultaneously
▫ Reader – Writer Problem
• No Reader waits unless a writer is accessing the buffer
31
Semaphores
• wrtSem (1)
• mutex (1)
• numReaders (0)
32
writer Reader
wait(wrtSem); while(1)
…. wait(mutex);
numReaders++;
perform writing;
if(numReaders==1)
…. wait(wrtSem);
signal(wrtSem); endif
signal(mutex);
….
Perform reading;
…
wait(mutex);
numReaders--;
if(numReaders==0)
signal(wrtSem);
endif
signal(mutex);
endwhile
33
Soln 5: Monitors
• Monitors provide control by allowing only one process to access a
critical resource at a time
▫ A class/module/package
▫ Contains procedures and data
 Data – object state
• Data abstraction mechanism that encapsulates a repsn of an
abstract object
34
An Abstract Monitor
monitor monName
{
… some local declarations
… initialize local data
procedure name(…arguments)
… other procedures
permanent variables (static)
}
35
Monitor Rules
• Only procedure names are visible – Public interface
• Permanent variables can be changed only thro’ one of the
procedures
• Any process can access any monitor procedure at any time
• Only one process may enter a monitor procedure
▫ Simultaneous access of two different proc
▫ Two invocations of same proc
• No process may directly access a monitor’s local variables
• A monitor may only access it’s local variables
36
Things Needed to Enforce Monitor
• “wait” operation
▫ Forces running process to sleep
• “signal” operation
▫ Wakes up a sleeping process
• Condition
▫ Synchronisation
37
Bounded Buffer Problem

• Codn variables
▫ Not Empty
 Tracks empty buffers -0
 Signaled when buffer count >0
▫ NotFull
 Tracks full buffers – 0
 Signaled when count < n-1
• Procedures
▫ put(data)
▫ get(data)
• Protected Entity
▫ bufferPool
38
Monitor - implementation
Monitor boundBuffer
bufferPool;
count = 0;
cond notEmpty;
cond not Full;
39
put(anItem)
{
while(count==n)wait(notFull);
put an item into buffer;
signal(notEmpty);
}
40
get(anItem)
{
while(count==0)wait(notEmpty);
get an item from buffer;
signal(notFull);
}
41
Producer Consumer
while(1) while(1)
…. ….
produce an item boundBuffer.get(anItem)
…. ….
boundBuffer.put(anItem) produce an item
…. ….
endwhile endwhile
42
Problems
• Starvation
▫ Block one process from running – while a
processor is waiting – other process are added and
removed in LIFO
• Deadlock
RTS
M8: Embedded Software - Tasks, Task Management & RTS

Timing Characteristics of Embedded System
 Embedded computing systems do more than one thing
 Environment causes Mode changes  Embedded System to
behave differently
 May perform logically different tasks – different rates
 Data may arrive at different rates
 Asynchronous input
2 RL8.3.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy

RTOS
 Allocate Resources of Computing System – programs that request them
 Scarcest Resource – CPU
 Schedule process
 OS considers the process to be in any one of 3 states
 Waiting
 Ready
 Executing
 Common way to select a process - priority

RTOS
Executing
needs data
gets data
& CPU
Pre-empted ready
Chosen to run
Rxd data
Ready Waiting
needs data

Scheduling – Priority Driven
Process Priority Exec Ready
P1 1 10 15
P2 2 30 0
P3 3 20 18
P2 P1 P2 P3
0 10 20 30 40 50 60
Timing Requirements of Processes

Initiation Time – Process goes from Wait state  Ready state
Deadline

Aperiodic Process
P1
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event

Scheduling
7 RL8.3.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy
Independent Periodic Tasks
Rate Monotonic Scheme (RMS)
 Fixed priority
 Preemptive Scheduling
 Priorities are assigned according to the periods
 Shorter the period higher is the priority
 Results show that as long as processor utilization of a task set
is less than 69 % - task set is schedulable using RMS
 Bound is obtained using the formula
i=1n ci/pi  n(21/n -1)

2  utilization -0.69
Simple periodic tasks – 100 %

Independent Periodic/Aperiodic Tasks
Earliest Deadline First (EDF)
 Dynamic priority
 Priorities are assigned according to the deadline
 Earlier the deadline higher is the priority
 Results show that as long as processor utilization of a task set
is lesser than 100 % - task set is schedulable using EDF
 Bound is obtained using the formula
i=1n ci/pi  1
utilization – 100 %

Independent Periodic/Aperiodic Tasks
Least Laxity First (LLF)
 Dynamic priority
 Priorities are assigned according to the laxity of task
 Laxity li =(di – ci’ – ti)
 Smaller the laxity higher is the priority
 More preemptions
 May result in Thrashing

Task Comp period
time
T1 2 6
T2 2 8
T3 3 12
11 RL8.3.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy
12
Resource Reclaiming
 Correctness
 Inexpensiveness
 Bounded Complexity
 Effectiveness
 Cost of rescheduling < Time reclaimed
 Cost of scheduling must be lesser than 10 % of the worst case computation
time of the tasks

Resource Reclaiming
 Resource reclaiming in a uni-processing environment with independent
tasks – straight forward
 Resource reclaiming in such environments – greedy in nature
 Work conserving/ band width conserving
 Resource Reclaiming will never leave a processor idle if there is a
dispatchable task

Resource Reclaiming
T1 =( 0,10,22)
T2 = (0,6,25)
T3 = (10,8,26)
T4 = (8,10,35)
T1 T2 T3 T4
0 10 16 24 34
T1 T2 T3 T4
0 5 10 16 20 24 34
T1 T2 T3 T4
0 5 11 15 25

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BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

● Introduction & Deﬁnition of Embedded Systems.

● A system within a system.

● Diﬀerence between general purpose computing systems

● Characteristics of an Embedded System.

BITS Pilani, Pilani Campus

EMBEDDED = Placed Inside

Embedded Computing System !

BITS Pilani, Pilani Campus

Just like a motor, bearing or gear….

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

We need a much smaller version of this!

BITS Pilani, Pilani Campus

System on Chip devices along with FPGA fabric interface

They comes in variety of packages and peripheral options...

BITS Pilani, Pilani Campus

● Development Cycle of an Embedded system.

Hardware Testing Software Testing

Operation & Maintenance

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

● C Data structures resembles to those used in

BITS Pilani, Pilani Campus

● CPUs in embedded systems.

Which one is more popular in embedded systems

BITS Pilani, Pilani Campus

● Requirements for a GPP to qualify as an embedded

BITS Pilani, Pilani Campus

Data Source - mouser.in

BITS Pilani, Pilani Campus

● Memory types in Embedded Systems

● Dynamic Memory Allocation

BITS Pilani, Pilani Campus

● Hit and Miss

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

● A fully charged cell will be at around 4.2V and a

● Depending on the chemistry of the cell, discharge

BITS Pilani, Pilani Campus

● To test the discharge capacity of the cells, a constant,

BITS Pilani, Pilani Campus

Suppose you were drawing a current of 1A form the cell

BITS Pilani, Pilani Campus

● Display to show the set discharge current and show the

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

● A fully charged cell will be at around 4.2V and a

● Depending on the chemistry of the cell, discharge

BITS Pilani, Pilani Campus

● To test the discharge capacity of the cells, a constant,

BITS Pilani, Pilani Campus

● Display to show the set discharge current and show the

BITS Pilani, Pilani Campus