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HDL Designer Series Language Support Guide: Release v2019.4
HDL Designer Series Language Support Guide: Release v2019.4
HDL Designer Series Language Support Guide: Release v2019.4
Guide
Release v2019.4
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Chapter 1
SystemVerilog Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting SystemVerilog as Your Default Design Language . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting SystemVerilog Language Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Creating SystemVerilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Adding SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Editing SystemVerilog Text Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting Code Browser Content for SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Exploring SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Identifying SystemVerilog Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reporting Assertions and Covergroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reporting SystemVerilog Bound Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compiling and Simulating SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 2
Verilog 2005 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting Verilog 2005 as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Migrating Verilog 95 Designs to Verilog 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Verilog 2005 Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Working with Verilog 2005 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example: Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating a Text View for an Existing Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . 34
Creating Verilog 2005 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example: Creating a Block Diagram View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Creating Mixed Dialect Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Importing Verilog 2005 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Editing Verilog 2005 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Generating HDL From Verilog 2005 Graphical Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 3
VHDL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL 2008 Supported Language Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL 2008 Backward Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Setting VHDL as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Setting VHDL Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Working with VHDL Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Chapter 4
PSL Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Creating PSL Assertion Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Linking PSL Assertions to HDS Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Attaching PSL files to a Design View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Activating PSL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Including PSL Files in ModelSim Compilation/ Simulation Flows . . . . . . . . . . . . . . . . . . . 79
End-User License Agreement
with EDA Software Supplemental Terms
This chapter provides a quick tour through the different features and tools available in HDL
Designer Series (HDS) that you can use in developing your SystemVerilog designs.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting SystemVerilog as Your Default Design Language . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting SystemVerilog Language Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Creating SystemVerilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Adding SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Editing SystemVerilog Text Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting SystemVerilog Syntax Highlighting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting Code Browser Content for SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Exploring SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Identifying SystemVerilog Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reporting Assertions and Covergroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reporting SystemVerilog Bound Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compiling and Simulating SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction
SystemVerilog combines the Verification capabilities of HVL (Hardware Verification
Language) with the ease of Verilog to provide a single platform for both design and verification.
HDS currently provides text-level support for SystemVerilog 3.1a/1800 standard.
SystemVerilog files/designs can be created in HDS, organized into libraries / projects and
managed accordingly. Not only can you create new designs but also you can import any of your
old SystemVerilog code created outside HDS. Doing so you can make use of all design
management capabilities provided through the tool.
HDS Design Manager helps you browse through your code and view it from different
perspectives. It also allows you to obtain reports on specific aspects of your design as assertions,
coverage points, etc.,
In this chapter we provide a quick tour through the different features and tools available in HDS
that you can use in developing your SystemVerilog designs.
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SystemVerilog Support
Setting SystemVerilog as Your Default Design Language
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SystemVerilog Support
Setting SystemVerilog Language Preferences
2. On the File tab, specify your default Verilog file extension by choosing from the System
Verilog(default) dropdown list.
3. On the Headers tab, choose from a pulldown list of view headers. The selected header is
is used in the created view. Graphical views are not supported.
4. You can set default Verilog compiler directives in the DefaultDirectives tab.
5. You can set default packages in the Default Packages tab.
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SystemVerilog Support
Creating SystemVerilog Files
6. Click OK. The above defined preferences will be added to new views.
Related Topics
Preferences for HDLViews [HDL Designer Series User Manual]
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SystemVerilog Support
Adding SystemVerilog Designs
If you choose to use a template, define whether you want to specify your own or work
with the default one. Templates are available for SV packages, programs, interfaces, and
classes.
5. Click Next to specify the new Verilog file location, name, and format.
6. Click Finish.
The DesignPad editor is launched displaying your new SystemVerilog file.
You can check your new design object in the Design Units pane of the Design Explorer
Tip
: To display a created class in the Design Unit Browser pane, add your code after the
module code or create a new class from the Design Creation wizard. Nested Classes
only appear in the DesignPad code browser.
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SystemVerilog Support
Adding SystemVerilog Designs
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SystemVerilog Support
Editing SystemVerilog Text Views
The figure below illustrates how HDS allows you to manage your design files in DesignPad.
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SystemVerilog Support
Setting SystemVerilog Syntax Highlighting Preferences
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SystemVerilog Support
Setting Code Browser Content for SystemVerilog
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SystemVerilog Support
Setting Code Browser Content for SystemVerilog
Procedure
1. In DesignPad, choose Options > Preferences.
The Preferences dialog box is displayed.
2. In the Categories pane, browse to Document Type > SystemVerilog > Code Browser.
The Code Browser page displays showing a list of all the available SystemVerilog
objects.
3. Select/deselect the objects you want to show/hide in the code browser window.
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SystemVerilog Support
Exploring SystemVerilog Designs
Tip
The Design Unit browser can be toggled to an Object List browser where you can group,
sort, and filter all objects (including instances).
You can control which objects are visible, which columns of additional data are shown
(including user defined property information), and save these settings in alternative
“viewpoints.”
For more information, refer to Accessing Design Explorersand Using the Side Data Browser.
Program Blocks
Program blocks are intended to contain test bench code, that is, they relate to verification only.
They represent leaf-levels of hierarchy.
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SystemVerilog Support
Identifying SystemVerilog Design Objects
Interfaces can
• Describe a re-usable group of signals. Modports allow this overall group of signals to be
divided into a number of subgroups and also have specific directionality, for example,
master and slave.
• Model “protocol” behavior, including protocol checking when associated with tasks and
functions.
• Be used as “adaptors” or “converters” thus allowing the same component to be
connected up at differing levels of abstraction.
Classes
Classes are user-defined data types that bring in the essence of object oriented programming to
the SystemVerilog language.
Tip
Systemverilog only allows one level of inheritance.
Packages
A package is a new SystemVerilog design unit similar to the VHDL package.
It is used for
SystemVerilog Assertions
An assertion is a statement that validates assumptions or checks conditions in a program
SystemVerilog has an integrated set of constructs that help you to build assertions and closely
couple them with the rest of your design or verification code.
• Provide control-oriented coverage. Coverage allows you to tell how well a design has
been tested.
• Specify and validate design behavior.
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SystemVerilog Support
Identifying SystemVerilog Design Objects
Cover Groups
Cover groups, derives from hardware verification languages. Cover groups can contain multiple
individual coverage points, allow “binning” of multiple values and support cross-coverage to
track combinations of values.
In the following section, you will see how the new SystemVerilog objects are displayed in each
Design Explorer browser.
Files’ Browser
In the Files’ Browser HDL source files can be expanded to see the top-level objects within
them. The key information/objects supported in the Files’ browser for Systemverilog designs
are shown in Table 1-5:
Table 1-5. System Verilog Files’ Browser Objects
Icon Description
Program Block
Interface
Class
Package
Module
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SystemVerilog Support
Reporting Assertions and Covergroups
Related Topics
Finding Design Objects [HDL Designer Series User Manual]
Creating an Unparsed Files Report [HDL Designer Series User Manual]
Finding Unbound Components [HDL Designer Series User Manual]
Procedure
In the Design Manager window
Select a module and from the popup menu choose Reports > Assertions(SV) or
Reports > Covergroups(SV).
You can report assertions/coverage within a single object, its hierarchy, or within the
entire library.
A new tab displays showing a report of the design assertions/covergroups.
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SystemVerilog Support
Reporting SystemVerilog Bound Objects
Related Topics
Finding Design Objects [HDL Designer Series User Manual]
Creating an Unparsed Files Report [HDL Designer Series User Manual]
Finding Unbound Components [HDL Designer Series User Manual]
You can create a report showing all the files to which a selected module is bound.
Procedure
1. In the Design Manager window, select a module and from the popup menu choose
Reports > WhereBound
A new tab displays showing a report of all the files to which a selected module is bound.
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SystemVerilog Support
Compiling and Simulating SystemVerilog Designs
Procedure
1. Choose Help > HDS Setup Assistant menu to display the HDS Setup Assistant wizard.
2. Open the Simulator page, which automatically detects the presence of any installed
simulators and displays the path of the executables.
3. Select the ModelSim simulator or the QuestaSim simulator.
4. Click Finish.
5. Select the root design unit in the Design Unit Browser.
6. Choose Settings from the popup menu of the QuestaSim Compile task to display the
Compile Settings dialog box.
7. Check the Enable code coverage option on the coverage tab.
8. Choose Run through Components from the popup menu of the Simulator button in the
shortcut bar.
The progress of the compilation is shown in the HDL Log window.
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SystemVerilog Support
Compiling and Simulating SystemVerilog Designs
Tip
Compilation warning messages may appear in the log window.
On completion of the compilation of the design, the Start Simulator dialog box displays.
9. Accept the default resolution, and check that the Interactive (GUI) and Enable
Communication with HDS options are selected.
10. Check the Enable code coverage option.
11. In the Additional simulator arguments field, enter the following to suppress the vopt
optimization mode and enforce the debug mode.
-novopt-assertdebug
12. Click the OK button to confirm the Start ModelSim/QuestaSim dialog box and load the
design.
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SystemVerilog Support
Compiling and Simulating SystemVerilog Designs
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Chapter 2
Verilog 2005 Support
Verilog 2005 style code can be generated from HDS Graphical Editors. HDL created or
generated code can be compiled and simulated.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting Verilog 2005 as the Default HDS Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Migrating Verilog 95 Designs to Verilog 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Verilog 2005 Language Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Working with Verilog 2005 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example: Creating a Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Creating a Text View for an Existing Verilog 2005 Interface . . . . . . . . . . . . . . . . . . . . . . 34
Creating Verilog 2005 Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Text Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating Verilog 2005 Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example: Creating a Block Diagram View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Creating Mixed Dialect Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Importing Verilog 2005 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Editing Verilog 2005 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Generating HDL From Verilog 2005 Graphical Views . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction
HDS provides both text-level and graphical support for the Verilog 2005 language.In this
chapter we will provide an overview of the features in HDS designed to support the V2k
language.
Importing existing Verilog 2005 designs in addition to creating new designs is now
possible.You can even toggle the language of existing HDS Verilog 95 designs.
Verilog 2005 text designs can be instantiated inside Block Diagram and IBD views as well as
visualized or converted to graphics. Generate constructs are recovered as Embedded Blocks.
HDS does not currently provide support for Generate Frames in Verilog 2005 designs.
Signed signals and ports, uwire net types, declarations with continuous assignments in addition
to initialized variable declarations are now supported.
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Verilog 2005 Support
Setting Verilog 2005 as the Default HDS Language
Tip
You can change the set default language for a specific view from the Design Content
Creation wizard.
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Verilog 2005 Support
Migrating Verilog 95 Designs to Verilog 2005
4. Select the Language node and set the SystemVerilog (Text Verilog) option in the left
pane of the window. Click Finish to save your new setting
You can change the default language for a specific view from the Design Content
Creation Wizard dialog box.
Related Topics
HDS Setup Assistant Wizard [Start Here Guide]
Main Settings Dialog Box [HDL Designer Series User Manual]
The HDL code generated from the converted designs will follow the set Verilog 2005
generation properties.
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Verilog 2005 Support
Migrating Verilog 95 Designs to Verilog 2005
Prerequisites
Existing Verilog ‘95 design.
Caution
VHDL or SystemVerilog designs cannot be toggled to Verilog 2005 designs.
Procedure
1. Select a Design Unit from the Design Units pane in the Design Explorer window.
2. Choose Change Language to > Verilog 2005 from the popup menu.
Notice that the Language field now displays Verilog 2005 instead of Verilog 95 for the
selected design unit.
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Verilog 2005 Support
Migrating Verilog 95 Designs to Verilog 2005
Caution
Verilog 2005 graphical views cannot be toggled back to Verilog 95 designs.
This is an example to show how you can toggle the language of your existing Verilog 95
designs and make use of the new Verilog 2005 supported features. It also points out the
rules followed when changing the language to Verilog 2005.
3. Create a new library with the name backup and copy the contents of the Uart_V library
into it.
4. Open the Uart_V library from the Project Manager window.
5. In the Design Units browser, select the uart_top design unit and choose Change
LanguageTo > Verilog 2005 from the popup menu.
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Verilog 2005 Support
Migrating Verilog 95 Designs to Verilog 2005
Notice that the Language field now displays Verilog 2005 instead of Verilog 95 for the
selected design unit.
6. Drag the uart_top design unit to the hierarchy browser. Examine the displayed
hierarchy.
Notice how the language of all Blocks and Embedded Blocks, which exist under the
uart_top design unit, has been changed to Verilog 2005. Toggling the language of a
Block Diagram or IBD view enforces the toggling of all underlying Blocks and
Embedded Blocks.
7. Expand the xmit_rcv_control design unit. The language of all views for this design unit
have been automatically changed to Verilog 2005.
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Verilog 2005 Support
Setting Verilog 2005 Language Preferences
8. Expand the uart_top design unit to view its symbol. The symbol language has been
automatically changed to Verilog 2005.
9. Select the uart_top symbol and choose Open from the popup menu.
A graphical representation of the symbol displays.
10. In the Structure Navigator bar, double-click Interface to display a tabular representation
of your symbol
Notice the new Signed and Value columns.
11. Expand the uart_top design unit to view its symbol. The symbol language has been
automatically changed to Verilog2005.
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Verilog 2005 Support
Setting Verilog 2005 Language Preferences
2. On the File tab, specify your default Verilog file extension by choosing from the Source
Verilog (default) dropdown list.
3. On the Headers tab, choose from a pulldown list of view headers. The selected header is
is used in the created view.
You can also choose to include the generation properties as comment text after the
header in the generated HDL and if this option is set, you can also include the signal
status in generated state machine HDL
4. You can set default Verilog compiler directives in the DefaultDirectives tab.
5. Click OK.
The above stated preferences will be added to any new view.
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Verilog 2005 Support
Working with Verilog 2005 Interfaces
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Verilog 2005 Support
Example: Creating a Verilog 2005 Interface
6. Click the Symbol icon in the Structure Navigator to display the graphical view of the
created interface.
Procedure
1. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
2. Choose Graphical View from the Categories pane and specify the view type as:
Interface from the File Types pane.
3. Set the language dialect as Verilog 2005.
4. Click Next to display the Specify View Name/Location page.
5. Select SCRATCH_LIB from the Library name dropdown list, and enter the following in
the Design Unit entry field:
Interface_V2k
6. Click Finish.
The Interface tabular IO editor is launched.
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Verilog 2005 Support
Example: Creating a Verilog 2005 Interface
7. Add the following signals and save the new interface view.
8. Click the Symbol icon in the Structure Navigator to display the graphical view of the
created interface.
Notice how the ports are declared using the default Ansi-C style.
9. Right-click on the symbol to display the Objects Properties dialog box. The Symbol tab
allows you update the symbol, symbol instances, and Symbol/View update properties.
You can change the display of symbol ports to show or hide the new Signed and Value
properties.
10. To change the display of the ports of the symbol to show itself, click the Port Display
button in the Symbol group box. To change the display of the ports of the symbol
instances, click the Port Display button in the Symbol Instance group box.
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Verilog 2005 Support
Creating a Text View for an Existing Verilog 2005 Interface
11. Click on the Port Display button in the Symbol group box and set the Signed and Value
options and save your changes.
Notice how the port declarations on the symbol have been updated.
Note
Two-way synchronization is supported between the Symbol tabular IO and the
Signals table.
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Verilog 2005 Support
Creating a Text View for an Existing Verilog 2005 Interface
Procedure
1. Set the port style that you want to have in your created text file by selecting Options >
Verilog from the Design Explorer window to display the Verilog Options dialog box.
2. On the Style tab, set your port definition style preferences as ANSI-C or List.
3. Select a Verilog 2005 Interface design unit from the Design Unit browser.
4. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
5. Choose Verilog View from the Categories pane and specify the view type as: Module
from the File Types pane.
6. Set the language dialect as Verilog 2005.
7. Click Next to specify the new Verilog view location and name.
8. Click Finish. The DesignPad editor is launched showing the newly created Verilog File.
The created Verilog file contains a module interface that has port style generated
according to the module ports declaration settings defined through the Verilog Options
dialog.
Related Topics
Design Content Creation Wizard [HDL Designer Series User Manual]
Verilog 2005 Generation Preferences [HDL Designer Series User Manual]
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Verilog 2005 Support
Creating Verilog 2005 Views
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Verilog 2005 Support
Example: Creating a Block Diagram View
5. Click Finish.
The appropriate editor is launched displaying the selected graphical view.
Procedure
1. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
2. Choose Graphical View from the Categories pane and select Block Diagram from the
File Types pane.
3. Set the language dialect as Verilog 2005.
4. Click Next to display the Specify View Name/Location page. Accept the set values and
click Next.
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Verilog 2005 Support
Creating Mixed Dialect Designs
5. On the Specify Interface page, the Symbol ports are listed. You can edit or update the
displayed list.
6. Click Finish to launch the Block Diagram editor displaying the new BD view.
7. Select the output2 signal and right-click to choose Object Properties from the popup
menu.
The Signals page of the Object Properties dialog box displays.
8. Select wire from the Type field dropdown list.
Notice that the Value field is disabled. Only output signals of type reg, integer, and time
can be given a value. Input signals can not have values.
9. Select the input2 signal and right-click to choose Object Properties from the popup
menu.
The Signals page of the Object Properties dialog box displays.
10. Select real from the Type field dropdown list.
Notice that the Signed check box is dimmed. Only signals of types net or reg can be
signed.
11. Close your block diagram view.
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Verilog 2005 Support
Creating Mixed Dialect Designs
Note
Mixed dialect graphical views are not allowed.
Tip
You have the ability to instance SystemVerilog text components into Verilog 2005 Block
Diagram and IBD views. This applies to components only, but not to blocks.
Procedure
1. Select a design unit from the Design Unit browser and do one of the following:
• Open the Design Content Creation wizard by clicking the New/Add button in the
shortcut bar.
• Choose New from the popup menu.
2. Specify your design type and language following the rules stated in table Table 2-2 and
complete the wizard steps.
A new view is created. A warning message is issued incase you try to create an invalid
view.
Examples
1. In the Design Explorer select the clock_divider design unit and choose New >
Graphical View>Block Diagram from the popup menu.
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Verilog 2005 Support
Importing Verilog 2005 Designs
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Verilog 2005 Support
Editing Verilog 2005 Signals
b. Specify whether you want to use a filelist to obtain information on design content by
setting the Use Filelist option. Specify the files to add.
2. Specify the method to determine the Verilog dialect used as Auto or Specified.
3. Complete the Add Existing Design wizard steps. The Design Explorer window is
displayed showing the added design.
Related Topics
Addition of Existing Design Content to an HDS Project [HDL Designer Series User Manual]
Removing Design Files From a Project [HDL Designer Series User Manual]
Add Existing Files to Library Dialog Box [HDL Designer Series User Manual]
Add Existing Design Wizard [HDL Designer Series User Manual]
Procedure
1. Open a Verilog 2005 Block Diagram view and double-click on any of its signals.
The Object Properties dialog displays.
2. Set the properties as for any Verilog or VHDL signal.
3. For all types other than Time and integer specify the signed property.
4. You may specify a value for any of your output signals.
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Verilog 2005 Support
Generating HDL From Verilog 2005 Graphical Views
Notice that any changes are synchronized with the Signals table and with the view
declaration text.
Related Topics
Editing Object Properties [Graphical Editors User Manual]
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Verilog 2005 Support
Generating HDL From Verilog 2005 Graphical Views
Verilog 2005 graphical views, this can be useful in the case of downstream tools with limited
Verilog 2001/2005 support.
Note
Moduleware instances in Verilog 2005 designs follow the Verilog 2005 code generation
settings.
Procedure
1. In the Design Explorer window select Options > Verilog to display the Verilog Options
dialog box. This is where you will be setting all your code generation preferences.
a. In the Generated Files group box of the File tab, set the file naming rules you want to
use when generating Verilog files or leave the default settings.
b. In the Verilog 2005 Generation Group box, specify some Verilog 2005 code style
features.
o Specify whether you want to generate ports in a port list or using the ANSII-C
style. On choosing to generate listed ports, the list sub-options allow you to
combine your generated ports’ data types with the port declaration or have them
in separate statements.
o For leaf level views, you can specify the sensitivity list separator style to be a
comma or an “OR”. You can also choose to allow implicit event expression @*
where appropriate.
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Verilog 2005 Support
Generating HDL From Verilog 2005 Graphical Views
c. Specify the style features of the generated code in the Style Options Group Box of
the Style tab or choose to leave the defaults
You can:
o Specify the default tab width setting for Verilog text views by entering the
number of spaces to indent.
o Choose to generate HDL with the begin and else keywords on separate lines.
o Add blank lines around comments by specifying the number of lines to add
before and after the comment line.
o Choose to add a label to generated always or initial code blocks and specify a
prefix or suffix which is added to the label names. You can also choose whether
to use uppercase or lowercase labels.
o Choose to include associated properties in generated Verilog.
d. If your design includes ModuleWare components, you can specify the style features
of the generated code.
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Verilog 2005 Support
Generating HDL From Verilog 2005 Graphical Views
In the ModuleWare Generation group box of the Style tab you can do the following:
o Choose blocking assignments or non-blocking assignments to registers in the
HDL for sequential (clocked) ModuleWare components.
o Optionally enter a non-blocking delay when non-blocking assignment is set.
(Note that the default value 0 means no delay.)
o Set the signal name prefix used for ModuleWare signals in the generated HDL
o Choose to use Pragmas when needed.
o Choose to use bus slices in sensitivity lists depending on whether your
simulation tool support slices or not; If it doesn’t do not set this option as this
will lead to including only the bus name in the sensitivity list on generation.
e. You can specify parameter generation properties. In the Parameters group box of the
Style tab, you can do the following:
o Choose whether all Verilog parameters defined in the symbol are automatically
initialized with default values and displayed when a component is instantiated. If
this option is not set, only the overridden parameters are displayed.
o Choose whether a synopsys template pragma is added above the parameter
declaration in the generated HDL for the symbol. (This option is enabled for
backward compatibility but should normally be unset if you are not using the
Synopsys synthesis tools.)
2. In the Design Explorer window, select a Verilog 2005 design unit and choose a
generation option from the Tasks > Generation submenu. Check the log window for
any warnings and errors.
3. To view your generated file, choose HDL > View Generated HDL.
Related Topics
Preferences for HDL Views [HDL Designer Series User Manual]
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Verilog 2005 Support
Generating HDL From Verilog 2005 Graphical Views
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Chapter 3
VHDL Support
HDS provides both text-level and graphical support for the VHDL language. In this chapter, we
will provide an overview of the features in HDS designed to support the VHDL 2008 language.
Importing existing VHDL 2008 designs in addition to creating new designs is now possible.
VHDL text designs can be instantiated inside Block Diagram and IBD views as well as
visualized or converted to graphics.
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VHDL Support
VHDL 2008 Supported Language Features
Note
Note the following:
• Using aggregates on the left and right hand side of the assignment statement is
not supported.
• Using aggregates within aggregate elements is not supported.
• Auto-detection of VHDL dialects depends on the syntax of constructs. When
using Slices in Array Aggregates, auto-detection may not work correctly in some
cases. If the automatic dialect detection of the design file is incorrect, you can set
the dialect manually as a workaround.
The following table lists the packages in which these operators are defined in VHDL
2008, along with the types these operators are defined for.
Table 3-1. Logical Shift Operators Support in VHDL 2008
Package Type
<Predefined> All operators are defined for arrays of bits and booleans.
numeric_bit & numeric_std All operators are defined for signed and unsigned.
numeric_bit_unsigned All operators are defined for bit_vector.
numeric_std_unsigned Only sla and sra are defined for std_ulogic_vector.
fixed_generic_pkg All operators are defined for unresolved_ufixed and
unresolved_sfixed.
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VHDL Support
VHDL 2008 Supported Language Features
VHDL 2008 also supports array aggregate choices containing others. This is
supported as long as the expression index range is locally static. See the following
example:
VARIABLE s : bit_vector(3 downto 0);
CASE s IS
WHEN ('0', others => '1') => …
WHEN ('1', others => '0') => …
END CASE;
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VHDL Support
VHDL 2008 Supported Language Features
Note
The body of generate statements ELSIF/ELSE and CASE should have begin/end
in pairs. Knowing that either both (begin/end) should exist, or both do not exist.
CONTEXT work.ctx;
ENTITY top IS
PORT(in1, in2: IN std_logic; out1: OUT std_logic);
END top;
Note
You can write a context reference in the context clause preceding a design unit,
or nested within another context declaration.
o Delimited Comments:
In addition to single line comments (starting with “- -” and ending on the same line),
VHDL 2008 added delimited comments (starting with “/*” and ending with “*/”).
A delimited comment can end on the same line, or on any subsequent line. Note that
nesting of comments is not allowed.
See the following example:
/* This is a delimited comments spanning
multiple lines and this /* is not the start of
a nested comment.
-- This line belongs to the delimited comment.
The delimited comment end here */
o Condition Operators:
VHDL 2008 provides a condition operator ?? which is used to simplify conditional
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VHDL Support
VHDL 2008 Supported Language Features
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VHDL Support
VHDL 2008 Supported Language Features
Package Instantiation:
PACKAGE myPkgInst IS NEW work.myPkg GENERIC MAP (width => 8);
Or:
PACKAGE myPkgInst IS NEW work.myPkg;
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VHDL Support
VHDL 2008 Supported Language Features
Or:
PACKAGE myPkg2 IS
GENERIC (a: integer;
PACKAGE myFixedPkg IS NEW IEEE.fixed_generic_pkg GENERIC MAP
(default) );
END PACKAGE;
Or:
PACKAGE myPkg3 IS
GENERIC (a : integer;
PACKAGE myFixedPkg IS NEW IEEE.fixed_generic_pkg GENERIC MAP
(x) );
END PACKAGE;
The entity in the example can be used to instantiate and_gate for BIT or
STD_LOGIC in the generic map during the unit instantiation as follows:
U1: entity work.and_gate generic map (t => BIT) port map
(...);
U2: entity work.and_gate generic map (t => STD_LOGIC) port map
(...);
• Generic Lists in Subprograms — VHDL 2008 allows you to define a generic list
within a subprogram. This allows a subprogram to operate on an arbitrary data
type. When you instantiate a subprogram having generics, its instance can be
called in the same way as regular subprograms. The subprogram’s instance
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VHDL Support
VHDL 2008 Supported Language Features
provides actual values to the generics in the generic map during the unit
instantiation. See the following example:
function max
generic(type t)
parameter(in1, in2 : t) return t is
begin
//…
end function max;
…
function max_int is new max generic map (t => INTEGER);
The entity in the example can be used to instantiate a comparator to compare two
values of type INTEGER or STD_LOGIC_VECTOR for example. This is done
by providing an actual function in the generic map that takes parameters of type
INTEGER or STD_LOGIC_VECTOR as follows:
function isGreaterInteger(in1, in2 : in INTEGER) return
boolean is ...
U1: entity work.and_gate generic map (t => BIT, isGreater =>
isGreaterInteger) port map (...);
function isGreaterStdLogicVec(in1, in2 : in STD_LOGIC_VECTOR)
return boolean is ...
U2: entity work.and_gate generic map (t => BIT, isGreater =>
isGreaterStdLogicVec) port map (...);
o std.standard:
HDL Designer Series supports a number of VHDL 2008 new predefined types and
associated operations, and at the same time extends support for the set of operations
associated with existing predefined types.
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VHDL Support
VHDL 2008 Supported Language Features
The following table shows a list of the newly supported predefined types along with
their supported associated operations:
Table 3-2. New Predefined Types and Associated Operations
New Type Associated Operations
boolean_vector • Array/scalar logic operators
• Logical (unary) reduction operators
• ?= and ?/= operators
• to_string operations
• to_bstring, to_ostring, to_hstring and their aliases
• Maximum and minimum operations
integer_vector • Relational operators and concatenation operator
• Maximum and minimum operations
real_vector • Equality and inequality operators and concatenation operator
• Maximum and minimum operations
time_vector • Equality and inequality operators and concatenation operator
• Maximum and minimum operations
The following table shows a list of the existing predefined types along with their
newly supported associated operations:
Table 3-3. Existing Predefined Types and Associated Operations
Existing Type Associated Operations
bit_vector • Array/scalar logic operators
• Maximum and minimum operations
bit • ?? operator
• Maximum and minimum operations
boolean • Maximum and minimum operations
time • mod and rem operators
• Maximum and minimum operations
o IEEE Packages:
The following IEEE packages are newly supported/enhanced by HDL Designer
Series:
• ieee.numeric_bit
• ieee.numeric_bit_unsigned
• ieee.numeric_std
• ieee.numeric_std_unsigned
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VHDL Support
VHDL 2008 Supported Language Features
• ieee.math_real
• ieee.math_complex
• ieee.std_logic_1164
• Fixed/Floating Point Packages
o fixed_float_types
o fixed_pkg
o fixed_generic_pkg
o float_pkg
o float_generic_pkg
The float_generic_pkg package is supported in DesignChecker, except for
DC synthesis checks.
o Unconstrained Element Types:
Composite types in VHDL such as arrays and records can have elements whose
types can be constrained or unconstrained. Prior to VHDL 2008, element types were
only allowed to be constrained, but currently unconstrained element types are
allowed for arrays and records in HDL Designer Series.
You can create a subtype for an unconstrained type, therefore, when defining a port
or a signal, you can define the constraints for both the type and its subtypes.
It should be noted that this construct does not support records in DesignChecker.
o All in Sensitivity List:
VHDL 2008 provides the ability to specify the “all” construct as a sensitivity list for
a combinatorial process instead of explicitly mentioning all read signals.
It should be noted that this construct is supported in DesignChecker except for DC
synthesis checks.
o Matching Case Statements:
The matching case statement (or case with “don’t care”) allows the use of a case
choice that includes “don’t care” elements. It is written like an ordinary case
statement but with a question mark after the case keyword as follows: case?. It is
mostly used with an expression of a vector type whose elements are values of
std_ulogic or std_logic type.
o External Names:
An external name signifies an object in the design hierarchy containing the external
name. External names may refer to a variable, signal or constant which is found in
another part of the design hierarchy. External names are enclosed in double angle
brackets << ... >>.
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VHDL Support
VHDL 2008 Supported Language Features
The grave accent character (also called back-tick) is followed by an identifier that
indicates the kind of information provided or the action to be performed. Other text
in the same line of code, if any, provides any further information required. The
directive ends with the end of the line. For more information and examples, refer to
IEEE Standard VHDL Language Reference Manual.
Also, protected tool directives are partially supported in HDS. HDS ignores anything
written between “protect begin protected directive” and “protect end protected
directive”.
• Breakpoints:
o A new package was added to the std library in HDS. The package name is ENV. This
package has stop and finish procedures necessary for supporting breakpoints.
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VHDL Support
VHDL 2008 Backward Compatibility Issues
• Improved IO Enhancements:
o IEEE.textio package and other IEEE packages having string operations are updated
to support new IO enhancements.
o Added predefined and implicit to_string functions, and predefined aliases required
for Improved IO enhancements.
• Miscellaneous:
o Updated standard package in HDS std library with a newer version.
o You can use the old set of packages by replacing the following directory with the
one having the old packages: <HDS home dir>/hdl_libs/ieee/hdl.However, they will
be ignored by DesignChecker synthesis rules.
However, if you need to migrate a design to VHDL 2008, you may need to manually make
some changes to your design.
This section describes the backward compatibility issues, the solutions provided by HDL
Designer Series, and the manual intervention required only in case you need to migrate to
VHDL 2008.
Note
Most of the following issues will appear in DesignChecker when running synthesis checks,
and may also appear in other flows in HDL Designer Series.
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VHDL Support
VHDL 2008 Backward Compatibility Issues
Example: Two READ procedures are defined in textio package; one with an std_logic_vector
output value and the other with an std_ulogic_vector output value.
Solution: As long as the file containing the duplicate subprograms is parsed as a pre-VHDL
2008 dialect, no syntax error will be produced. If the subprogram is called from a VHDL 2008
or a pre-VHDL 2008 file, HDL Designer Series chooses the most appropriate definition to bind
with.
Migration: If the file having the subprogram definitions is parsed as VHDL 2008, you have to
omit the subprogram with the std_logic_vector parameter, otherwise the tool will give the
following syntax error:
Examples:
Solution: As long as the file containing the user definitions is parsed as a pre-VHD 2008 file,
no syntax errors will be raised. The tool filters out the standard definitions when parsing pre-
VHDL 2008 files so that only user definitions are visible.
Migration: If the file having the user definitions is parsed as VHDL 2008, you have to omit
your definitions or replace them with aliases to the standard definitions, otherwise the tool will
raise the following syntax errors for the above examples respectively:
1 Use
of undeclared identifier 'real_vector'.
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VHDL Support
VHDL 2008 Backward Compatibility Issues
Example: The new keyword default was used as an identifier in old designs.
Solution: As long as the file containing the identifier is parsed as pre-VHDL 2008, no syntax
error will be raised. HDL Designer Series filters out keywords based on the language version of
the parsed file.
Migration: If the file having the identifier is parsed as VHDL 2008, you have to rename the
identifier first, otherwise the tool will raise the following syntax error:
Solution: HDL Designer Series provides one set of packages that includes de facto and standard
packages. Hence, for the above example, you can either keep any code referencing
std_logic_unsigned or change it to reference numeric_std_unsigned.
Solution: HDL Designer Series automatically handles matching the subprogram call if the
caller has the same or different language version of the file having the subprogram declaration.
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VHDL Support
Setting VHDL as the Default HDS Language
Tip
You can change the set default language for a specific view from the Design Content
Creation wizard.
3. You can set VHDL as the default language by choosing Help > HDSSetup Assistant.
The HDS Setup Assistant wizard appears.
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VHDL Support
Setting VHDL Language Preferences
4. Select the Language node and set the VHDL 2008 (Graphics) or VHDL 2008 (Text
VHDL) option in the left pane of the window. Click Finish to save your new setting.
Related Topics
HDS Setup Assistant Wizard [Start Here Guide]
Main Settings Dialog Box [HDL Designer Series User Manual]
3. On the Headers tab, choose from a pulldown list of view headers. The selected header is
used in the created view.
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VHDL Support
Setting VHDL Language Preferences
You can also choose to include the generation properties after the header in the
generated VHDL. If this option is set, you can also include the signal status in generated
state machine VHDL.
4. Click OK. The above stated preferences will be added to any new view.
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VHDL Support
Working with VHDL Interfaces
6. You can click on the Symbol icon in the Structure Navigator to display the graphical
view of the created interface.
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VHDL Support
Example: Creating a VHDL Interface
Procedure
1. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
2. Choose Graphical View from the Categories pane and specify the view type as
Interface from the File Types pane.
3. Set the language as VHDL 2008.
4. Click Next to display the Specify View Name/Location page.
5. Select SCRATCH_LIB from the Library name dropdown list and enter VHDL_Interface
in the Design Unit name field.
6. Click Finish. The Interface tabular IO editor is launched.
7. Add the following signals and save the new interface view.
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VHDL Support
Example: Creating a VHDL Interface
8. Click the Symbol icon in the Structure Navigator to display the graphical view of the
created interface. Notice how the ports are declared using the default Ansi-C style.
9. Right-click on the symbol and choose Objects Properties to display the Symbol/
Interface Properties dialog box. The Symbol tab allows you to update the symbol and
symbol instance options.
To change the display of the ports of the symbol to show itself, click the Port Display
button in the Symbol group box. To change the display of the ports of the symbol
instances, click the Port Display button in the Symbol Instance Options group box.
10. Click the Port Display button in the Symbol group box, the Port Display Control dialog
box displays.
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VHDL Support
Creating a Text View for an Existing VHDL Interface
11. In the Fields to display group box, update the format and visibility of usage and
declaration information attached to all ports then save your changes. Notice how the port
declarations on the symbol have been updated.
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VHDL Support
Creating a Text View for an Existing VHDL Interface
Related Topics
Design Content Creation Wizard [HDL Designer Series User Manual]
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VHDL Support
Creating VHDL 2008 Views
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VHDL Support
Example: Creating a Block Diagram View
Procedure
1. Invoke the Design Content Creation wizard by clicking the New/Add button in the
Design Explorer shortcut bar.
2. Choose Graphical View from the Categories pane and select Block Diagram from the
File Types pane.
3. Set the language as VHDL 2008.
4. Click Next to display the Specify View Name/Location page. Accept the set values then
click Next.
5. On the Specify Interface page, the Symbol ports are listed. You can edit or update the
displayed list.
6. Click Finish to launch the Block Diagram editor displaying the new BD view.
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VHDL Support
Importing VHDL 2008 Designs
7. Select the Out2 signal, then right-click and choose Object Properties from the popup
menu.
The Signals page of the Object Properties dialog box displays.
8. Select std_logic from the Type field dropdown list. Notice that the Bounds field is
disabled.
9. Close your block diagram view.
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VHDL Support
Generating HDL from VHDL Graphical Views
Procedure
1. Open a VHDL Block Diagram view and double-click on any of its signals.
The BD Object Properties dialog box displays.
2. Set the properties as for any Verilog or VHDL signal.
3. Specify a value for any of your output signals. Notice that any changes are synchronized
with the Signals table and with the view declaration text.
Related Topics
Editing Object Properties [Graphical Editors User Manual]
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VHDL Support
Generating HDL from VHDL Graphical Views
Procedure
1. In the Design Explorer window select Options > VHDL to display the VHDL Options
dialog box. This is where you will be setting all your code generation preferences.
a. In the Generated Files group box of the File tab, set the file naming rules you want to
use when generating VHDL files or leave the default settings.
b. Specify the style features of the generated code in the Style Options group box of the
Style tab or choose to leave the defaults.
o Specify the default tab width setting for VHDL text views by entering the
number of spaces to indent.
o Add blank lines around comments by specifying the number of lines to add
before and after the comment line.
o Choose to use uppercase VHDL keywords.
o Create component declarations. They will be applied to new diagrams only.
o Choose to specify a prefix or suffix that is added to the label names. You can
also choose whether to use uppercase or lowercase labels.
o Choose the way VHDL end statements are generated for entities, architectures,
configuration, subprograms (functions and tasks), and components.
o Choose to include associated properties in generated VHDL.
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VHDL Support
Generating HDL from VHDL Graphical Views
c. If your design includes ModuleWare components, you can specify the style features
of the generated code.
In the ModuleWare Generation group box of the Style tab, you can do the following:
o Choose 4-Value Logic (MVL4) to generate ModuleWare components using the
std_ulogic values 0, 1, X and Z only or 9-Value Logic (MVL9) to allow all the
std_logic or std_ulogic values 0, 1, L, H, X, -, U, W and Z. (This option controls
whether the values in conditions and CASE selects are compared using MVL4 or
MVL9 values.)
o Set the Signal/Variable Name Prefix used for ModuleWare signals in the
generated HDL.
o Choose to use signal names instead of internal variables in the VHDL generated
for a ModuleWare part.
o Choose to use Attributes when needed.
o Choose to use bus slices in sensitivity lists depending on whether your
simulation tool support slices or not; If it does not, do not set this option as this
will lead to including only the bus name in the sensitivity list on generation.
d. In the Test Bench Generation group box of the Style tab, you can specify the default
names for the test bench and the testers views.
2. In the Design Explorer window, select a VHDL design unit and choose a generation
option from the Tasks > Generate submenu. Check the log window for any warnings
and errors.
3. To view your generated file, choose HDL > View Generated HDL.
Related Topics
Preferences for HDL Views [HDL Designer Series User Manual]
Identifiers and Reserved Words [HDL Designer Series User Manual]
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Chapter 4
PSL Assertions
PSL is a language for the formal specification of hardware. PSL files contain PSL verification
units (vunits).
HDS supports the creation of PSL assertion files as side data files linked to a design view and
recognized by the ModelSim flow.
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PSL Assertions
Creating PSL Assertion Files
Note
Files created in the Side Data pane are automatically associated to the specified design view.
Procedure
1. Invoke the Design Content Creation wizard.
2. Choose Registered View from the Categories pane and Property Specification Language
File from the File Types pane.
3. To base your assertions file on a predefined template, set the UseTemplates option.
Otherwise, click Next to start with a blank file.
If you choose to use a template, define whether you want to specify your own or work
with the default one.
4. Click Next to specify the new PSL file location, name and format. At this stage you can
do one of the following
• Create your PSL file as a stand-alone file not linked to any design view by selecting
Design Unit from the In section dropdown list.
• Link your PSL file to a specific design view by choosing to place your files in the
Side Data or Design Files section. Refer to “Linking PSL Assertions to HDS Design
Views” on page 77.
5. Click Finish. The DesignPad editor is launched displaying your new PSL file.
Related Topics
Linking PSL Assertions to HDS Design Views
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PSL Assertions
Linking PSL Assertions to HDS Design Views
Tip
HDS treats these linked files as side data files to the specified design view.
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PSL Assertions
Activating PSL Files
You now have a PSL file stored as a design file and a reference to that PSL file
stored in it’s simulation side data.
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PSL Assertions
Including PSL Files in ModelSim Compilation/ Simulation Flows
2. Choose Properties from the popup cascade menu. This will display the design view
Properties dialog.
3. Select a PSL file and click the Unset Active button on the Simulation page.
Note
You can also select your PSL file in the Side Data pane and from the popup cascade
menu choose set active or inactive.
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PSL Assertions
Including PSL Files in ModelSim Compilation/ Simulation Flows
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