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VNS3NV04D-E

OMNIFET II
fully autoprotected Power MOSFET

Features

Max On-State resistance (per ch.) RON 120m


Current limitation (typ)
Drain-Source clamp voltage
ILIMH
VCLAMP
3.5A
40V
( s )
SO-8
u ct
■ Linear current limitation
o d
■ Thermal shut down
P r


Short circuit protection
Integrated clamp Description
e t e
■ Low current drawn from input pin
o l
The VNS3NV04D-E is a device formed by two
■ Diagnostic feedback through input pin
b s
monolithic OMNIFET II chips housed in a
■ Esd protection
- O standard SO-8 package. The OMNIFET II are
designed in STMicroelectronics VIPower M0-3

(analog driving)
(s )
Direct access to the gate of the power mosfet Technology: they are intended for replacement of
standard Power MOSFETS from DC up to 50KHz

c t
Compatible with standard power mosfet applications. Built in thermal shutdown, linear

d u current limitation and overvoltage clamp protects


the chip in harsh environments.

r o Fault feedback can be detected by monitoring the

e P voltage at the input pin.

l e t
s o
O b
Table 1. Device summary
Package Tube Tape and Reel

SO-8 VNS3NV04D-E VNS3NV04DTR-E

September 2013 Rev 3 1/21


www.st.com 21
Contents VNS3NV04D-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
)
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
( s
3
u ct
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
o d
Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
P r
Linear current limiter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
t e
Overtemperature and short circuit protection . . . . . . . . . . . . . . . . . . . . . . 16
e
3.4 l
Status feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
o
4 b s
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
- O
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
(s )
SO-8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
c t
SO-8 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

d u
5
r o
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

e P
l e t
s o
O b

2/21
VNS3NV04D-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1


Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. Source Drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 9. Protections (-40°C < Tj < 150°C, unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

3/21
List of figures VNS3NV04D-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5


Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Source-Drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.
Figure 11.
( s )
Static Drain-Source On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.
Figure 13.
Static Drain-Source On resistance vs. Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

u
Static Drain-Source On resistance Vs. Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ct
Figure 14.
d
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
o
Figure 15.
Figure 16.
P r
Static Drain-Source On resistance Vs. Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17.
Figure 18.
t e
Turn On current slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Turn On current slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
e
Figure 19.
l
Input voltage Vs. Input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
o
Figure 20.
Figure 21.
b s
Turn off Drain source voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Turn off Drain-Source voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 22.
Figure 23.
- O
Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching time resistive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 24.
Figure 25.
(s )
Switching time resistive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 26.
c t
Normalized On resistance Vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 27.
Figure 28.
d u
Normalized Input threshold voltage Vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normalized current limit Vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 29.
r o
Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 30.
Figure 31.
e P
SO-8 Package mechanical data & package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SO-8 Tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 32.
l e t
SO-8 Tape and reel shipment (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

s o
O b

4/21
VNS3NV04D-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

DRAIN1 DRAIN2

OVERVOLTAGE OVERVOLTAGE
CLAMP CLAMP

INPUT1 INPUT2
GATE GATE
CONTROL CONTROL

LINEAR LINEAR

( s )
ct
OVER CURRENT CURRENT
LIMITER LIMITER OVER
TEMPERATURE TEMPERATURE

SOURCE1 SOURCE2
d u
r o
e P
Figure 2. Configuration diagram (top view)

l e t
s o
SOURCE 1 1

O b 8 DRAIN 1
DRAIN 1
-
INPUT 1

)
SOURCE 2

(s
INPUT 2 4 5
DRAIN 2
DRAIN 2

c t
d u
r o
e P
l e t
s o
O b

5/21
Electrical specifications VNS3NV04D-E

2 Electrical specifications

Figure 3. Current and voltage conventions

IIN1 RIN1 ID1


INPUT 1 DRAIN 1
IIN2 RIN2 ID2
VIN1 VDS1
INPUT 2 DRAIN 2
VIN2
SOURCE 1 SOURCE 2 VDS1

( s )
u ct
o d
P r
e t e
2.1 Absolute maximum ratings
o l
b s
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the

- O
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for

(s )
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

t
program and other relevant quality document.

c
Table 2.
d u
Absolute maximum ratings
Symbol
r o Parameter Value Unit

e P
VDSn Drain-Source Voltage (VINn=0V) Internally clamped V

l e t VINn Input voltage Internally clamped V

s o IINn Input current +/-20 mA

O b RIN MINn
IDn
Minimum input series impedance
Drain current
220
Internally limited

A
IRn Reverse DC output current -5.5 A
VESD1 Electrostatic discharge (R=1.5K, C=100pF) 4000 V
Electrostatic discharge on output pins only (R=330,
VESD2 16500 V
C=150pF)
Ptot Total dissipation at Tc=25°C 4 
Tj Operating junction temperature Internally limited °C
Tc Case operating temperature Internally limited °C
Tstg Storage temperature -55 to 150 °C

6/21
VNS3NV04D-E Electrical specifications

2.2 Thermal data


Table 3. Thermal data
Symbol Parameter Max value Unit

Rthj-lead Thermal resistance junction-lead (per channel) 30 °C/W


Rthj-amb Thermal resistance junction-ambient 80(1) °C/W
1. When mounted on a standard single-sided FR4 board with 50mm of Cu (at least 35 m thick) connected
2
to all DRAIN pins of the relative channel

2.3 Electrical characteristics


( s )
ct
Values specified in this section are for -40°C< Tj <150°C, unless otherwise stated.

Table 4. Off
d u
o
Pr
Symbol Parameter Test Conditions Min Typ Max Unit

VCLAMP
Drain-Source clamp
voltage
VIN=0V; ID=1.5A

e t e 40 45 55 V

Drain-Source clamp
o l
VCLTH
threshold voltage
VIN=0V; ID=2mA

b s 36 V

-O
Input threshold
VINTH VDS=VIN; ID=1mA 0.5 2.5 V
voltage

IISS
( s
Supply current from
) VDS=0V; VIN=5V 100 150 A

ct
input pin
Input-Source clamp IIN=1mA 6 6.8 8

du
VINCL V
voltage IIN=-1mA -1.0 -0.3

r o
Zero input voltage
VDS=13V; VIN=0V; Tj=25°C 30

e
IDSS
Pdrain current
(VIN=0V) VDS=25V; VIN=0V 75
A

e t
s ol Table 5. On

O b Symbol Parameter

Static Drain-Source
Test conditions

VIN=5V; ID=1.5A; Tj=25°C


Min Typ Max

120
Unit

RDS(on) m
On resistance VIN=5V; ID=1.5A 240

7/21
Electrical specifications VNS3NV04D-E

Electrical characteristics (continued) (Tj=25°C, unless otherwise specified)

Table 6. Dynamic
Symbol Parameter Test conditions Min Typ Max Unit

Forward
gfs (1) VDD=13V; ID=1.5A 5.0 S
transconductance
COSS Output capacitance VDS=13V; f=1MHz; VIN=0V 150 pF

Table 7. Switching
Symbol Parameter Test conditions Min Typ Max

( s ) Unit

ct
td(on) Turn-on delay time 90 300 ns
VDD=15V; ID=1.5A

du
tr Rise Time 250 750 ns
Vgen=5V; Rgen=RIN MIN=220
td(off) Turn-off delay time 450 1350 ns
tf Fall time
(see Figure 4)
r o 250 750 ns
td(on) Turn-on delay time
e P 0.45 1.35 s
VDD=15V; ID=1.5A
e t s

ol
tr Rise time 2.5 7.5
Vgen=5V; Rgen=2.2 K
td(off) Turn-off delay time 3.3 10.0 s
tf Fall time
b s
(see Figure 4)
2.0 6.0 s

O
VDD=15V; ID=1.5A

)-
(dI/dt)on Turn-on current slope 4.7 A/s
Vgen=5V; Rgen=RIN MIN=220

Qi
t
Total input charge( s VDD=12V; ID=1.5A; VIN=5V
8.5 nC

u c Igen=2.13mA (see Figure 7)

o d
Pr
Table 8. Source Drain diode
Symbol Parameter Test Conditions Min Typ Max Unit

e t e
VSD(1) Forward On voltage ISD=1.5A; VIN=0V 0.8 V
l
so
trr Reverse recovery time 107 ns

O b Qrr
Reverse recovery
charge
ISD=1.5A; dI/dt=12A/s
VDD=30V; L=200H
(see Figure 5)
37 C

Reverse recovery
IRRM 0.7 A
current
1. Pulsed: Pulse duration = 300s, duty cycle 1.5%

8/21
VNS3NV04D-E Electrical specifications

Table 9. Protections (-40°C < Tj < 150°C, unless otherwise specified)


Symbol Parameter Test Conditions Min Typ Max Unit

Ilim Drain current limit VIN=5V; VDS=13V 3.5 5 7 A


Step response current
tdlim VIN=5V; VDS=13V 10 s
limit
Overtemperature
Tjsh 150 175 200 °C
shutdown
Tjrs Overtemperature reset 135 °C
Igf Fault sink current VIN=5V; VDS=13V; Tj=Tjsh 10 15 20 mA
Starting Tj=25°C; VDD=24V

( s )
ct
Single pulse VIN=5V Rgen=RIN MIN=220
Eas 100 mJ
avalanche energy L=24mH
(see Figure 6 and Figure 8)
d u
Switching time test circuit for resistive load r o
Figure 4.

e P
l e t
s o
O b VD

)-
Rgen
Vgen

t ( s
u c
ID

o d
Pr
90%

e t e
ol tr tf
10%

bs
t
td(on) td(off)

O Vgen

9/21
Electrical specifications VNS3NV04D-E

Figure 5. Test circuit for diode recovery times

A
A
D
I FAST L=100uH
OMNIFET DIODE

S B
B

220
D
VDD
Rgen
I
( s )
ct
OMNIFET

Vgen
d u
o
S

P r 8.5 

e t e
o l
b s
Figure 6.
- O
Unclamped inductive load test circuits

(s )
c t
d u
r o
e P
l e t
s o
O b
RGEN
VIN

PW

10/21
VNS3NV04D-E Electrical specifications

Figure 7. Input charge test circuit

VIN GEN

( s )
u ct
o d
P r
e te
o l ND8003

b s
Figure 8.
- O
Unclamped inductive waveforms

(s )
c t
d u
r o
e P
l e t
s o
O b

11/21
Electrical specifications VNS3NV04D-E

2.4 Electrical characteristics curves


Figure 9. Source-Drain diode forward Figure 10. Static Drain-Source On
characteristics resistance
Vsd (mV) Rds(on) (mohms)
1100
1000

1050 Tj=-40ºC
900
Vin=0V Vin=2.5V
1000 800

950 700

900 600

850 Tj=25ºC
500

800 400

750

700
300

( s )Tj=150ºC

ct
200

650 100

600
0 1 2 3 4 5 6 7 8 9 10 11 12
0
0.05 0.1 0.15 0.2 0.25

d u0.3 0.35 0.4 0.45 0.5 0.55


Id (A)

r o Id(A)

Figure 11. Derating curve


P
Figure 12. Static Drain-Source On

e
resistance vs. Input voltage

l e t
Rds(on) (mohms)

o 300

bs
275

250

- O 225

200
Tj=150ºC

( s ) 175

150
Id=3.5A
Id=1A

c t 125

100
Tj=25ºC

du
Tj=-40ºC Id=3.5A
75 Id=1A

Id=3.5A

o
50
Id=1A

P r 25

0
3 3.5 4 4.5 5 5.5 6 6.5

e t e Vin(V)

ol
Figure 13. Static Drain-Source On Figure 14. Transconductance
resistance Vs. Input voltage

b s
O Rds(on) (mohms)
250

225
Id=1.5A
Gfs (S)
11

10
Vds=13V Tj=-40ºC
200 9
Tj=25ºC
175 8

Tj=150ºC Tj=150ºC
7
150
6
125
5
100
4
75
Tj=25ºC 3
50
Tj=-40ºC 2
25 1

0 0
3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vin(V) Id (A)

12/21
VNS3NV04D-E Electrical specifications

Figure 15. Static Drain-Source On Figure 16. Transfer characteristics


resistance Vs. Id

Rds(on) (mohms) Idon (A)


250 6

225 5.5
Vds=13.5V
Vin=5V 5
200
Tj=150ºC
4.5
175
4
Tj=150ºC
150
3.5
125 3
Tj=25ºC Tj=-40ºC
100 2.5

2
75

50
Tj= - 40ºC
1.5

1
Tj=25ºC

( s )
ct
25
0.5
0 0

du
0 0.5 1 1.5 2 2.5 3 3.5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Id (A) Vin (V)

r o
Figure 17. Turn On current slope Figure 18. Turn On current slope

e P
e t
ol
di/dt(A/us) di/dt(A/usec)
5 1.75

bs
4.5
Vin=5V 1.5
4 Vdd=15V
Vin=3.5V

O
Id=1.5A 1.25 Vdd=15V
3.5

-
Id=1.5A
3
1
2.5
)
t(s
0.75
2

1.5

u c 0.5

d
0.25
0.5

r o
0 250 500 750 1000 1250 1500 1750 2000 2250 2500
0
0 250 500 750 1000 1250 1500 1750 2000 2250 2500

e P Rg(ohm) Rg(ohm)

e t
ol
Figure 19. Input voltage Vs. Input Figure 20. Turn off Drain source voltage
charge slope

b s Vin (V) dv/dt(V/usec)

O 9

8
Vds=1V
300

275
250 Vin=5V
7
Id=1.5A Vdd=15V
225
Id=1.5A
6 200

175
5
150
4
125

3 100

75
2
50
1
25

0 0
0 1 2 3 4 5 6 7 8 9 10 11 0 500 1000 1500 2000 2500
250 750 1250 1750 2250
Qg (nC)
Rg(ohm)

13/21
Electrical specifications VNS3NV04D-E

Figure 21. Turn off Drain-Source voltage Figure 22. Capacitance variations
slope

dv/dt(V/usec) C(pF)
300 350
275
250 Vin=3.5V
300
Vdd=15V f=1MHz
225
Id=1.5A Vin=0V
200 250
175

150 200
125
100 150
75

50
25
100

( s )
ct
0 50
0 500 1000 1500 2000 2500

u
0 5 10 15 20 25 30 35
250 750 1250 1750 2250

d
Vds(V)
Rg(ohm)

Figure 23. Switching time resistive load Figure 24. Switching time resistive load
r o
e P
t
t(usec) t(nsec)

e
4 900

3.5
td(off)
o l
800
tr

s
Vdd=15V
Vdd=15V
700 Id=1.5A

b
3 Id=1.5A
Rg=220ohm
Vin=5V tr 600
2.5

O
)-
500
2
tf 400

t(s
1.5 td(off)
300

u c td(on)
200
tf

td(on)

d
0.5 100

ro
0 0
0 500 1000 1500 2000 2500 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25

e P 250 750 1250


Rg(ohm)
1750 2250
Vin(V)

l e t
Figure 25. Output characteristics Figure 26. Normalized On resistance Vs.

s o temperature

O b Id (A)
5

4.5
Vin=5V
Rds(on) (mOhm)
4

Vin=4V 3.5
4 Vin=5V
Id=1.5A
3.5 3
Vin=3V
3
2.5
2.5
2
2

1.5 1.5

1
1
0.5

0 0.5
0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 175

Vds (V) Tc )ºC)

14/21
VNS3NV04D-E Electrical specifications

Figure 27. Normalized Input threshold Figure 28. Normalized current limit Vs.
voltage Vs. temperature junction temperature

Vinth (V) Ilim (A)


2 10

1.8 9
Vds=Vin Vin=5V
1.6 8
Id=1mA Vds=13V
1.4 7

1.2 6

1 5

0.8 4

)
0.6 3

0.4 2

( s
ct
0.2 1

u
0 0

d
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (ºC)

r o
Tc (ºC)

Figure 29. Step response current limit


e P
Tdlim(usec)

l e t
13

12.5
s o
12

11.5
Vin=5V
Rg=220ohm

O b
11

) -
(s
10.5

10

9.5
c t
9

d u
8.5

8
r o
e P
7.5

t
5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5

o l e Vdd(V)

b s
O

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Protection features VNS3NV04D-E

3 Protection features

During normal operation, the INPUT pin is electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power MOSFET and can be used as a switch from
DC up to 50KHz. The only difference from the user’s standpoint is that a small DC current
IISS (typ. 100A) flows into the INPUT pin in order to supply the internal circuitry.
The device integrates:

3.1 Overvoltage clamp protection


( s )
ct
Internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET
stage give this device unrivalled ruggedness and energy handling capability. This feature is
mainly important when driving inductive loads.
d u
r o
3.2 Linear current limiter circuit
e P
l e t
Limits the drain current ID to Ilim whatever the INPUT pin voltages. When the current limiter

s o
is active, the device operates in the linear region, so power dissipation may exceed the
capability of the heatsink. Both case and junction temperatures increase, and if this phase
b
lasts long enough, junction temperature may reach the overtemperature threshold Tjsh.
O
) -
(s
3.3 Overtemperature and short circuit protection

c t
These are based on sensing the chip temperature and are not dependent on the input
u
voltage. The location of the sensing element on the chip in the power stage area ensures
d
r o
fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the
range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted
P
when the chip temperature falls of about 15°C below shut-down temperature.

e
l e t
3.4
s o Status feedback

O b In the case of an overtemperature fault condition (Tj > Tjsh), the device tries to sink a
diagnostic current Igf through the INPUT pin in order to indicate fault condition. If driven from
a low impedance source, this current may be used in order to warn the control circuit of a
device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not
able to supply the current Igf, the INPUT pin will fall to 0V. This will not however affect the
device operation: no requirement is put on the current capability of the INPUT pin
driver except to be able to supply the normal operation drive current IISS.
Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL Logic circuit.

16/21
VNS3NV04D-E Package and packing information

4 Package and packing information

4.1 ECOPACK® packages


In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

( s )
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P r
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o l
b s
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(s )
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s o
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Package and packing information VNS3NV04D-E

4.2 SO-8 Package mechanical data


Figure 30. SO-8 Package mechanical data & package outline
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 1.750 0.0689
MECHANICAL DATA
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091

D (1) 4.800 4.900 5.000 0.1890 0.1929 0.1969

E 5.800 6.000 6.200 0.2283 0.2362 0.2441

( s )
ct
E1 (2) 3.800 3.900 4.000 0.1496 0.1535 0.1575

e 1.270 0.0500
h 0.250 0.500 0.0098 0.0197

d u
L 0.400 1.270 0.0157 0.0500

r o
P
L1 1.040 0.0409
k 0˚ 8˚ 0˚ 8˚
ccc 0.100 0.0039

e te
Notes: 1. Dimensions D does not include mold flash,
protrusions or gate burrs.

o l
bs
Mold flash, potrusions or gate burrs shall not
exceed 0.15mm in total (both side).
2. Dimension “E1” does not include interlead flash
SO-8
or protrusions. Interlead flash or protrusions shall
not exceed 0.25mm per side.

- O
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d u
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s o
O b

0016023 D

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VNS3NV04D-E Package and packing information

4.3 SO-8 Packing information


Figure 31. SO-8 Tube shipment (no suffix)

B
C Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A A 3.2
B 6
C (± 0.1) 0.6

All dimensions are in mm.

Figure 32. SO-8 Tape and reel shipment (suffix “TR”)


( s )
REEL DIMENSIONS
u ct
o d
P r
Base Q.ty
Bulk Q.ty
A (max)
2500
2500
330

e t eB (min)
C (± 0.2)
1.5
13

o l F
G (+ 2 / -0)
20.2

s
12.4
N (min)

b
60
T (max) 18.4

O
)-
All dimensions are in mm.

TAPE DIMENSIONS
t ( s
u c
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width

o d W 12

P r
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
D (± 0.1/-0)
4
8
1.5

e t e Hole Diameter
Hole Position
D1 (min)
F (± 0.05)
1.5
5.5

o l Compartment Depth
Hole Spacing
K (max)
P1 (± 0.1)
4.5
2

b s All dimensions are in mm.

O End

Start

Top No components Components No components


cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

19/21
Revision history VNS3NV04D-E

5 Revision history

Table 10. Document revision history


Date Revision Changes

28-Oct-2005 1 Initial release.


Document reformatted and converted into new ST template.
25-Jun-2007 2
Table 4: Off - IDSS unit corrected
25-Sep-2013 3 Updated disclaimer.

( s )
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P r
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(s )
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20/21
VNS3NV04D-E

Please Read Carefully:

( s )
u ct
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

o d
All ST products are sold pursuant to ST’s terms and conditions of sale.

P r
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

e t e
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

o l
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

s
third party products or services or any intellectual property contained therein.

b
- O
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

(s )
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

c t
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

d u
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

r o
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

P
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

e
e t
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

l
s o
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

O b
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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