MB90860A FujitsuMediaDevices

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FUJITSU SEMICONDUCTOR
DATA SHEET DS07-13732-2E
16-bit Proprietary Microcontroller

CMOS
F2MC-16LX MB90860A Series

MB90F867A (S) , MB90867A (S)
■ DESCRIPTION
The MB90860A-series is Fujitsu 16-bit general-purpose microcontroller which enhances each kind of timers and
communication macros. With the new 0.35 µm CMOS technology, Fujitsu now offers 128 Kbytes on-chip FLASH-
ROM program memory. An internal voltage booster removes the necessity for a second programming voltage.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGES
100-pin Plastic QFP 100-pin Plastic LQFP
(FPT-100P-M06) (FPT-100P-M05)
MB90860A Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-
plied PLL clock).
• 16 Mbyte CPU memory space
• 24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
(Continued)
2
MB90860A Series
(Continued)
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
• UART (LIN/SCI) : 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : 2 channels
• Up to 400 kbit/s transfer rate
• DTP/External interrupt : 16 channels, CAN wakeup : 2 channels
• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• ROM security function
• Protects the content of ROM (MASK ROM device only)
• Flash security function
• Protects the content of Flash (Flash device only)
• External bus interface
• Clock monitor function
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C standard Specification as defined by
Philips.
3
MB90860A Series
■ PRODUCT LINEUP
Part Number
MB90F867A (S) , MB90867A (S) MB90V340(S)
Parameter
CPU F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
System clock
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
Boot-block,Flash memory
ROM External
128 Kbytes
RAM 6 Kbytes 30 Kbytes
Emulator-specific
 Yes
power supply*1
0.35 µm CMOS with on-chip voltage regulator for internal 0.35 µm CMOS with
Technology power supply + Flash memory with on-chip voltage regulator
On-chip charge pump for programming voltage for internal power supply
3.5 V to 5.5 V : at normal operating (not using A/D converter)
Operating
4.0 V to 5.5 V : at using A/D converter/Flash programming 5 V ± 10%
voltage range
4.5 V to 5.5 V : at using external bus
Temperature range −40 °C to +105 °C 
Package QFP-100, LQFP-100 PGA-299
4 channels 5 channels
UART Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 Kbit/s) 2 channel
24 input channels
A/D
Converter 10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels) Supports External Event Count function
Signals an interrupt when overflowing
16-bit Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
I/O Timer
(fsys = Machine clock freq.)
(2 channels) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare Signals an interrupt when 16-bit I/O Timer match output compare registers.
(8 channels (16-bit) / A pair of compare registers can be used to generate an output signal.
16 channels (8-bit) )
16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive
(8 channels) Signals an interrupt upon external event
(Continued)
4
MB90860A Series
(Continued)
Part Number
MB90F867A (S) , MB90867A (S) MB90V340(S)
Parameter
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
8/16-bit Sixteen 8-bit reload registers for L pulse width
Programmable Pulse Sixteen 8-bit reload registers for H pulse width
Generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(8 channels) 8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN Interface  3 channels
External Interrupt Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
(16 channels) expanded inteligent I/O services (EI2OS) and DMA
D/A converter  2 channels
Up to100 kHz
devices with ‘S’-suffix : without subclock
Subclock for low
devices without ‘S’-suffix : with subclock
power operation
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O Ports Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash
Data retention time : 20 years 
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90860A Series
■ PIN ASSIGNMENTS
• MB90F867A (S) , MB90867A (S)
(TOP VIEW)
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P82/SIN0/TIN2/INT14R
P84/SCK0/INT15R
P03/AD03/INT11
P02/AD02/INT10
P83/SOT0/TOT2
P01/AD01/INT9
P00/AD00/INT8
P77/AN23/INT7
P76/AN22/INT6
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P87/SCK1
P86/SOT1
P85/SIN1
MD0
MD1
MD2
PA 1
RST
Vss
Vcc
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P04/AD04/INT12 81 50 P75/AN21/INT5
P05/AD05/INT13 82 49 P74/AN20/INT4
P06/AD06/INT14 83 48 P73/AN19/INT3
P07/AD07/INT15 84 47 P72/AN18/INT2
P10/AD08/TIN1 85 46 P71/AN17/INT1
P11/AD09/TOT1 86 45 P70/AN16/INT0
P12/AD10/SIN3/NT11R 87 44 Vss
P13/AD11/SOT3 88 43 P67/AN7/PPGE(F)
P14/AD12/SCK3 89 42 P66/AN6/PPGC(D)
Vcc 90 QFP - 100 41 P65/AN5/PPGA(B)
Vss 91 40 P64/AN4/PPG8(9)
X1 92 39 P63/AN3/PPG6(7)
X0 93 38 P62/AN2/PPG4(5)
P15/AD13 94 37 P61/AN1/PPG2(3)
P16/AD14 95 36 P60/AN0/PPG0(1)
P17/AD15 96 35 AVss
P20/A16/PPG9(8) 97 34 AVRL
P21/A17/PPGB(A) 98 33 AVRH
P22/A18/PPGD(C) 99 32 AVcc
P23/A19/PPGF(E) 100 31 P57/AN15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P32/WRL/WR/INT10R
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P42/IN6/INT9R
P36/RDY/OUT6
P37/CLK/OUT7
Vcc
Vss
C
P43/IN7
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
P40/X0A*
P41/X1A*
(FPT-100P-M06)
* : MB90F867A, MB90867A : X0A, X1A

MB90F867AS, MB90867AS : P40, P41
(Continued)
6
MB90860A Series
(Continued)
(TOP VIEW)
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P82/SIN0/TIN2/INT14R
P84/SCK0/INT15R
P83/SOT0/TOT2
P00/AD00/INT8
P77/AN23/INT7
P76/AN22/INT6
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
PA0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P87/SCK1
P86/SOT1
P85/SIN1
MD0
RST
PA 1
Vss
Vcc
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P01/AD01/INT9 76 50 MD1
P02/AD02/INT10 77 49 MD2
P03/AD03/INT11 78 48 P75/AN21/INT5
P04/AD04/INT12 79 47 P74/AN20/INT4
P05/AD05/INT13 80 46 P73/AN19/INT3
P06/AD06/INT14 81 45 P72/AN18/INT2
P07/AD07/INT15 82 44 P71/AN17/INT1
P10/AD08/TIN1 83 43 P70/AN16/INT0
P11/AD09/TOT1 84 42 Vss
P12/AD10/SIN3/NT11R 85 41 P67/AN7/PPGE(F)
P13/AD11/SOT3 86 40 P66/AN6/PPGC(D)
P14/AD12/SCK3 87 LQFP - 100 39 P65/AN5/PPGA(B)
Vcc 88 38 P64/AN4/PPG8(9)
Vss 89 37 P63/AN3/PPG6(7)
X1 90 36 P62/AN2/PPG4(5)
X0 91 35 P61/AN1/PPG2(3)
P15/AD13 92 34 P60/AN0/PPG0(1)
P16/AD14 93 33 AVss
P17/AD15 94 32 AVRL
P20/A16/PPG9(8) 95 31 AVRH
P21/A17/PPGB(A) 96 30 AVcc
P22/A18/PPGD(C) 97 29 P57/AN15
P23/A19/PPGF(E) 98 28 P56/AN14
P24/A20/IN0 99 27 P55/AN13
P25/A21/IN1 100 26 P54/AN12/TOT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P32/WRL/WR/INT10R
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P34/HRQ/OUT4
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P43/IN7
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P42/IN6//INT9R
P44/SDA0/FRCK0
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P31/RD/IN5
P33/WRH
P35/HAK/OUT5
(FPT-100P-M05)
* : MB90F867A, MB90867A : X0A, X1A

MB90F867AS, MB90867AS : P40, P41
7
MB90860A Series
■ PIN DESCRIPTION
Pin No. Circuit
Pin name Function
LQFP100*2 QFP100*1 type
90 92 X1 Oscillation output
A
91 93 X0 Oscillation input
52 54 RST E Reset input
General purpose I/O. The register can be set to select whether
P00 to P07 to use a pull-up resistor. This function is enabled in single-chip
mode.
75 to 82 77 to 84 G
I/O pins for 8 lower bits of the external address/data bus.
AD00 to AD07
This function is enabled when the external bus is enabled.
INT8 to INT15 External interrupt request input pins for INT8 to INT15.
P10 to use a pull-up resistor. This function is enabled in single-chip
mode.
83 85 G
I/O pin for bit 8 of the external address/data bus.
AD08
TIN1 Event input pin for the reload timer 1
mode.
84 86 G
AD09
TOT1 Output pin for the reload timer 1
mode.
85 87 N I/O pin for bit 10 of the external address/data bus.
AD10
SIN3 Serial data input pin for UART3
INT11R Sub external interrupt request input pin for INT11
mode.
86 88 G
AD11
SOT3 Serial data output pin for UART3
mode.
87 89 G
AD12
SCK3 Clock I/O pin for UART3
(Continued)
8
MB90860A Series
Pin No. Circuit

Pin name Function
LQFP100* 2
QFP100* 1 type
mode.
92 94 G
AD13
SIN4 Serial data input pin for UART4 (MB90V340 only)
mode.
93 95 G
AD14
SOT4 Serial data output pin for UART4 (MB90V340 only)
mode.
94 96 G
I/O pin for bit 15 of the external address/data bus. This function
AD15
is enabled when the external bus is enabled.
SCK4 Clock I/O pin for UART4 (MB90V340 only)
to use a pull-up resistor.In external bus mode, the pin is
P20 to P23
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
Output pins for A16 to A19 of the external address bus. When
95 to 98 97 to 100 G
the corresponding bit in the external address output control
A16 to A19
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
PPG9,PPGB,
Output pins for PPGs
PPGD,PPGF
to use a pull-up resistor.In external bus mode, the pin is
P24 to P27
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
99 to 2 1 to 4 G Output pins for A20 to A23 of the external address bus. When
the corresponding bit in the external address output control
A20 to A23
register (HACR) is 0, the pins are enabled as high address
output pins (A20 to A23).
IN0 to IN3 Data sample input pins for input captures ICU0 to ICU3
General purpose I/O.The register can be set to select whether
P30 to use a pull-up resistor.This function is enabled in single-chip
mode.
3 5 G
Address latch enable output pin. This function is enabled when
ALE
the external bus is enabled.
IN4 Data sample input pin for input capture ICU4
(Continued)
9
MB90860A Series
Pin No. Circuit

Pin name Function
2
LQFP100* QFP100* 1 type
General purpose I/O.The register can be set to select whether to
P31 use a pull-up resistor.This function is enabled in single-chip
mode.
4 6 G
Read strobe output pin for the data bus. This function is enabled
RD
when the external bus is enabled.
General purpose I/O. The register can be set to select whether to
P32 use a pull-up resistor. This function is enabled either in single-chip
mode or with the WR/WRL pin output disabled.
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR/WRL pin output are en-
5 7 WRL / WR G abled. WRL is used to write-strobe 8 lower bits of the data bus in
16-bit access while WR is used to write-strobe 8 bits of the data
bus in 8-bit access.
RX2 RX input pin for CAN2 Interface (MB90V340 only)
P33 use a pull-up resistor.This function is enabled either in single-chip
mode or with the WRH pin output disabled.
Write strobe output pin for the 8 higher bits of the data bus. This
6 8 G
function is enabled when the external bus is enabled, when the
WRH
external bus 16-bit mode is selected, and when the WRH output
pin is enabled.
TX2 TX Output pin for CAN2 (MB90V340 only)
mode or with the hold function disabled.
7 9 G
Hold request input pin. This function is enabled when both the ex-
HRQ
ternal bus and the hold function are enabled.
OUT4 Waveform output pin for output compare OCU4
mode or with the hold function disabled.
8 10 G
Hold acknowledge output pin. This function is enabled when both
HAK
the external bus and the hold function are enabled.
mode or with the external ready function disabled.
9 11 G
Ready input pin. This function is enabled when both the
RDY
external bus and the external ready function are enabled.
(Continued)
10
MB90860A Series
Pin No. Circuit

Pin name Function
LQFP100* 2
QFP100* 1 type
P37 to use a pull-up resistor. This function is enabled either in
single-chip mode or with the CLK output disabled.
10 12 G
CLK output pin. This function is enabled when both the
CLK
external bus and CLK output are enabled.
P40 , P41 F General purpose I/O (devices with S-suffix)
11 to 12 13 to 14
X0A , X1A B Oscillator input pins for sub-clock (devices without S-suffix)
P42 General purpose I/O
16 18 F
RX1 RX input pin for CAN1 (MB90V340 (S) only)
17 19 IN7 F Data sample input pin for input capture ICU7
TX1 TX Output pin for CAN1 (MB90V340 (S) only)
18 20 SDA0 H Serial data I/O pin for I2C 0
FRCK0 Input for the 16-bit I/O Timer 0
19 21 SCL0 H Serial clock I/O pin for I2C 0
FRCK1 Input for the 16-bit I/O Timer 1
20 22 H
SDA1 Serial data I/O pin for I2C 1
21 23 H
SCL1 Serial clock I/O pin for I2C 1
22 24 AN8 O Analog input pin for the A/D converter
23 25 AN9 I Analog input pin for the A/D converter
TIN3 Event input pin for the reload timer 3
(Continued)
11
MB90860A Series
Pin No. Circuit

Pin name Function
LQFP100* 2
QFP100* 1 type
27 29 I
AN13 Analog input pin for the A/D converter
P56 to P57 General purpose I/O
28, 29 30, 31 AN14 to AN15 J Analog input pin for the A/D converter
DA00 to DA01 D/A converter analog output pins (MB90V340 only)
AN0 to AN7 Analog input pins for the A/D converter
34 to 41 36 to 43 I
PPG0, 2, 4, 6,
Output pins for PPGs
8, A, C, E
43 to 48, 45 to 50,
AN16 to AN23 I Analog input pins for the A/D converter (devices with C-suffix)
53, 54 55, 56
INT0 to INT7 External interrupt request input pins for INT0 to INT7
TIN0 Event input pin for the reload timers 0
55 57 F
ADTG Trigger input pin for the A/D converter
56 58 F
CKOT Output pin for the clock monitor
57 59 M
TIN2 Event input pin for the reload timers 2
58 60 SOT0 F Serial data output pin for UART0
59 61 SCK0 F Clock I/O pin for UART0
60 62 M
61 63 F
(Continued)
12
MB90860A Series
(Continued)
Pin No. Circuit
Pin name Function
LQFP100* 2
QFP100* 1 type
62 64 F
65 to 68 67 to 70 F
PPG1, 3, 5, 7 Output pins for PPGs
69 to 72 71 to 74 F Waveform output pins for output compares OCU0 to OCU3.

OUT0 to
This function is enabled when the OCU enables waveform
OUT3
output.
PA0 General purpose I/O
73 75 RX0 F RX input pin for CAN0 (MB90V340 (s) only)
PA1 General purpose I/O
74 76 F
TX0 TX Output pin for CAN0 (MB90V340 (s) only)
30 32 AVCC K Vcc power input pin for analog circuits
Reference voltage input for the A/D Converter. This power
31 33 AVRH L supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AVCC.
32 34 AVRL K Lower reference voltage input for the A/D Converter
33 35 AVSS K Vss power input pin for analog circuits
Input pins for specifying the operating mode. The pins must be
50, 51 52, 53 MD1, MD0 C
directly connected to Vcc or Vss
Input pin for specifying the operating mode. The pins must be
49 51 MD2 D
directly connected to Vcc or Vss.
13 15
63 65 VCC  Power (3.5 V to 5.5 V) input pins
88 90
14 16
42 44
VSS  Power (0V) input pins
64 66
89 91
This is the power supply stabilization capacitor pin. It should be
15 17 C K connected to a higher than or equal to 0.1 µF ceramic capaci-
tor.
*1 : FPT-100P-M06
*2 : FPT-100P-M05
13
MB90860A Series
■ I/O CIRCUIT TYPE

Type Circuit Remarks
Oscillation circuit
X1 • High-speed oscillation feedback
Xout
resistor = approx. 1 MΩ
A X0
Standby control signal
X1A Oscillation circuit

Xout
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
B X0A
Standby control signal
Mask ROM and EVA device:

• CMOS Hysteresis input pin
C R
Hysteresis
inputs Flash device:
• CMOS input pin
Mask ROM and EVA device:

R
Hysteresis
• CMOS Hysteresis input pin
inputs • Pull-down resistor valule: approx. 50 kΩ
D
Pull-down
Flash device:
Resistor
• CMOS input pin
• No Pull-down
CMOS Hysteresis input pin

• Pull-up resistor valule: approx. 50 kΩ
Pull-up
E Resistor
R
Hysteresis
inputs
(Continued)
14
MB90860A Series

• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the stand-
Pout
by-time input shutdown function)
• Automotive input (With the standby-time
Nout input shutdown function)
F R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown

pull-up control
Pout • Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
Nout
shutdown function)
R • Programmalble pullup resistor: 50 kΩ
G approx.
Hysteresis inputs
Automotive inputs
TTL input
Standby control for

input shutdown

Pout
H R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
15
MB90860A Series

• CMOS hysteresis inputs (With the standby-
Pout
time input shutdown function)
• Automotive input (With the standby-time in-
Nout put shutdown function)
• A/D analog input
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input

• D/A analg output
Pout
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
Nout • Automotive input (With the standby-time in-
put shutdown function)
R
Hysteresis inputs
J
Automotive inputs
Standby control for
input shutdown
Analog input
Analog output
• Power supply input protection circuit
• A/D converter reference voltage power

ANE
supply input pin, with the protection circuit
• Flash devices do not have a protection cir-
L AVR cuit against VCC for pin AVRH
ANE
(Continued)
16
MB90860A Series
(Continued)
Pout
• CMOS inputs (With the standby-time
M R
CMOS inputs
Automotive inputs
Standby control for
input shutdown

pull-up control
Pout • Automotive input (With the standby-time
• TTL input (With the standby-time input
Nout
shutdown function)
R Programmable pullup registor:50 kΩ
N
approx.
CMOS inputs
Automotive inputs
TTL input
Standby control for

input shutdown

Pout
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
17
MB90860A Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on(External-bus mode)
• Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90860A Series
X0
Open X1
4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
18
MB90860A Series
5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc Vss
Vss
MB90860A
Vcc Series Vcc
Vss
Vss Vcc
7. Pull-up/down resistors
The MB90860A Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
19
MB90860A Series
11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
VDD5
VDD3
Port0 to Port3
Port0 to 3 outputs Port0 to 3 outputs = Hi-Z

might be unstable
15. Flash security Function

The security byte is located in the area of the flash memory.
If protection code 01H is written in the security byte, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
Flash memory size Address for security byte
MB90F867A (S) Embedded 1 Mbit Flash Memory FE0001H
20
MB90860A Series
■ BLOCK DIAGRAMS
MB90V340(S)
X0,X1
X0A,X1A* Clock
16LX
RST Controller CPU
IO Timer 0 FRCK0
RAM 30 K
Input
Capture IN7 to IN0
8 ch
Output
Compare OUT7 to OUT0
8 ch
Prescaler
5 ch IO Timer 1
FRCK1
SOT4 to SOT0 CAN

UART RX2 to RX0
SCK4 to SCK0 5 ch Controller
3 ch TX2 to TX0
SIN4 to SIN0
AVCC 16-bit Reload TIN3 to TIN0

AVSS Timer 4 ch TOT3 to TOT0
AN23 to AN0 10-bit ADC
AVRH 24 ch
AVRL AD15 to AD00
ADTG A23 to A16
FMC-16 Bus
ALE
RD
10-bit External
DA01, DA00 DAC WRL
Bus
2 ch Interface WRH
HRQ
8/16-bit HAK
PPGF to PPG0 PPG RDY
16 ch CLK
SDA1, SDA0 I2C

Interface INT15 to INT8
SCL1, SCL0 External (INT15R to INT8R)
2 ch
Interrupt
INT7 to INT0
DMAC
Clock
Monitor CKOT
* : Only for MB90V340 ( without ‘S’ Suffix )
21
MB90860A Series
MB90F867A (S) , MB90867A (S)

X0,X1
X0A,X1A* Clock
16LX
RST Controller CPU
RAM IO Timer 0 FRCK0

6K
Input
Capture IN7 to IN0
8 ch
ROM/Flash
128 K Output
Compare OUT7 to OUT0
8 ch
Prescaler
4 ch IO Timer 1
FRCK1
SOT3 to SOT0
UART
SCK3 to SCK0 4 ch
SIN3 to SIN0
AVCC 16-bit Reload TIN3 to TIN0

AVSS Timer 4 ch TOT3 to TOT0
AN15 to AN0 10-bit ADC
AN23 to AN16 16/24 ch
AVRH AD15 to AD00
AVRL A23 to A16
FMC-16 Bus
ADTG ALE
RD
External
WRL
Bus
Interface WRH
8/16-bit HRQ
PPGF to PPG0 PPG
16 ch HAK
RDY
CLK
SDA1, SDA0 I2C
Interface
SCL1, SCL0 2 ch INT15 to INT8
External (INT15R to INT8R)
Interrupt
INT7 to INT0
DMAC
Clock
Monitor CKOT
* : Only for devices without ‘S’ Suffix
22
MB90860A Series
■ MEMORY MAP
MB90867A (S)
MB90V340 (S)
MB90F867A (S)
FFFFFFH FFFFFFH
ROM(FF bank) ROM(FF bank)
FF0000H FF0000H
FEFFFFH FEFFFFH
ROM(FE bank) ROM(FE bank)
FE0000H FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH ROM 00FFFFH ROM

008000H
(Image of FF bank) (Image of FF bank)
008000H
007FFFH 007FFFH
Peripheral Peripheral
007900H 007900H
0078FFH
RAM 30 K
0018FFH
RAM 6 K
000100H 000100H
0000EFH 0000EFH
Peripheral Peripheral
000000H 000000H
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
23
MB90860A Series
■ I/O MAP
Abbrevia-
Address Register Access Resource name Initial value
tion
00H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXX
0AH Port A Data Register PDRA R/W Port A XXXXXXXX
0BH Port 5 Analog Input Enable Register ADER5 R/W Port 5, A/D 11111111
0CH Port 6 Analog Input Enable Register ADER6 R/W Port 6, A/D 11111111
0DH Port 7 Analog Input Enable Register ADER7 R/W Port 7, A/D 11111111
0EH Input Level Select Register 0 ILSR0 R/W Ports 00000000
0FH Input Level Select Register 1 ILSR1 R/W Ports 00000000
10H Port 0 Direction Register DDR0 R/W Port 0 00000000
1AH Port A Direction Register DDRA R/W Port A 00000100
1BH Reserved
1CH Port 0 Pullup Control Register PUCR0 R/W Port 0 00000000
1DH Port 1 Pullup Control Register PUCR1 R/W Port 1 00000000
1EH Port 2 Pullup Control Register PUCR2 R/W Port 2 00000000
1FH Port 3 Pullup Control Register PUCR3 R/W Port 3 00000000
(Continued)
24
MB90860A Series
Abbrevia-
tion
20H Serial Mode Register 0 SMR0 W, R/W 00000000
21H Serial Control Register 0 SCR0 W, R/W 00000000
RDR0/
22H Reception/Transmission Data Register 0 R/W 00000000
TDR0
23H Serial Status Register 0 SSR0 R, R/W 00001000
UART0
R, W,
24H Extended Communication Control Reg. 0 ECCR0 000000XX
R/W
25H Extended Status/Control Register 0 ESCR0 R/W 00000100
26H Baud Rate Generator Register 00 BGR00 R/W 00000000
27H Baud Rate Generator Register 01 BGR01 R/W 00000000
RDR1/
2AH Reception/Transmission Data Register 1 R/W 00000000
TDR1
2BH Serial Status Register 1 SSR1 R, R/W 00001000
UART1
R, W,
2CH Extended Communication Control Reg. 1 ECCR1 000000XX
R/W
2DH Extended Status Control Register 1 ESCR1 R/W 00000100
2EH Baud Rate Generator Register 10 BGR10 R/W 00000000
2FH Baud Rate Generator Register 11 BGR11 R/W 00000000
30H PPG 0 Operation Mode Control Register PPGC0 W, R/W 0X000XX1
31H PPG 1 Operation Mode Control Register PPGC1 W, R/W 16-bit PPG 0/1 0X000001
32H PPG 01 Clock Select Register PPG01 R/W 000000X0
33H Reserved
37H Reserved
3AH PPG 4 and PPG 5 Clock Select Register PPG45 R/W 000000X0
Program Address Detection Control Address Match
3BH PACSR1 R/W 00000000
Status Register 1 Detection 1
3CH PPG 6 Operation Mode Control Register PPGC6 W, R/W 0X000XX1
3DH PPG 7 Operation Mode Control Register PPGC7 W, R/W 16-bit PPG 6/7 0X000001
3EH PPG 67 Clock Select Register PPG67 R/W 000000X0
3FH Reserved
(Continued)
25
MB90860A Series
Abbrevi-
ation
43H Reserved
44H PPG A Operation Mode Control Register PPGCA W, R/W 0X000XX1
45H PPG B Operation Mode Control Register PPGCB W, R/W 16-bit PPG A/B 0X000001
46H PPG AB Clock Select Register PPGAB R/W 000000X0
47H Reserved
48H PPG C Operation Mode Control Register PPGCC W, R/W 0X000XX1
49H PPG D Operation Mode Control Register PPGCD W, R/W 16-bit PPG C/D 0X000001
4AH PPG CD Clock Select Register PPGCD R/W 000000X0
4BH Reserved
4CH PPG E Operation Mode Control Register PPGCE W, R/W 0X000XX1
4DH PPG F Operation Mode Control Register PPGCF W, R/W 16-bit PPG E/F 0X000001
4EH PPG EF Clock Select Register PPGEF R/W 000000X0
4FH Reserved
50H Input Capture Control Status Register 0/1 ICS01 R/W 00000000
Input Capture 0/1
51H Input Capture Edge Register 0/1 ICE01 R/W, R XXX0X0XX
Input Capture 2/3
53H Input Capture Edge Register 2/3 ICE23 R XXXXXXXX
Input Capture 4/5
55H Input Capture Edge Register 4/5 ICE45 R XXXXXXXX
Input Capture 6/7
57H Input Capture Edge Register 6/7 ICE67 R/W, R XXX000XX
58H Output Compare Control Status Register 0 OCS0 R/W 0000XX00
Output Compare 0/1
59H Output Compare Control Status Register 1 OCS1 R/W 0XX00000
5AH Output Compare Control Status Register 2 OCS2 R/W 0000XX00
Output Compare 2/3
5BH Output Compare Control Status Register 3 OCS3 R/W 0XX00000
5CH Output Compare Control Status Register 4 OCS4 R/W 0000XX00
Output Compare 4/5
5DH Output Compare Control Status Register 5 OCS5 R/W 0XX00000
5EH Output Compare Control Status Register 6 OCS6 R/W 0000XX00
Output Compare 6/7
5FH Output Compare Control Status Register 7 OCS7 R/W 0XX00000
(Continued)
26
MB90860A Series
Abbrevia-
tion
60H Timer Control Status Register 0 TMCSR0 R/W 00000000
16-bit Reload Timer 0
61H Timer Control Status Register 0 TMCSR0 R/W XXXX0000
68H A/D Control Status Register 0 ADCS0 R/W 000XXXX0
69H A/D Control Status Register 1 ADCS1 R/W 0000000X
6AH A/D Data Register 0 ADCR0 R 00000000
A/D Converter
6BH A/D Data Register 1 ADCR1 R XXXXXX00
6CH ADC Setting Register 0 ADSR0 R/W 00000000
6DH ADC Setting Register 1 ADSR1 R/W 00000000
6EH Reserved
6FH ROM Mirroring Register ROMM W ROM Mirror XXXXXXX1
70H to 8FH Reserved
90H to 9AH Reserved
DMA Descriptor Channel Specification
9BH DCSR R/W 00000000
Register
DMA
9CH DMA Status Register L DSRL R/W 00000000
9DH DMA Status Register H DSRH R/W 00000000
Program Address Detection Control Address Match
9EH PACSR0 R/W 00000000
Status Register 0 Detection 0
9FH Delayed Interrupt/Release DIRR R/W Delayed Interrupt XXXXXXX0
Low Power
A0H Low-power Mode Control Register LPMCR W, R/W 00011000
Controller
Low Power
A1H Clock Selection Register CKSCR R, R/W 11111100
Controller
A2H, A3H Reserved
A4H DMA Stop Status Register DSSR R/W DMA 00000000
A5H Automatic Ready Function Select Reg. ARSR W 0011XX00
External Memory
A6H External Address Output Control Reg. HACR W 00000000
Access
A7H Bus Control Signal Selection Register ECSR W 0000000X
A8H Watchdog Control Register WDTC R, W Watchdog Timer XXXXX111
A9H Timebase Timer Control Register TBTC W, R/W Time Base Timer 1XX00100
(Continued)
27
MB90860A Series
Abbrevia-
tion
AAH Watch Timer Control Register WTC R, R/W Watch Timer 1X001000
ABH Reserved
ACH DMA Enable Register L DERL R/W 00000000
DMA
ADH DMA Enable Register H DERH R/W 00000000
Flash Control Status Register
AEH (FlashDevices only. FMCS R, R/W Flash Memory 000X0000
Otherwise reserved)
AFH Reserved
B0H Interrupt Control Register 00 ICR00 W, R/W 00000111
Interrupt Controller
BAH Interrupt Control Register 10 ICR10 W, R/W 00000111
BBH Interrupt Control Register 11 ICR11 W, R/W 00000111
BCH Interrupt Control Register 12 ICR12 W, R/W 00000111
BDH Interrupt Control Register 13 ICR13 W, R/W 00000111
BEH Interrupt Control Register 14 ICR14 W, R/W 00000111
BFH Interrupt Control Register 15 ICR15 W, R/W 00000111
C0H D/A Converter Data 0 DAT0 R/W XXXXXXXX
C1H D/A Converter Data 1 DAT1 R/W XXXXXXXX
D/A Converter
C2H D/A Control 0 DACR0 R/W XXXXXXX0
C3H D/A Control 1 DACR1 R/W XXXXXXX0
C4H, C5H Reserved
External Interrupt Request Enable
C6H ENIR0 R/W 00000000
Register 0
C7H External Interrupt Request Register 0 EIRR0 R/W External Interrupt 0 XXXXXXXX
C8H External Interrupt Level Register 0 ELVR0 R/W 00000000
C9H External Interrupt Level Register 0 ELVR0 R/W 00000000
(Continued)
28
MB90860A Series
Abbrevia-
tion
External Interrupt Request Enable
CAH ENIR1 R/W 00000000
Register 1
CBH External Interrupt Request Register 1 EIRR1 R/W XXXXXXXX
CCH External Interrupt Level Register 1 ELVR1 R/W External Interrupt 1 00000000
CDH External Interrupt Level Register 1 ELVR1 R/W 00000000
External Interrupt Source Select
CEH EISSR R/W 00000000
Register
CFH PLL/Subclock Control Register PSCCR W PLL XXXX0000
D0H DMA Buffer Address Pointer L BAPL R/W XXXXXXXX
D1H DMA Buffer Address Pointer M BAPM R/W XXXXXXXX
D2H DMA Buffer Address Pointer H BAPH R/W XXXXXXXX
D3H DMA Control Register DMACS R/W XXXXXXXX
DMA
D4H I/O Register Address Pointer L IOAL R/W XXXXXXXX
D5H I/O Register Address Pointer H IOAH R/W XXXXXXXX
D6H Data Counter L DCTL R/W XXXXXXXX
D7H Data Counter H DCTH R/W XXXXXXXX
D8H Serial Mode Register 2 SMR2 W, R/W 00000000
D9H Serial Control Register 2 SCR2 W, R/W 00000000
Reception/Transmission Data RDR2/
DAH R/W 00000000
Register 2 TDR2
DBH Serial Status Register 2 SSR2 R, R/W 00001000
UART2
Extended Communication Control R, W,
DCH ECCR2 000000XX
Register 2 R/W
DDH Extended Status/Control Register 2 ESCR2 R/W 00000100
DEH Baud Rate Reload Register 20 BGR20 R/W 00000000
DFH Baud Rate Reload Register 21 BGR21 R/W 00000000
E0H to EFH Reserved
F0H to FFH External
(Continued)
29
MB90860A Series
Abbrevia-
tion
7900H Reload Register L0 PRLL0 R/W XXXXXXXX
7901H Reload Register H0 PRLH0 R/W XXXXXXXX
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
790AH Reload Register L5 PRLL5 R/W XXXXXXXX
790BH Reload Register H5 PRLH5 R/W XXXXXXXX
790CH Reload Register L6 PRLL6 R/W XXXXXXXX
790DH Reload Register H6 PRLH6 R/W XXXXXXXX
16-bit PPG 6/7
790EH Reload Register L7 PRLL7 R/W XXXXXXXX
790FH Reload Register H7 PRLH7 R/W XXXXXXXX
16-bit PPG 8/9
7914H Reload Register LA PRLLA R/W XXXXXXXX
7915H Reload Register HA PRLHA R/W XXXXXXXX
16-bit PPG A/B
7916H Reload Register LB PRLLB R/W XXXXXXXX
7917H Reload Register HB PRLHB R/W XXXXXXXX
7918H Reload Register LC PRLLC R/W XXXXXXXX
7919H Reload Register HC PRLHC R/W XXXXXXXX
16-bit PPG C/D
791AH Reload Register LD PRLLD R/W XXXXXXXX
791BH Reload Register HD PRLHD R/W XXXXXXXX
791CH Reload Register LE PRLLE R/W XXXXXXXX
791DH Reload Register HE PRLHE R/W XXXXXXXX
16-bit PPG E/F
791EH Reload Register LF PRLLF R/W XXXXXXXX
791FH Reload Register HF PRLHF R/W XXXXXXXX
7920H Input Capture Data Register 0 IPCP0 R XXXXXXXX
Input Capture 0/1
(Continued)
30
MB90860A Series
Abbrevia-
tion
Input Capture 2/3
Input Capture 4/5
792AH Input Capture Data Register 5 IPCP5 R XXXXXXXX
792BH Input Capture Data Register 5 IPCP5 R XXXXXXXX
792CH Input Capture Data Register 6 IPCP6 R XXXXXXXX
792DH Input Capture Data Register 6 IPCP6 R XXXXXXXX
Input Capture 6/7
792EH Input Capture Data Register 7 IPCP7 R XXXXXXXX
792FH Input Capture Data Register 7 IPCP7 R XXXXXXXX
7930H Output Compare Register 0 OCCP0 R/W XXXXXXXX
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
793AH Output Compare Register 5 OCCP5 R/W XXXXXXXX
793BH Output Compare Register 5 OCCP5 R/W XXXXXXXX
793CH Output Compare Register 6 OCCP6 R/W XXXXXXXX
793DH Output Compare Register 6 OCCP6 R/W XXXXXXXX
Output Compare 6/7
793EH Output Compare Register 7 OCCP7 R/W XXXXXXXX
793FH Output Compare Register 7 OCCP7 R/W XXXXXXXX
7940H Data Register 0 TCDT0 R/W 00000000
I/O Timer 0
7942H Control Status Register 0 TCCSL0 R/W 00000000
7943H Control Status Register 0 TCCSH0 R/W 0XXXXXXX
I/O Timer 1
7946H Control Status Register 1 TCCSL1 R/W 00000000
7947H Control Status Register 1 TCCSH1 R/W 0XXXXXXX
(Continued)
31
MB90860A Series
Abbrevia-
tion
7948H TMR0/ R/W 16-bit Reload XXXXXXXX
Timer Register 0/Reload Register 0
7949H TMRLR0 R/W Timer 0 XXXXXXXX
794AH TMR1/ R/W 16-bit Reload XXXXXXXX
794BH TMRLR1 R/W Timer 1 XXXXXXXX
794CH TMR2/ R/W 16-bit Reload XXXXXXXX
794DH TMRLR2 R/W Timer 2 XXXXXXXX
794EH TMR3/ R/W 16-bit Reload XXXXXXXX
794FH TMRLR3 R/W Timer 3 XXXXXXXX
RDR3/
7952H Reception/Transmission Data Register 3 R/W 00000000
TDR3
7953H Serial Status Register 3 SSR3 R, R/W 00001000
UART3
R, W,
7954H Extended Communication Control Reg. 3 ECCR3 000000XX
R/W
7955H Extended Status/Control Register 3 ESCR3 R/W 00000100
7956H Baud Rate Reload Register 30 BGR30 R/W 00000000
7957H Baud Rate Reload Register 31 BGR31 R/W 00000000
RDR4/
795AH Reception/Transmission Data Register 4 R/W 00000000
TDR4
795BH Serial Status Register 4 SSR4 R, R/W 00001000
UART4
R, W,
795CH Extended Communication Control Reg. 4 ECCR4 000000XX
R/W
795DH Extended Status/Control Register 4 ESCR4 R/W 00000100
795EH Baud Rate Reload Register 40 BGR40 R/W 00000000
795FH Baud Rate Reload Register 41 BGR41 R/W 00000000
7960H to
Reserved
796BH
796CH Clock Output Enable Register CLKR R/W Clock Monitor XXXX0000
796DH to
Reserved
796FH
(Continued)
32
MB90860A Series
Abbrevia-
tion
7970H I2C Bus Status Register 0 IBSR0 R 00000000
7971H 2
I C Bus Control Register 0 IBCR0 W, R/W 00000000
7972H ITBAL0 R/W 00000000
I2C 10-bit Slave Address Register 0
7973H ITBAH0 R/W 00000000
7974H ITMKL0 R/W I2C Interface 0 11111111
I2C 10-bit Slave Address Mask Register 0
7975H ITMKH0 R/W 00111111
7976H 2
I C 7-bit Slave Address Register 0 ISBA0 R/W 00000000
2
7977H I C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111
7978H 2
I C Data Register 0 IDAR0 R/W 00000000
7979H,
Reserved
797AH
797BH I2C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111
797CH to
Reserved
797FH
7980H I2C Bus Status Register 1 IBSR1 R 00000000
7981H I2C Bus Control Register 1 IBCR1 W, R/W 00000000
7982H ITBAL1 R/W 00000000
I2C 10-bit Slave Address Register 1
7983H ITBAH1 R/W 00000000
2
7984H ITMKL1 R/W I C Interface 1 11111111
I2C 10-bit Slave Address Mask Register 1
7985H ITMKH1 R/W 00111111
7986H 2
I C 7-bit Slave Address Register 1 ISBA1 R/W 00000000
7987H I2C 7-bit Slave Address Mask Register 1 ISMK1 R/W 01111111
7988H I2C Data Register 1 IDAR1 R/W 00000000
7989H,
Reserved
798AH
798BH I2C Clock Control Register 1 ICCR1 R/W I2C Interface 1 00011111
798CH to
Reserved
79C1H
79C2H Clock Modulator Control Register CMCR R, R/W Clock Modulator 0001X000
79C3H to
Reserved
79DFH
(Continued)
33
MB90860A Series
(Continued)
Abbrevia-
tion
79E0H Program Address Detection Register 0 PADR0 R/W XXXXXXXX
Address Match
Detection 0
79E9H to
Reserved
79EFH
79F0H Program Address Detection Register 3 PADR3 R/W XXXXXXXX
Address Match
Detection 1
79F9H to
Reserved
7FFFH
Notes : • Initial value of “X” represents unknown value.

• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.
34
MB90860A Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control
EI2OS DMA ch Interrupt vector
Interrupt cause register
clear number
Number Address Number Address
Reset N  #08 FFFFDCH  
INT9 instruction N  #09 FFFFD8H  
Exception N  #10 FFFFD4H  
(Reserved) N  #11 FFFFD0H
ICR00 0000B0H
(Reserved) N  #12 FFFFCCH
Input Capture 6 Y1  #13 FFFFC8H
ICR01 0000B1H
Input Capture 7 Y1  #14 FFFFC4H
I2C0 N  #15 FFFFC0H
ICR02 0000B2H
(Reserved) N  #16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8H
ICR03 0000B3H
ICR04 0000B4H
16-bit Reload Timer 3 Y1  #20 FFFFACH
PPG 0/1/4/5 N  #21 FFFFA8H
ICR05 0000B5H
PPG 2/3/6/7 N  #22 FFFFA4H
PPG 8/9/C/D N  #23 FFFFA0H
ICR06 0000B6H
PPG A/B/E/F N  #24 FFFF9CH
Time Base Timer N  #25 FFFF98H
ICR07 0000B7H
External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N  #27 FFFF90H
ICR08 0000B8H
External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8CH
A/D Converter Y1 5 #29 FFFF88H
ICR09 0000B9H
I/O Timer 0 / I/O Timer 1 N  #30 FFFF84H
Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80H
ICR10 0000BAH
Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH
Input Capture 0 to 3 Y1 8 #33 FFFF78H
ICR11 0000BBH
Output Compare 2/3/6/7 Y1 9 #34 FFFF74H
UART 0 RX Y2 10 #35 FFFF70H
ICR12 0000BCH
UART 0 TX Y1 11 #36 FFFF6CH
UART 1 RX / UART 3 RX Y2 12 #37 FFFF68H
ICR13 0000BDH
UART 1 TX / UART 3 TX Y1 13 #38 FFFF64H
(Continued)
35
MB90860A Series
(Continued)
Interrupt control
EI2OS DMA ch Interrupt vector
Interrupt cause register
clear number
Number Address Number Address
UART 2 RX / UART 4 RX Y2 14 #39 FFFF60H
ICR14 0000BEH
UART 2 TX / UART 4 TX Y1 15 #40 FFFF5CH
Flash Memory N  #41 FFFF58H
ICR15 0000BFH
Delayed interrupt N  #42 FFFF54H
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
36
MB90860A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Rating
Parameter Symbol Unit Remarks
Min Max
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1
Power supply voltage
AVRH, AVCC ≥ AVRH, AVCC ≥ AVRL,
VSS − 0.3 VSS + 6.0 V
AVRL AVRH ≥ AVRL
Input voltage VI VSS − 0.3 VSS + 6.0 V *2
Output voltage VO VSS − 0.3 VSS + 6.0 V *2
Maximum Clamp Current ICLAMP −4.0 +4.0 mA *4
Total Maximum Clamp Current Σ|ICLAMP|  40 mA *4
“L” level maximum output current IOL  15 mA *3
“L” level average output current IOLAV  4 mA *3
“L” level maximum overall output current ΣIOL  100 mA *3
“L” level average overall output current ΣIOLAV  50 mA *3
“H” level maximum output current IOH  −15 mA *3
“H” level average output current IOHAV  −4 mA *3
“H” level maximum overall output current ΣIOH  −100 mA *3
“H” level average overall output current ΣIOHAV  −50 mA *3
Power consumption PD  340 mW MB90F867A
Operating temperature TA −40 +105 °C
Storage temperature TSTG −55 +150 °C
(Continued)
37
MB90860A Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting P-ch
resistance
+B input (0 V to 16 V)
N-ch
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90860A Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Value
Parameter Symbol Unit Remarks
Min Typ Max
4.0 5.0 5.5 V Under normal operation
Under normal operation, when not
VCC, 3.5 5.0 5.5 V using the A/D converter and not
Power supply voltage Flash programming.
AVCC
4.5 5.0 5.5 V When External bus is used.
3.0  5.5 V Maintains RAM data in stop mode
Use a ceramic capacitor or capac-
itor of better AC characteristics.
Smooth capacitor CS 0.1  1.0 µF
Capacitor at the VCC should be
greater than this capacitor.
Operating temperature TA −40  +105 °C
CS
C Pin Connection Diagram
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB90860A Series
3. DC Characteristics
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Sym- Value
Parameter Pin Condition Unit Remarks
bol Min Typ Max
Port inputs if CMOS
hysteresis input levels
VIHS   0.8 VCC  VCC + 0.3 V are selected (except
UART SIN input pins
and I2C input pins)
Port inputs if
VIHA   0.8 VCC  VCC + 0.3 V AUTOMOTIVE input
levels are selected
Input H Port inputs if TTL input
voltage VIHT   2.0  VCC + 0.3 V
levels are selected
(At VCC =
UART SIN inputs if
5 V ± 10%)
VIHS   0.7 VCC  VCC + 0.3 V CMOS input levels are
selected
I2C Port inputs if CMOS
VIHI   0.7 VCC  VCC + 0.3 V hysteresis input levels
are selected
RST input pin (CMOS
VIHR   0.8 VCC  VCC + 0.3 V
hysteresis)
VIHM   VCC − 0.3  VCC + 0.3 V MD input pin
Port inputs if CMOS
hysteresis input levels
VILS   VSS − 0.3  0.2 VCC V are selected (except
UART SIN input pins
and I2C input pins)
Port inputs if
VILA   VSS − 0.3  0.5 VCC V AUTOMOTIVE input
levels are selected
Input L Port inputs if TTL
voltage VILT   VSS − 0.3  0.8 V
input levels are selected
(At VCC =
UART SIN inputs if
5 V ± 10%)
VILS   VSS − 0.3  0.3 VCC V CMOS input levels are
selected
I2C Port inputs if CMOS
VILI   VSS − 0.3  0.3 VCC V hysteresis input levels
are selected
RST input pin (CMOS
VILR   VSS − 0.3  0.2 VCC V
hysteresis)
VILM   VSS − 0.3  VSS + 0.3 V MD input pin
Output H Normal VCC = 4.5 V,
VOH VCC − 0.5   V
voltage outputs IOH = −4.0 mA
Output H I2C current VCC = 4.5 V,
VOHI VCC − 0.5   V
voltage outputs IOH = −3.0 mA
Output L Normal VCC = 4.5 V,
VOL   0.4 V
voltage outputs IOL = 4.0 mA
Output L I2C current VCC = 4.5 V,
VOLI   0.4 V
voltage outputs IOL = 3.0 mA
(Continued)
40
MB90860A Series
(Continued)
(TA = −40 °C to +105, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Sym- Value
bol Min Typ Max
Input leak current IIL  VCC = 5.5 V, VSS < VI < VCC −1  1 µA
P00 to P07,
P10 to P17,
Pull-up
RUP P20 to P27,  25 50 100 kΩ
resistance
P30 to P37,
RST
Pull-down Except Flash
RDOWN MD2  25 50 100 kΩ
resistance devices
VCC = 5.0 V,
Internal frequency : 24 MHz,  55 70 mA MB90F867A
At normal operation.
VCC = 5.0 V,
ICC Internal frequency : 24 MHz,  70 85 mA MB90F867A
At writing FLASH memory.
VCC = 5.0 V,
Internal frequency : 24 MHz,  75 90 mA MB90F867A
At erasing FLASH memory.
VCC = 5.0 V,
ICCS Internal frequency : 24 MHz,  25 35 mA MB90F867A
At Sleep mode.
VCC = 5.0 V,
ICTS Internal frequency : 2 MHz,  0.3 0.8 mA MB90F867A
At Main Timer mode
VCC = 5.0 V,
Power supply Internal frequency : 24 MHz,
current* ICTSPLL6 VCC  4 7 mA MB90F867A
At PLL Timer mode,
external frequency = 4 MHz
VCC = 5.0V
Internal frequency: 8 kHz,
ICCL  170 360 µA MB90F867A
At sub operation
TA = +25°C
VCC = 5.0V
ICCLS  20 50 µA MB90F867A
At sub sleep
TA = +25°C
VCC = 5.0V
ICCT  10 35 µA MB90F867A
At watch mode
TA = +25°C
VCC = 5.0 V,
ICCH At Stop mode,  7 25 µA MB90F867A
TA = +25°C
Other than C, AVCC, AVSS,
Input capacity CIN   5 15 pF
AVRH, AVRL, VCC, VSS,
* : Current values are tentative. They are subject to change without notice according to improvements in the
characteristics. The power supply current is measured with an external clock.
41
MB90860A Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Parameter Symbol Pin Unit Remarks
Min Typ Max
When using an oscillation
X0, X1 3  16 MHz
circuit
fC
Clock frequency When using an external
X0 3  24 MHz
clock*
fCL X0A, X1A — 32.768 100 kHz
When using an oscillation
X0, X1 62.5  333 ns
circuit
tCYL
Clock cycle time When using an external
X0 41.67  333 ns
clock
tCYLL X0A, X1A 10 30.5 — µs
PWH, PWL X0 10   ns Duty ratio is about 30% to
Input clock pulse width
PWHL, PWLL X0A 5 15.2  µs 70%.
Input clock rise and fall time tCR, tCF X0   5 ns When using external clock
Internal operating clock fCP  1.5  24 MHz When using main clock
frequency (machine clock) fCPL  8.192 50 kHz When using sub clock
Internal operating clock tCP  41.67  666 ns When using main clock
cycle time (machine clock) tCPL  20 122.1  µs When using sub clock
* : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
tCYL
0.8 VCC
X0
0.2 VCC
PWH PWL
tCF tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL PWLL
tCF tCR
Clock Timing
42
MB90860A Series
• Guaranteed PLL operation range

Guaranteed operation range
Guaranteed PLLL operation range (CS2=1)

Power supply voltage VCC (V)
5.5
Guaranteed A/D converter
operation range
4.5
3.5
Guaranteed PLL operation range (CS=0)
1.5 4 8 20 24
Machine clock fCP (MHz)
Guaranteed operation range of MB90860A Series
CS2 (bit0 in PSCCR reigster) = 0

Guaranteed operation frequency range*2
×4 ×3 ×2
(CS=11) (CS=10) (CS=01) ×1
20 (CS=00)
16
12 ×1/2
(PLL off)
4.0
1.5
3 4 8 12 16 20 24
1
External clock fC (MHz)
CS2 (bit0 in PSCCR reigster) = 1

Guaranteed operation frequency range*2
×6 ×4 ×2
(CS=10) (CS=01) (CS=00)
24
16
12 ×1/2
(PLL off)
4.0
1.5
3 4 8 12 16 24
1
External clock fC (MHz)
*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 20 MHz.
*2 : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
External clock frequency and Machine clock frequency
43
MB90860A Series
(2) Reset Standby Input

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Value
Min Max
500  ns Under normal operation
In Stop mode, Sub Clock
Reset input Oscillation time of oscillator*
tRSTL RST  ns mode, Sub Sleep mode
time + 100 µs
and Watch mode
100  µs In Time Timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC 0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC 0.2 VCC
90% of
amplitude
X0
Internal operation
clock 100 m s
Oscillation time
of oscillator Oscillation stabilization
waiting time
Instruction execution
Internal reset
44
MB90860A Series
(3) Power On Reset

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Value
Parameter Symbol Pin Condition Unit Remarks
Min Max
Power on rise time tR VCC 0.05 30 ms

Power off time tOFF VCC 1  ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V 0.2 V 0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
3V 50 mV/ms maximum.
Holds RAM data
VSS
45
MB90860A Series
(4) Bus Timing (Read)

(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Sym- Value
bol Min Max
ALE pulse width tLHLL ALE tCP/2 − 10  ns
ALE, A23 to
Valid address ⇒ ALE ↓ time tAVLL A16, AD15 tCP/2 − 15  ns
to AD00
ALE, AD15
ALE ↓ ⇒ Address valid time tLLAX tCP/2 − 15  ns
to AD00
A23 toA16,
Valid address ⇒ RD ↓ time tAVRL AD15 to tCP − 15  ns
AD00, RD
A23 to A16,
Valid address ⇒ Valid data
tAVDV AD15 to  5 tCP/2 − 40 ns
input
AD00
RD pulse width tRLRH RD  3 tCP/2 − 20  ns
RD, AD15 to
RD ↓ ⇒ Valid data input tRLDV  3 tCP/2 − 50 ns
AD00
RD, AD15 to
RD ↑ ⇒ Data hold time tRHDX 0  ns
AD00
RD ↓ ⇒ ALE ↑ time tRHLH RD, ALE tCP/2 − 15  ns
RD, A23 to
RD ↑ ⇒ Address valid time tRHAX tCP/2 − 10  ns
A16
A23 to A16,
Valid address ⇒ CLK ↑ time tAVCH AD15 to tCP/2 − 15  ns
AD00, CLK
RD ↓ ⇒ CLK ↑ time tRLCH RD, CLK tCP/2 − 15  ns
ALE ↓ ⇒ RD ↓ time tLLRL ALE, RD tCP/2 − 15  ns
46
MB90860A Series
tRLCH
tAVCH
2.4 V 2.4 V
CLK
tLLAX
tAVLL tRHLH
2.4 V 2.4 V 2.4 V

ALE
0.8 V
tLHLL
tAVRL tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
2.4 V 2.4 V
A23 to A16
0.8 V 0.8 V
tRLDV
tRHDX
tAVDV
2.4 V 2.4 V VIH VIH
AD15 to AD00 Address Read data
0.8 V 0.8 V VIL VIL
47
MB90860A Series
(5) Bus Timing (Write)

Value
Min Max
A23 to A16,
Valid address ⇒ WR ↓ time tAVWL AD15 to AD00, tCP−15  ns
WR
WR pulse width tWLWH WR 3 tCP/2 − 20  ns
Valid data output ⇒ WR ↑ AD15 to AD00,
tDVWH 3 tCP/2 − 20  ns
time WR

AD15 to AD00,
WR ↑ ⇒ Data hold time tWHDX 15  ns
WR
A23 to A16,
WR ↑ ⇒ Address valid time tWHAX tCP/2 − 10  ns
WR
WR ↑ ⇒ ALE ↑ time tWHLH WR, ALE tCP/2 − 15  ns
WR ↓ ⇒ CLK ↑ time tWLCH WR, CLK tCP/2 − 15  ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V 2.4 V
A23 to A16
0.8 V 0.8 V
tDVWH tWHDX
2.4 V 2.4 V 2.4 V

AD15 to AD00 Address Write data
0.8 V 0.8 V 0.8 V
48
MB90860A Series
(6) Ready Input Timing

Sym- Test Value
Parameter Pin Units Remarks
bol Condition Min Max
RDY setup time tRYHS RDY 45  ns

RDY hold time tRYHH RDY 0  ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS tRYHH
VIH VIH
RDY
When WAIT is not used.
RDY
When WAIT is used. VIL
49
MB90860A Series
(7) Hold Timing

Value
Parameter Symbol Pin Condition Units Remarks
Min Max
Pin floating ⇒ HAK ↓
tXHAL HAK 30 tCP ns
time

HAK ↑ time ⇒ Pin valid
tHAHV HAK tCP 2 tCP ns
time
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4V
HAK
0.8V
tXHAL tHAHV
High-Z
2.4V 2.4V
Each pin
0.8V 0.8V
50
MB90860A Series
(8) UART0/1/2/3/4
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Min Max
Serial clock cycle time tSCYC SCK0 to SCK4 8 tCP  ns
SCK0 to SCK4,
SCK ↓ → SOT delay time tSLOV −80 +80 ns
SOT0 to SOT4 Internal clock
operation output
SCK0 to SCK4, pins are
Valid SIN → SCK ↑ tIVSH 100  ns
SIN0 to SIN4 CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SCK ↑ → Valid SIN hold time tSHIX 60  ns
SIN0 to SIN4
Serial clock “H” pulse width tSHSL SCK0 to SCK4 4 tCP  ns
Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP  ns
SCK0 to SCK4, External clock
SCK ↓ → SOT delay time tSLOV  150 ns
SOT0 to SOT4 operation output
pins are
SCK0 to SCK4,
Valid SIN → SCK ↑ tIVSH CL = 80 pF + 1 TTL. 60  ns
SIN0 to SIN4
SCK0 to SCK4,
SCK ↑ → Valid SIN hold time tSHIX 60  ns
SIN0 to SIN4
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns)
tSCYC
2.4 V
SCK
0.8 V 0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH tSHIX
VIH VIH
SIN
VIL VIL
Internal Shift Clock Mode
51
MB90860A Series
tSLSH tSHSL
VIH VIH
SCK
VIL VIL
tSLOV
2.4 V
SOT
0.8 V
tIVSH tSHIX
VIH VIH
SIN
VIL VIL
External Shift Clock Mode
(9) Trigger Input Timing

Value
Min Max
INT0 to INT15,
tTRGH
Input pulse width INT0R to INT15R,  5 tCP  ns
tTRGL
ADTG
VIH VIH
INT0 to INT15, VIL VIL
INT0R to INT15R,
ADTG tTRGH tTRGL
52
MB90860A Series
(10) Timer Related Resource Input Timing

Value
Min Max
tTIWH TIN0 to TIN3
Input pulse width  4 tCP  ns
tTIWL IN0 to IN7
VIH VIH
TIN0 to TIN3, VIL VIL
IN0 to IN7
tTIWH tTIWL
(11) Timer Related Resource Output Timing

(TA = –40° to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Value
Min Max
TOT0 to TOT3,
CLK ↑ ⇒ TOUT change time tTO  30  ns
PPG0 to PPGF
2.4 V
CLK
TOT0 to TOT3, 2.4 V

PPG0 to PPGF 0.8 V
tTO
53
MB90860A Series
(12) I2C Timing

(TA = –40°C to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Standard-mode Fast-mode*4
Parameter Symbol Condition Unit
Min Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition
tHDSTA 4.0  0.6  µs
SDA ↓ → SCL ↓
“L” width of the SCL clock tLOW 4.7  1.3  µs
“H” width of the SCL clock tHIGH 4.0  0.6  µs
Set-up time for a repeated START condition
tSUSTA 4.7  0.6  µs
SCL ↑ → SDA ↓
R = 1.7 kΩ,
Data hold time C = 50 pF*1
tHDDAT 0 3.45*2 0 0.9*3 µs
SCL ↓ → SDA ↓ ↑
Data set-up time
tSUDAT 250  100  ns
SDA ↓ ↑ → SCL ↑
Set-up time for STOP condition
tSUSTO 4.0  0.6  µs
SCL ↑ → SDA ↑
Bus free time between a STOP and START
tBUS 4.7  1.3  µs
condition
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tLOW tSUDAT tHDSTA tBUS
SCL
tHIGH
tHDSTA tHDDAT tSUSTA tSUSTO
54
MB90860A Series
5. A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Min Typ Max
Resolution     10 bit
Total error     ±3.0 LSB
Nonlinearity error     ±2.5 LSB
Differential
    ±1.9 LSB
nonlinearity error
Zero reading
VOT AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
voltage
Full scale reading
VFST AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
voltage
1.0 4.5 V ≤ AVCC ≤ 5.5 V
Compare time    16,500 µs
2.0 4.0 V ≤ AVCC < 4.5 V
0.5 4.5 V ≤ AVCC ≤ 5.5 V
Sampling time    ∞ µs
1.2 4.0 V ≤ AVCC < 4.5 V
Analog port input
IAIN AN0 to AN23 −0.3  +0.3 µA
current
Analog input
VAIN AN0 to AN23 AVRL  AVRH V
voltage range
Reference  AVRH AVRL + 2.7  AVCC V
voltage range  AVRL 0  AVRH − 2.7 V
Power supply IA AVCC  3.5 7.5 mA
current IAH AVCC   5 µA *
Reference IR AVRH  600 900 µA
voltage current IRH AVRH   5 µA *
Offset between
 AN0 to AN23   4 LSB
input channels
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH − AVRL becomes smaller.
55
MB90860A Series
6. Definition of A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.
Non linearity : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
error and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
linearity error value.
Total error : Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Zero reading : Input voltage which results in the minimum conversion value.
voltage
Full scale : Input voltage which results in the maximum conversion value.
reading voltage
Total error
3FF
1.5 LSB
3FE Actual conversion
characteristics
3FD
{1 LSB × (N − 1) + 0.5 LSB}
Digital output
004 VNT
(Actually-measured value)
003
Actual conversion
002 characteristics
Ideal characteristics
001
0.5 LSB
AVRL AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}

Total error of digital output “N” = [LSB]
1 LSB
AVRH − AVRL
1 LSB = (Ideal value) [V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
56
MB90860A Series
(Continued)
Non linearity error Differential linearity error

Ideal
3FF characteristics
Actual conversion
characteristics
3FE
{1 LSB × (N − 1) N+1 Actual conversion
+ VOT } characteristics
3FD VFST (actual
measurement
value)
Digital output
Digital output
N
VNT (actual
004 measurement value)
V (N + 1) T
Actual conversion N−1 (actual measurement
003
characteristics value)
VNT
002 (actual measurement value)
Ideal characteristics Actual conversion
001 N−2
characteristics
VOT (actual measurement value)
AVRL AVRH AVRL AVRH
Analog input Analog input
VNT − {1 LSB × (N − 1) + VOT}

Non linearity error of digital output N = [LSB]
1 LSB
V (N+1) T − VNT
Differential linearity error of digital output N = −1 LSB [LSB]
1 LSB
VFST − VOT
1 LSB = [V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
57
MB90860A Series
7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
if the output inpedance exceeds 1.5 kΩ, set a longer sampling time or add an external capacitor compensate
the output inpedance. About setting of sampling time, please refer to hardware manual of MB90860A series.
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
Analog input R
Comparator
4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF

4.0 V ≤ AVCC < 4.5 V : R =: 13.6 kΩ, C =: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics

Value
Parameter Conditions Unit Remarks
Min Typ Max
Excludes programming
Sector erase time  1 15 s
prior to erasure
TA = +25 °C Excludes programming
Chip erase time  9  s
VCC = 5.0 V prior to erasure
Word (16 bit width) Except for the over head
 16 3,600 µs
programming time time of the system
Programs/Erase cycle  10,000   cycle
Flash Data Retention Average
20   Year *
Time TA = +85 °C
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
58
MB90860A Series
■ ORDERING INFORMATION
Part number Package Remarks
MB90F867APF
MB90F867ASPF 100-pin Plastic QFP
MB90867APF (FPT-100P-M06)
MB90867ASPF
MB90F867APFV
MB90F867ASPFV 100-pin Plastic LQFP
MB90867APFV (FPT-100P-M05)
MB90867ASPFV
MB90V340 299-pin Ceramic PGA
For evaluation
MB90V340S (PGA-299C-A01)
59
MB90860A Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
100-pin Plastic QFP
Note 2) Pins width and pins thickness including plating thickness.
(FPT-100P-M06)
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80 51
81 50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100 31 +0.35 0.25(.010)

3.00 –0.20
+.014
.118 –.008
(Mounting height)
1 30 0~8˚
0.65(.026) 0.32±0.05 0.17±0.06
0.13(.005) M
(.013±.002) (.007±.002)
0.80±0.20 0.25±0.20
"A" (.031±.008) (.010±.008)
0.88±0.15 (Stand off)
(.035±.006)
C 2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
60
MB90860A Series
(Continued)
Note 1) * : These dimensions do not include resin protrusion.
100-pin Plastic LQFP
Note 2) Pins width and pins thickness include plating thickness.
(FPT-100P-M05)
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75 51
76 50
0.08(.003)
Details of "A" part
+0.20 +.008
1.50 –0.10 .059 –.004
INDEX (Mounting height) 0.10±0.10
(.004±.004)
(Stand off)
100 26
0˚~8˚
"A" 0.50±0.20 0.25(.010)
(.020±.008)
1 25 0.60±0.15
0.50(.020) 0.20±0.05 0.145±0.055 (.024±.006)
0.08(.003) M
(.008±.002) (.0057±.0022)
C 2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
61
MB90860A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0405
 FUJITSU LIMITED Printed in Japan

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16-bit Proprietary Microcontroller

F2MC-16LX MB90860A Series

100-pin Plastic QFP 100-pin Plastic LQFP

*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

* : MB90F867A, MB90867A : X0A, X1A

* : MB90F867A, MB90867A : X0A, X1A

Pin No. Circuit

Pin No. Circuit

Pin No. Circuit

Pin No. Circuit

69 to 72 71 to 74 F Waveform output pins for output compares OCU0 to OCU3.

■ I/O CIRCUIT TYPE

Standby control signal

X1A Oscillation circuit

Standby control signal

Mask ROM and EVA device:

Mask ROM and EVA device:

CMOS Hysteresis input pin

Type Circuit Remarks

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

Standby control for

• CMOS level output(IOL = 3 mA, IOH = −3 mA)

Type Circuit Remarks

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

• Power supply input protection circuit

• A/D converter reference voltage power

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

Standby control for

• CMOS level output(IOL = 4 mA, IOH = −4 mA)

4. Precautions for when not using a sub clock signal

5. Notes on during operation of PLL clock mode

11. Notes on Energization

Port0 to 3 outputs Port0 to 3 outputs = Hi-Z

15. Flash security Function

SOT4 to SOT0 CAN

AVCC 16-bit Reload TIN3 to TIN0

SDA1, SDA0 I2C

* : Only for MB90V340 ( without ‘S’ Suffix )

MB90F867A (S) , MB90867A (S)

RAM IO Timer 0 FRCK0

AVCC 16-bit Reload TIN3 to TIN0

* : Only for devices without ‘S’ Suffix

00FFFFH ROM 00FFFFH ROM

Notes : • Initial value of “X” represents unknown value.

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

• Input/output equivalent circuits

C Pin Connection Diagram

• Guaranteed PLL operation range

Guaranteed PLLL operation range (CS2=1)

CS2 (bit0 in PSCCR reigster) = 0

CS2 (bit0 in PSCCR reigster) = 1

(2) Reset Standby Input

Under normal operation:

0.2 VCC 0.2 VCC

(3) Power On Reset

(4) Bus Timing (Read)

2.4 V 2.4 V 2.4 V