Date Unit Topic Subtopic

10.05.2021 4 Introduction  Timing metrics

 Memory
elements
 Static Vs
Dynamic
memory
 Latches Vs
Registers
Static Latches and  Bistability
Registers Principle
 SR Flip Flops
11.05.2021 4 Static Latches and  MUX based
Registers Latches
 Master-Slave
Ede Triggered
Register
Dynamic Latches and  True Single-
Registers Phase Clocked
Register
12.05.2021 Dynamic Latches and  True Single-
Registers Phase Clocked
Register
Alternate Register Style  Pipelining
 Latch Vs Register
Pipelining
 NORA CMOS
13.5.2021 Non bistable  Schmitt trigger
sequential circuits  Monostable Seq.
circuits
 Astable Circuits
Timing considerations  Clock
Uncertainty
 Clock skew and
jitter
 Impact of jitter
14.05.2021 Memory  Classification
 Memory
architectures
 Memory building
blocks
15.05.2021 Implementation  Introduction
strategies  Full custom
and Semi-
custom design
 Standard cell
design
 ASIC design
flow