Sub: VLSI Design 4-1 ECE

Descriptive Questions

1. a) Explain the nMOS transistor Fabrication Process with the help of neat sketches.
b) Discuss the steps involved in BiCMOS technology.
2. a)Derive the relationship between drain to source current I ds verses drain to source voltage Vds in non-
saturated and saturated region.
b) Explain the various symbols used in layout diagram notation? Draw the Layout diagram of CMOS
NOR?
3. a) Design a stick diagram for two input nMOS NAND Gate.
b) Discuss the transistor related design rule (orbit 2µm CMOS).
c) Explain the limits of miniaturization on scaling.
4. a) Explain the issues involved in driving large capacitor loads in VLSI circuit regions.
b) Calculate the gate capacitance value of 5 mm technology minimum size transistor with gate to
channel value is 4 x 10-4 pF/mm2 .

MCQ

1. What is the disadvantage of the MOS device? ( )

a) limited current sourcing
b) limited voltage sinking
c) limited voltage sourcing
d) unlimited current sinking

2. Electronics are characterized by ( )

a) low cost
b) low weight and volume
c) reliability
d) all of the mentioned

3. What are the features of BiCMOS? ( )

a) low input impedance
b) high packing density
c) high input impedance
d) bidirectional

4. nMOS fabrication process is carried out in ____________. ( )

a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals

5. As source drain voltage increases, channel depth_________. ( )

a) increases
b) decreases
c) logarithmically increases
d) exponentially increases

6. n and p transistors are separated by using __________. ( )

a) differentiation line
b) separation line
c) demarcation line
d) black line

7. The dopants are introduced in the active areas of silicon by: ( )

a) Diffusion process
b) Ion Implantaion process
c) Chemical Vapour Deposition
d) Either Diffusion or Ion Implantaion Process

8. The photoresist layer is exposed to________. ( )

a) visible light
b) ultraviolet light
c) infra red light
d) LED

9. Which contributes to the wiring capacitance? ( )

a) fringing fields
b) interlayer capacitance
c) peripheral capacitance
d) all of the mentioned

10. The spacing of interconnect is scaled by ( )

a) α
b) 1/α
c) α2
d) 1/α2

Fill in the blanks

1. In enhancement mode, device is in _________ condition.

2. Stick diagrams are those which convey layer information through_____.

3. The condition for non saturated region is____________.

4. ______ architecture is used to design VLSI .

5. Medium scale integration has ________ logic gates.

6. Cross section area is scaled by_________.

7. Greater the switching speed, _____ is the more.

8. _______ are scalable design rules?

9. The size of a transistor is usually defined in terms of its________

10. Which layer is used for power and signal lines?________