Simple Dynamic D-latch

Consider the dynamic D-latch circuit shown below

Assume VoD = 1.2 V, Vou 0 V, V = 0.54 V, VH= 0.66 V, VoH = 1.2

Vzn of MP= 048 V

CK=1 & Vin =VoH = 1.2 V V, = 12 -0.48 0.72 V> VIH of inv.
CK=0 V,starts to decrease because of charge leakage
If V, is lower than V = 0.66 V

The D-latch may produce an erroneous output

The charge stored in C, must be restored

Neeraj Tripathi

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 Basic Principles of Pass Transistor Circuits
Basic Pass Transistors

Vx
Vin=VoH
x

CK
CK

CK=1 The logic "1" or "0" transfer

CK=0 charge stored in C
Pass transistor: Only current path
The charge stored in the parasitic capacitor Cx
Determines the output level

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 94 Synchronous Dynamic Circuit Techniques

Dynamic Pass Transistor Circuits

nMOS pass transistors fed to non-overlapping clock , 2

se 2

Penod T (one oycle)

Neeraj Tripathi
 Dynamic Pass Transistor Circuits
Three stages of a pseudo nMOS dynamic shift register
circuit driven with two-phase clocking
During the active phase of ,
-The input level Vn is transferred into the input capacitance Cgt
During the active phase of O
The output voltage level of the first stage is transferred into
the second stage input capacitance Ginz

V
V L

Neeraj Tripathi
 Dynamic Pass Transistor Circuits
Three stages of a pseudo nMOS dynamic shift register
circuit driven with two-phase clocking
During the active phase of O,
-The input level Vin is transferred into the input capacitance Cint
During the active phase of 2
The output voltage level of the first stage is transferred into
the second stage input capacitance Gin2

in

Neeraj Tripathi
 Shift Register Circuit using
Enhancement-Load nMOS Inverters
Applying clock signal to the gate of the load transistor
instead of biasing the load transistors
Reduced power consumption and silicon area
- Called "Ratioed Logic" since Vo of each stage is determined by
the driver-to-load ratio
VDD VoD
1

Vout

out2 out3

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 General Circuit Structure of Ratioed
Synchronous Dynamic Logic
The overall power consumption
Dynamic enhancement-load logic « Pseudo nMOS logic

nMOS Logic
Stage 1
nMOS Logic
Stage 2

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 Dynamic CMOS Circuit Techniques
CMOS Transmission Gate-Logic

*****

L Stage Stage 2

Implementing CMOS
Transmission gate

Neeraj Tripathi
 CMOS Transmission Gate
Advantages
Smaller transfer time
N o threshold voltage drop
Disadvantages
Unavoidable skew and overlapping between CK and CK
K

Neeraj Tripathi
 Dynamic CMOS Logic
Operation based on
precharging and evaluating
Clock low The pMOS
Clock
charges the output node
=
high: Logic high Vout remains
->

Logic low-> Vout drops

chargeEvalaton charge

B2 od

F={444,+ B,B)

Neeraj Tripathi
 Cascading Problem
The case evaluating 1st and 2nd stages at the same time
Vout2 at the end of the evaluation phase will be erroneous
Alternative clocking scheme is required

out1 Vout2 Cnarg Evaluatio

1st stage 2nd stage

niMO
MOS
og logic
out1

Correct

Vou2 erroneoSSta

11
 (A

High-Performance Dynamic CMOS Circuits

Domino CMOS Logic
Problem in
cascading conventional dynamic CMOS stages
Unexpected discharge in Vout due to the propagation
delay of the stage before
Inserting an inverter buffer as a solution
-
Called "domino CMOS logic"

MOS
nMOS
MOS
 8-input Complex Logic Gate

HL CL

L c-L L

Using conventional CMOS logic Domino CMOS logic

13
Limitations of Domino CMOS Logic
static logic stages allowed
Only Even # of
I

Static ptes
(ven o f stages)

MMOS
nMOS

structure available
Only non-inverting
consumption due to clock
Large power
cause error
Large leakage may
Low noise margin
Charge sharing oblem Difficult synthesis