----------------- 2 BIT VEDIC MULTIOLIER--------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vedic2 is
Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end vedic2;

architecture Behavioral of vedic2 is

signal iq: std_logic_vector( 3 downto 0);
signal iq1:std_logic;
begin

iq(0)<= a(0) and b(0);

iq(1)<= (a(0)and b(1)) xor ( a(1) and b (0));
iq1<= (a(0)and b(1)) and( a(1) and b (0));
iq(2)<= iq1 xor (a(1) and b(1));
iq(3)<= iq1 and (a(1) and b(1));
q<= iq;
end Behavioral;
------------------ 4 BIT VEDIC MULTIPLIER-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vedic4 is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0));
end vedic4;

architecture Behavioral of vedic4 is

component vedic2 is
Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal iq1,iq2,iq3,iq4,iq5,iq6,iq7,iq8: std_logic_vector( 3 downto 0);
signal iq10,iq11,iq13,iq14,iq15: std_logic_vector( 5 downto 0);

begin
c1: vedic2 port map ( a(1 downto 0), b( 1 downto 0), iq1);
c2: vedic2 port map ( a(3 downto 2), b( 1 downto 0), iq2);
c3: vedic2 port map ( a(1 downto 0), b( 3 downto 2), iq3);
c4: vedic2 port map ( a(3 downto 2), b( 3 downto 2), iq4);
q( 1 downto 0)<= iq1( 1 downto 0);
iq5<= iq2+ ("00"& iq1(3 downto 2));
iq10<= "00"&iq3;
iq11<= iq4& "00";
iq13<= iq10+iq11;
iq14<= "00"& iq5;
iq15<= iq13+iq14;
q( 7 downto 2)<= iq15;
end Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vedic8 is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0));
end vedic8;

architecture Behavioral of vedic8 is

component vedic4 is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal iq1,iq2,iq3,iq4,iq5: std_logic_vector( 7 downto 0);
signal iq10,iq11,iq13,iq14,iq15: std_logic_vector( 11 downto 0);

begin
c1: vedic4 port map ( a(3 downto 0), b( 3 downto 0), iq1);
c2: vedic4 port map ( a(7 downto 4), b( 3 downto 0), iq2);
c3: vedic4 port map ( a(3 downto 0), b( 7 downto 4), iq3);
c4: vedic4 port map ( a(7 downto 4), b( 7 downto 4), iq4);
q( 3 downto 0)<= iq1( 3 downto 0);
iq5<= iq2+ ("0000"& iq1(7 downto 4));
iq10<= "0000"&iq3;
iq11<= iq4& "0000";
iq13<= iq10+iq11;
iq14<= "0000"& iq5;
iq15<= iq13+iq14;
q( 15 downto 4)<= iq15;
end Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vedic16 is
Port ( a,b : in STD_LOGIC_VECTOR (15 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end vedic16;

architecture Behavioral of vedic16 is

component vedic8 is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal iq1,iq2,iq3,iq4,iq5: std_logic_vector( 15 downto 0);
signal iq10,iq11,iq13,iq14,iq15: std_logic_vector( 23 downto 0);
begin
c1: vedic8 port map ( a(7 downto 0), b( 7 downto 0), iq1);
c2: vedic8 port map ( a(15 downto 8), b( 7 downto 0), iq2);
c3: vedic8 port map ( a(7 downto 0), b(15 downto 8), iq3);
c4: vedic8 port map ( a(15 downto 8), b(15 downto 8), iq4);
q( 7 downto 0)<= iq1( 7 downto 0);

iq5<= iq2+ ("00000000"& iq1(15 downto 8));

iq10<= "00000000"&iq3;
iq11<= iq4& "00000000";
iq13<= iq10+iq11;
iq14<= "00000000"& iq5;
iq15<= iq13+iq14;
q(31 downto 8)<= iq15;
end Behavioral;