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Article: Design and FPGA Implementation of High Speed Vedic Multiplier
Article: Design and FPGA Implementation of High Speed Vedic Multiplier
Article: Design and FPGA Implementation of High Speed Vedic Multiplier
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International Journal of Computer Applications (0975 – 8887)
Volume 90 – No 16, March 2014
2.1.2 How is it better than the conventional bit. It uses group propagate and generate as intermediate
signals which are given by the logic equations below:
. method?
𝑃𝑖: 𝑗 = 𝑃(𝑖: 𝑘 + 1) ∙ 𝑃(𝑘: 𝑗)
𝐺𝑖: 𝑗 = 𝐺(𝑖: 𝑘 + 1) + (𝑃 𝑖: 𝑘 + 1 ∙ 𝐺 𝑘: 𝑗 )
3. Post processing
It involves computation of sum bits. Sum bits are computed
by the logic given below:
c2 s2 s1 s0
4 bit KSA
Figure 4: 16-bit Kogge stone adder network [8] 0 0
(3-0)
ca1
This is an attempt to apprehend the functioning of KSA in (3-2)
three distinct steps: 4 bit KSA (1-0)
ca2
1. Pre processing
This step involves computation of generate and propagate HALF ADDER
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International Journal of Computer Applications (0975 – 8887)
Volume 90 – No 16, March 2014
𝟎𝟎𝟏𝟏𝟏𝟎𝟎𝟏 𝟐∗ 𝟎𝟎𝟎𝟏𝟏𝟎𝟎𝟏 𝟐
2. = 𝟎𝟎𝟎𝟎𝟎𝟏𝟎𝟏𝟏𝟎𝟎𝟏𝟎𝟎𝟎𝟏 𝟐
Output:
8
International Journal of Computer Applications (0975 – 8887)
Volume 90 – No 16, March 2014
IJCATM : www.ijcaonline.org 9