Dynamics of hole injection from p-GaN

drain of a hybrid drain embedded GIT

Cite as: AIP Advances 11, 055101 (2021); https://doi.org/10.1063/5.0049319
Submitted: 03 March 2021 . Accepted: 13 April 2021 . Published Online: 03 May 2021

Jinming Sun, Oliver Haeberlen, Clemens Ostermaier, Gerhard Prechtl, Ramakrishna Tadikonda, Eric
Persson, Reenu Garg, Mohamed Imam, Sameh Khalil, and Alain Charles

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Dynamics of hole injection from p -GaN drain

of a hybrid drain embedded GIT
Cite as: AIP Advances 11, 055101 (2021); doi: 10.1063/5.0049319
Submitted: 3 March 2021 • Accepted: 13 April 2021 •
Published Online: 3 May 2021

Jinming Sun,1,a) Oliver Haeberlen,2 Clemens Ostermaier,2 Gerhard Prechtl,2 Ramakrishna Tadikonda,3
Eric Persson, Reenu Garg, Mohamed Imam,1 Sameh Khalil,1 and Alain Charles5
1 4

AFFILIATIONS
1
Infineon Technologies Americas Corp., El Segundo, California 90245, USA
2
Infineon Technologies, Siemensstraße, 29500 Villach, Austria
3
Renesas Electronics America, Inc., Tempe, Arizona 85264, USA
4
Microchip Technologies, Chandler, Arizona 85224, USA
5
ABCs World Consulting, Manhattan Beach, California 90266, USA

a)
Author to whom correspondence should be addressed: jinming.sun@infineon.com

ABSTRACT
The addition of a p-GaN drain to a conventional gate-injection transistor (GIT), forming the so-called hybrid drain embedded GIT, is crucial
in the suppression of the dynamic Rdson. The DC leakage due to hole injection is limited to around 10 nA/mm at 600 V (25 ○ C). However, an
injected hole current of several amperes (W = 210 mm) has been observed during the hard switching event. To reconcile this difference over 6
orders of magnitude, a TCAD study is carried out to understand the dynamics of the hole injection and what leads to the difference between
the static and the transient current. According to the scenario played out by the present simulation model, the high concentration of carbon,
intentionally doped to control the vertical leakage, plays a crucial role in limiting the hole injection current to its DC level, while under fast
switching, the hole injection current can be very high due to a lag in response on the part of the carbon trap.
© 2021 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/5.0049319

I. INTRODUCTION blocking stage, limiting the dynamic Rdson increase to only 5% up to

GaN-based power devices have been recognized as the most
promising technology being able to displace Si in 600 V-rated
power applications for achieving high efficiency energy conver-
sion.1,2 This is due to the unique material advantages of GaN over
its Si counterpart, such as a high critical electric field (3.3 MV/cm)
and high channel mobility (∼2000 cm2 /Vs) of electrons.3–7 The het-
erojunction structure of GaN is by default a normally on FET
with a Two-Dimensional Electron Gas (2DEG) channel formed
at the AlGaN/GaN interface in equilibrium.8 To make it a nor-
mally off device, a p-GaN gate [gate injection transistor (GIT)]
has been devised to shift the threshold voltage (Vth ) into the
positive domain.9 A further advancement on the GIT came with
the use of p-GaN near the drain contact [hybrid drain embed-
ded GIT (HD-GIT)].10,11 It has been shown that during high
voltage switching, the hole injection from the p-GaN drain was
able to offset the negative charge formed by trapping during the
850 V.
However, using p-GaN drain injection to manage the dynamic
Rdson is contingent upon the condition that the hole injection cur-
rent (Idp ) does not present a huge increase in DC off-state Idss . The
DC leakage due to hole injection is measured to be 10 nA/mm at
600 V (25 ○ C).11 However, in the switching test, pulses of Idp with
a peak value as high as several amperes have been observed during
switching transitions (Fig. 2).
Before one can evaluate the device implication that such a high
current peak can have, it is imperative to have a clear understanding
of how this large current comes about, given that the DC injection
current is six orders of magnitude smaller.
To this end, a TCAD simulation12,13 is carried out to study
both the DC leakage and hard switching. By virtue of the device-
level details not attainable in measurement, the TCAD simulation
is the chosen tool that can reveal the triggering mechanism of the
hole injection, the carrier/trap interaction during the injection, the

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evolution of trap occupancy at DC, and the switching condition.

Explaining the paradox of the DC and switching Idp is the focus
of this study. As it turns out, the carbon-doped trap and its ioniza-
tion are crucial in limiting the hole injection current to its DC level.
However, the ionization process (trapping through hole capture) has
a finite characteristic capture time,14 below which the trapping will
not catch up with the injection, causing a large injection current of
the order of amperes to flow.

II. MEASUREMENT AND SIMULATION

The typical magnitude of the DC off-state drain leakage of a
commercial normally off HD-GIT (Wg = 210 mm) is 10 nA/mm at
Vd = 600 V and room temperature.11 At high drain bias, the hole
injection from the p-GaN near the drain dominates the total leakage.
During the switching, however, Idp from the HD-GIT can
exhibit very high current pulses. Using the switching circuitry shown
FIG. 2. Upper panel: Measured waveform of a HD-GIT during hard switching with
in Fig. 1, Panasonic has demonstrated that in a hard-switching con- low dV/dt around 10 V/ns. Lower panel: Idp (in purple) is the hole current injected
dition, Idp (Wg = 210 mm) (measured using a separate terminal as from the p-GaN drain measured by a special test structure with separate con-
shown in Fig. 2) can surge up to several amperes during turn on tact to the p-GaN drain. Wg = 210 mm (data from Panasonic Corporation, shared
and turn off transitions, before decaying into the sub-ampere regime information with Infineon).
(DC level) (Fig. 2). To understand how Idp of this magnitude is
possible, the switching waveform is studied via TCAD simulation
(Synopsys) using the same switching circuitry in Fig. 1. The DC output curves Id Vd from the TCAD are shown in
The TCAD model used has the basic ingredients of a conven- Fig. 4 for off (Vg = 0) and on (Vg = 3 V) at room and high tem-
tional GaN HEMT device model such as that used in Refs. 12 and 13. peratures (150 ○ C). In all cases, Idp does not exceed 10 μA/mm
An auto-compensation model15 is used for modeling carbon, in for Vd up to 600 V. However, a dynamic switching simulation (Vb
which a donor electron trap is coupled with an acceptor hole trap = 600 V) predicts an injected hole current (Idp ) of the order of sev-
(0.85 eV above the valence band16 and the hole Xsection σ h = 10−14 eral amperes, in agreement with Fig. 2. As shown in Fig. 5, Idp surges
cm2 ). A hole captured by the acceptor trap makes the pair single pos- at the on-to-off (off) and off-to-on (on) transitions and then decays
itively charged. With the shallower donor empty, the model is equiv- off with time. The significance of this result is that it corroborates the
alent to the recently proposed model of donor type hole trap.17 Other experimental finding that large hole injection in the range of many
method of modeling the trap (i.e., dominant acceptor) may result amperes is possible during the switching for a device with very small
in some slightly quantitative difference. A simplified non-uniform DC hole injection current.
spatial distribution of carbon has been employed in the simulation
with a high doping of 1018 cm−3 inside a thick AlGaN layer (Fig. 3).
The highly resistive doping layer is intended for vertical leakage
control.

FIG. 1. A switching circuitry used in measurement and TCAD simulation to produce FIG. 3. Carbon doping profile as a function of the depth of the epi. Trap energies
a hard switching condition. in auto-compensation are also illustrated.

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FIG. 4. Simulated DC Id and Idp at room temperature and 150 ○ C, Vg = 0, and
Vg = 3 V. In both off and on states, Idp does not exceed 10 μA/mm.
FIG. 5. Simulated switching waveform in the switching circuit of Fig. 1. In both on
transition (left) and off transition (right), a surge of injected hole current of the order
of amperes is seen. Wg = 210 mm.
III. ANALYSIS OF THE SWITCHING SIMULATION
According to our model, the hole starts to inject whenever a
forward bias is formed between the p-GaN drain (anode) and the
channel below it (cathode), a p-drain diode. This happens during the
off (channel depletion) and on transitions (Ohmic drop in the chan-
nel by Id ). After the initial injection, the hole current would have
flown unimpeded into the epi bulk if it were not for the suppressing
effect of a dynamic positive charge buildup. Upon injection, holes
are captured by the hole trap inside the epi and positive space charge
is formed, restricting further flow of holes. The faster the injection
(relative to the trap capture), the higher the peak injection current
will be. Idp decays to the DC value after positive space charge is
formed. The off (on-to-off) and on (off-to-on) transitions in Fig. 5
will now be examined separately in detail.
(a) Off transition: To understand the initiation and decay of the
hole injection during the off transition, three points in time,
t1 , t2 , and t3 , corresponding to before, during, and after the
AIP Advances 11, 055101 (2021); doi: 10.1063/5.0049319
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injection, respectively, are selected for inspection. Figure 6(a)
shows Vd , Id , and Idp at t1 , t2 , and t3 . Figure 6(b) shows the
hole density near the p-GaN drain at t1 , t2 , and t3 . The hole
density is initially low at t1 ; then becomes pronounced and
more widespread at t2 , flowing toward the source through
the parasitic Two-Dimensional Hole Gas (2DHG) channel
at the interface;18 and eventually decays toward a small DC
level at t3 . Figure 6(c) is a plot of the electron Fermi potential
along the channel close to the p-GaN drain. At t1 , before the
hole injection happens, the potential beneath the p-GaN edge
(indicated by the arrow) is very close to the drain potential,
which is also the potential of the p-GaN drain. Hence, the
forward bias of the p-drain diode (p-GaN drain/n channel)
is only 0.31 V, not enough for the diode to turn on. This is
due to the fact that at t1 , there is no significant depletion pen-
etration to the point of the channel below the p-GaN drain
edge (Vd = 120 V). Upon a further increase in Vd , the channel
below p-GaN is depleted and its potential trails behind Vd so
that a forward bias is established for the diode to turn on (at
t2 , the diode drop is 3.64 V). Large hole injection ensues and
positive space charge builds up as a result of hole capture by
the trap. Figure 6(d) shows the evolution of the space charge
at t1 , t2 , and t3 as a result of hole capture/release. At t1 , coming
from the on-state with a replenished n channel, the positive
space charge is low and close to be neutral. At the start of
injection at t2 , the hole flows unimpededly into the buffer due
to a lag in time needed to establish positive space charge. Pos-
itive space charge then begins to form due to capturing of the
injected hole by the trap at t2 and continues to increase until
t3 [Fig. 6(d)]. The well-formed positive space charge restricts
the hole flow and reduces Idp into its sub-ampere value
(Idp = 3 mA at t3 ). The forward bias of the p-drain diode at
t3 is also reduced to 3.35 V due to the increase in the positive
space charge [Fig. 6(c)]. Note that Idp peaks after Id begins to
decline [Fig. 6(a)], indicating that the decay of Idp is not the
result of a drop in Id .
(b) On transition: more complex is the transition from off to on.
Before large hole injection occurs at the transition, a weak
forward bias is already in place in the p-drain diode [2.12 eV
at t1 , Fig. 7(c)], inherited from the off phase with a small
sub-ampere current of Idp [t1 in Fig. 7(a)]. With turning-on
of the gate and an increase in Id at t2 , a large high Ohmic
drop is developed at the junction between the channel below
the p-GaN drain and the channel below the drain contact
[3.56 eV, t2 in Fig. 7(c)]. This causes an increase in forward
bias in the p-drain diode, leading to large hole injection. The
already ionized hole traps in the epi respond to the increased
hole flow by further ionizing the trap, leading to more pos-
itive space charge to restrict Idp [t3 at Figs. 7(a) and 7(d)].
Following this, the gate continues to turn on and Vd plum-
mets toward its on-state value so that the forward bias of
the p-drain diode will eventually be eliminated, causing Idp
to peter out. This latter factor however will not come into
play until Vd drops significantly. To emphasize the role of
the positive space charge in the Idp decay, t3 is chosen at
a point where Vd is still around blocking voltage (587 V)
but Idp is already on its decaying trajectory. At t3 , the mech-
anism of forward bias reduction by fully turning-on the
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FIG. 6. (a) Three points in time selected during off transition (before, during, and after the Idp surge). Upper panel: Vd and Idp . Lower panel: Id and Idp . (b) Hole density at t1 ,
t2 , and t3 . (c) Electron Fermi potential along the channel near the p-GaN drain at t1 , t2 , and t3 . The vertical arrows indicate the location of the p-GaN drain edge toward the
gate. (d) Space charge at t1 , t2 , and t3 .

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FIG. 7. (a) Three points in time selected during on transition (before, during, and after the Idp surge). Upper panel: Vd and Idp . Lower panel: Id and Idp . (b) Hole density at t1 ,
t2 , and t3 . (c) Electron Fermi potential along the channel near the p-GaN drain at t1 , t2 , and t3 . The vertical arrows indicate the location of the p-GaN drain edge toward the
gate. (d) Space charge at t1 , t2 , and t3 .

device has not come into play yet. To further separate the
two driving factors in Idp decay, a computer verification is
designed in Sec. IV, in which Idp transient will be simu-
lated by fast gate turning-on while keeping Vd constant at
600 V.
For the present trap model, the typical hole capture time is 10
ns at a hole density level of 1015 cm−3 (1/Vth p σ h , where Vth is the
thermal velocity of an electron at 107 cm/s, p is the hole density,
and σ h is the capture cross section to the valence band). This is the
typical peak injected hole density, for example, at t2 in Fig. 6(b). The

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FIG. 8. Simulated fast turn-off (average 58 V/ns) at 400 V. In simulation, Idp
contributes about 4 μJ, 17% of the total switching loss of 23 μJ.
complete switching time for a swing of 600 V is on the order of 100
ns for dv/dt = 6 V/ns, a fraction of which is the time to forward bias
the p-drain diode. To get a sense of the speed of the injection, the
time between Idp at its peak and at 10% of its peak during the Idp rise
is defined as the injection time. The injection time is seen as 21 ns for
the off transition [Fig.6(a)] and 6 ns for the on transition [Fig. 7(a)].
Both of these injection times are faster (for hole density lower than
1015 cm−3 ) or on the same magnitude of the capture time, causing
the initial unimpeded Idp to surge.
The p-drain diode is a distributed diode spanning the whole
length of the p-GaN. The hole density shown in Figs. 6(b) and 7(b)
shows a qualitative correlation with the surge and decay of the Idp .
Quantitatively, Idp at the peak (t2 ) and decay (t3 ) can be matched well
by the seemingly small but significant forward bias reduction from
t2 to t3 . If we model the p-drain diode as a compact non-ideal diode
using the value of Idp at t2 and t3 for each switching transition, an ide-
ality factor of 1.4 for off transition and 1.0 for on transition results.
Finally, the positive space charge formed by hole capture, formed
around 10 ns after injection, plays a pivotal role in the reduction
of the forward potential by 100 mV or so (electrostatically), leading
directly to the decay of the Idp transient from t2 to t3 . Idp is significant
before its formation (above ampere) and drops to the sub-ampere
regime after its formation at about 10 ns (the capture time) after the
injection peak.
Switching loss increases due to the Idp surge in switching transi-
tions. Take, for example, the turn-off edge of the simulated switching
waveform at Fig. 5 (dv/dt = 6 V/ns), and the loss ascribed to the Idp
transient is about 6% of the total switching loss (45 μJ out of 810 μJ).
In fast dv/dt switching (dv/dt = 45–58 V/ns and Vd = 400 V) where
the overlap of voltage and current is small, the percentage increases
to around 17% (4 μJ out of 23 μJ) (Fig. 8).
IV. COMPUTER VERIFICATION
A priori analysis of a hard-switching simulation has asserted
that the action of trapping inside the epi is the critical element in
the surge and decay of Idp during the switching transition. However,
the fact that both switching nodes (drain and gate) vary simultane-
ously during a switching transition complicates the analysis and adds
AIP Advances 11, 055101 (2021); doi: 10.1063/5.0049319
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FIG. 9. Virtual experiment: Id and Idp leakage as a function of Vd for different trap
energy levels above the valence band. Shallower traps exhibit a very high leakage
level. Room temperature and Vg = 0. Et = 0.85 eV is the nominal value used
throughout the rest of the simulation.
ambiguity to the elucidation of the mechanism. To reinforce the
conclusion drawn, computer verification is designed to mimic the
switching transition with only one node varying during a transition,
thus demonstrating the mechanism with a simpler waveform. The
focus is on the demonstration of the points established previously
from the switching simulation, albeit with a simpler construction.
Before we get into the computer verification itself, it is worth
mentioning some virtual experiments for consistency check. Since
the analysis shows that trap capture of the injected hole is the factor
that limits the Idp to its DC off state leakage, disabling the trap cap-
ture would lead to large Idp and device breakdown. This is indeed
the case: when trapping is disabled in the simulation (by zeroing
its capture cross section), Id and Idp go to a nearly vertically steep
breakdown at the point of hole injection. This breakdown happens
irrespective of the ramp rate of the Vd (even for dv/dt close to DC
sweep).
Another virtual experiment involves artificially moving the
acceptor trap’s energy level. This single parameter change involving
only the trap level can cause the DC hole injection leakage current
(and thus Id leakage) to rise more than 6 orders of magnitude into
FIG. 10. Idp has an OFF transient when Vd is pulsed to 600 V in 100 ns with Vg = 0.
After 200 ns, Vg is pulsed to 3 V in 100 ns and Idp has another ON transient with
Vd = 600 V. The decay is due to the formation of positive space charge via hole
capture/emission.
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the ampere range (Fig. 9). The trap level determines the level of hole to constrict it. This virtual experiment highlights the sensitive role
concentration at which the hole capture begins to take place. A shal- played by the trap.
lower acceptor trap level means that a much higher hole density The computer verification emulates the switching transition by
has to be developed before hole capture/positive ionization begins first ramping up Vd at a constant dv/dt (6 V/ns) while keeping the

FIG. 11. (a) Three points in time selected during Vd ramp (off transition emulation) (before, during, and after the Idp surge). Upper panel: Vd and Idp . Lower panel: Id and Idp .
(b) Hole density at t1 , t2 , and t3 . (c) Electron Fermi potential along the channel near the p-GaN drain at t1 , t2 , and t3 . The vertical arrows indicate the location of the p-GaN
drain edge toward the gate. (d) Space charge at t1 , t2 , and t3 .

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FIG. 12. (a) Three points in time selected during Vg ramp (on transition emulation) (before, during, and after the Idp surge). Upper panel: Vg and Idp . Lower panel: Id and Idp .
(b) Hole density at t1 , t2 , and t3 . (c) Electron Fermi potential along the channel near the p-GaN drain at t1 , t2 , and t3 . The vertical arrows indicate the location of the p-GaN
drain edge toward the gate. (d) Space charge at t1 , t2 , and t3 .

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Vg at zero. This is analogous to an off transition in the switch-
ing circuitry except that the channel is off all the time. Different
from the switching simulation where dv/dt is controlled by a gate
driver and inductive load, Vd ’s ramping is simply achieved by a
time-dependent voltage source. While in the switching circuitry, Id
is large (equal to the inductor current) throughout the off transition
(around 20 A) before reducing to leakage [Fig. 6(a)], Id in off tran-
sition emulation consists mainly of the capacitive charging current
before the hole injects. After hole injection, Id is made of the hole
injection current and hole-induced electron current by conductiv-
ity modulation.19 As seen in Fig. 10, Idp has a transient during the
Vd ramp with the peak value above ampere (the slow ramp version
of which produces only DC leakage), demonstrating the fast deple-
tion as the driving force for hole injection and the hole capture by
trapping as the mechanism for Idp ’s subsequent decay. The shape of
the Idp transient, however, is not identical to the transient in switch-
ing simulation (for example, Idp peaks at Vd around 260 V, while in
switching simulation, Idp peaks near the blocking voltage at 600 V).
There are two steps for the Idp decay: (a) a sharp decay after the
peak while Vd is still ramping up. This is clearly due to the for-
mation of the positive space charge. (b) A secondary drop into the
sub-ampere regime after Vd stops at 600 V. Vd ramping up is seen
here as a driving force for hole injection counteracted by the action
of positive space charge formation that resists the flow of the injected
hole.
After the Vd ramp, Vd is kept at 600 V for 200 ns before a
gate pulse of 3 V turns the gate on in 100 ns (Fig. 10, green curve).
This intends to emulate the on transition in the switching circuitry
where a sudden increase in Id forward-biases the p-drain diode and
starts another surge of hole injection. However, different from the
on transition in switching, Vd is kept constant at 600 V instead
of decreasing toward a low Ohmic value. The second Idp transient
seen here in Fig. 10 demonstrates the high Ohmic drop caused by
an increase in Id as the driving force for hole injection and the
hole capture by trapping as the mechanism for Idp ’s subsequent
decay. Formation of a low Ohmic channel as Vd drops, as happen-
ing during the on transition in switching, is not the cause of Idp
decay.
For analysis, we choose three points in time, t1 , t2 , and t3 , cor-
responding to before, during, and after the hole injection of the
emulated off transition, respectively [Fig. 11(a)]. t3 is chosen to be
at the first step of Idp decay. Figure 11(b) shows the hole density
near the p-GaN drain at t1 , t2 , and t3 . Figure 11(c) is a plot of the
electron Fermi potential along the channel near the p-GaN drain.
Figure 11(d) shows the evolution of the space charge at t1 , t2 , and t3
as a result of hole capture/release. The evolution of the hole density,
the electron Fermi level (the forward bias on the p-drain diode), and
the space charge during the Idp transient follows the same trend as
that of Fig. 6 corresponding to the off transition of a switching simu-
lation. Its simpler construction (just a fast Vd ramp), however, makes
more illustrative the previous assertion regarding the initiation and
decay of the hole injection.
Similar examination has been applied to the emulated-on tran-
sition [Fig. 12(a)]. In this case, the Idp peak at t2 is coincident with
the end of the gate pulse to 3 V, highlighting the Id increase as the
driving force of hole injection. Figure 12(c) of the electron Fermi
electron potential plot shows that the forward bias of the p-drain
diode has increased (from 3.08 to 3.62 eV) with increasing Id from
AIP Advances 11, 055101 (2021); doi: 10.1063/5.0049319
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t1 to t2 . From t2 to t3 , Id is nearly constant, so the effect of forma-
tion of positive space charge becomes more dominant, forcing the
Idp decay.
The role of the hole capture/positive space charge formation
[Fig. 12(d)] in the Idp decay, however, is seen more clearly with Vd
now being held constant throughout (not dropping toward a low
Ohmic value as in the case of switching).
V. CONCLUSION
The simulation study in conjunction with a hard-switching
measurement at 600 V establishes the intricate relation between
p-GaN drain injection in a HD-GIT and carbon doping. The appar-
ent discrepancy of the magnitude of the hole injection current at
DC and a fast switching condition is reconciled and explained by
the TCAD simulation. The hole injection from the p-drain diode is
initiated whenever a forward bias is established at on-to-off and off-
to-on transitions. The control of the hole injection current in DC is
contingent upon the intentionally doped carbon acting as a trap. A
large surge in Idp (in the order of amperes) is possible during a fast
switching transition where the injection is faster than the process of
the hole capture. Hole capture by the acceptor trap and the result-
ing positive space charge formation inside the epi ultimately lead to
diminishing of the forward bias and decay of the Idp transient to its
DC value. The above conclusion, drawn from the complex switching
simulation, is further illustrated with a simpler construction consist-
ing of two fast pulses (Vd pulse and Vg pulse), which mimics the off
and on transitions in hard switching.
ACKNOWLEDGMENTS
The authors would like to thank Dr. Yasuhiro Uemoto and his
group at Panasonic Corporation for sharing their hard-switching
measurement result and helpful discussion.
DATA AVAILABILITY
The data that support the findings of this study are available
within the article.
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