1,2,3:

Q1. The interconnection structure must support which transfer?

5/5
a. memory to processor
b. processor to memory
c. I/O to or from memory
d. all of the above
 
 
Q2. Computer _________ refers to those attributes that have a direct impact on the
logical execution of a program.
0/5
a. organization
b. specifics
c. design
d. architecture

 
Q3. Architectural attributes include __________ .
a. I/O mechanisms
b. control signals
c. interfaces
d. memory technology used

 
Q4. _________ attributes include hardware details transparent to the programmer.
0/5
a. Interface
b. Organizational
c. Memory
d. Architectural
 
Correct answer
b. Organizational

 
Q5. It is a(n) _________ design issue whether a computer will have a multiply
instruction.
0/5
a. architectural
b. memory
c. elementary
d. organizational
 
Correct answer
a. architectural

 
Q6. An I/O device is referred to as a __________.
0/5
a. CPU
b. control device
 
c. peripheral
d. register

Correct answer
c. peripheral

 
Q7. The _________ stores data
5/5
a. system bus
b. I/O
c. main memory
 
d. control unit

 
Q8. The __________ moves data between the computer and its external environment.
0/5
a. data transport
 
b. I/O
c. register
d. CPU interconnection

Correct answer
b. I/O

 
Q9. A common example of system interconnection is by means of a __________.
5/5
a. register
b. system bus
 
c. data transport
d. control device

 
Q10._________ provide storage internal to the CPU.
0/5
a. Control units
b. ALUs
c. Main memory
 
d. Registers

Correct answer
d. Registers

 
Q11. The __________ performs the computer's data processing functions.
5/5
a. Register
b. CPU interconnection
c. ALU
 
d. system bus

 
Q12. Virtually all contemporary computer designs are based on concepts developed
by __________ at the Institute for Advanced Studies, Princeton.
5/5
a. John Maulchy
b. John von Neumann
 
c. Herman Hollerith
d. John Eckert

 
Q13. The processing required for a single instruction is called a(n) __________ cycle.
0/5
a. execute
 
b. fetch
c. instruction
d. packet

Correct answer
c. instruction
 
Q14. The von Neumann architecture is based on which concept?
5/5
a. data and instructions are stored in a single read-write memory
b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above
 
 
Q15. A(n) _________ is generated by some condition that occurs as a result of an
instruction execution.
5/5
a. timer interrupt
b. I/O interrupt
c. program interrupt
 
d. hardware failure interrupt

 
Q16. The data lines provide a path for moving data among system modules and are
collectively called the _________.
5/5
a. control bus
b. address bus
c. data bus
 
d. system bus

 
Q17. The _________ was the world's first general-purpose electronic digital computer.
5/5
a. UNIVAC
b. MARK IV
c. ENIAC
 
d. Hollerith's Counting Machine

 
Q18. The PDP-8 used __________.
0/5
a. vacuum tubes
 
b. integrated circuits
c. Microelectronic
d. Transistor

Correct answer
b. integrated circuits

 
Q19. The __________ interprets the instructions in memory and causes them to be
executed.
0/5
a. main memory
b. control unit
c. I/O
d. arithmetic and logic unit
 
Correct answer
b. control unit

 
Q20. Referred to as the von Neumann architecture and is based on key concepts?
5/5
a. Data and instructions are stored in a single read-write memory
b. The contents of this memory are addressable by location, without regard to the type of data
contained there
c. Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the
next
d. All answers above
4:

Q1. The cache is responsible for…?

5/5
A. speeding up the operation and processing of the computer.
 
B. the cache is responsible for slowing down computer operations and processing.
C. storing most of the computer's data.
D. restoring the original settings of the computer.

 
Q2. Choose the wrong answer Method of Accessing Units of Data have…?
5/5
A. Memory is organized into units of data called records
B. Access time is variable
C. Access time is fixed
 
D. Access must be made in a specific linear sequence

 
Q3. Design constraints on a computer’s memory can be summed up by three
questions:
5/5
A. How much? How fast? How expensive?
 
B. How much? How far? How expensive?
C. How much? How long? How expensive?
D. How many? How fast? How expensive?

 
Q4. We was learned about diagram Memory Hierarchy. In inboard memory have:
0/5
A. Registers, cache, DVD-RAM
B. Registers, cache, main memory
C. CD-ROM, cache, main memory
D. Registers, cache, magnetic tape
 
Correct answer
B. Registers, cache, main memory

 
Q5. What is RA mean?
5/5
A. Read Address
 
B. Read Assignments
C. Remember Address
D. Remember Assignments

 
Q6. What is Volatile memory?
5/5
A. Information decays naturally or is lost when electrical power is switched off
 
B. May be either volatile or nonvolatile
C. Once recorded, information remains without deterioration until deliberately changed
D. A place to store all computer data
 
Q7. __________ refers to whether memory is internal or external to the computer.
5/5
A. Location
 
B. Access
C. Hierarchy
D. Tag

 
Q8. A portion of main memory used as a buffer to hold data temporarily that is to be
read out to disk is referred to as a _________.
5/5
A. Disk cache
 
B. Latency
C. Virtual address
D. Miss

 
Q9. The cache memory is used by the computer's central processing unit (CPU) for
what?
5/5
A. to minimize the average time in accessing data in main memory
 
B. to minimize the average time in processing information of the CPU
C. to increase the capacity of main memory
D. to increase the efficiency of the graphics processor

 
Q10. A line includes a _________ that identifies which particular block is currently
being stored.
5/5
A. Cache
B. Hit
C. Tag
 
D. Locality

 
Q11. The key advantage of the __________ design is that it eliminates contention for
the cache between the instruction fetch/decode unit and the execution unit.
5/5
A. Logical cache
B. Split cache
 
C. Unified cache
D. Physical cache

 
Q12. A logical cache stores data using __________
5/5
A. Physical addresses
B. Virtual addresses
 
C. Random addresses
D. None of the above

 
Q13. In reference to access time to a two-level memory, a _________ occurs if an
accessed word is not found in the faster memory?
5/5
A. Miss
 
B. Hit
C. Line
D. Tag

 
Q14. When using the __________ technique all write operations made to main
memory are made to the cache as well.
0/5
A. Write back
 
B. LRU
C. Write through
D. Unified cache

Correct answer
C. Write through

 
Q15. __________ is the simplest mapping technique and maps each block of main
memory into only one possible cache line.
5/5
A. Direct mapping
 
B. Associative mapping
C. Set associative mapping
D. None of the above

 
Q16. The ________ consists of the access time plus any additional time required
before a second access can commence.
5/5
A. Latency
B. Memory cycle time
 
C. Direct access
D. Transfer rate

 
Q17. The transfer between CPU and Cache is ______________
5/5
A. Block transfer
B. Word transfer
 
C. Set transfer
D. Associative transfer

 
Q18. For random-access memory, __________ is the time from the instant that an
address is presented to the memory to the instant that data have been stored or made
available for use.
5/5
A. Memory cycle time
B. Direct access
C. Transfer rate
D. Access time
 
 
Q19. individual blocks or records have a unique address based on physical location
with __________
5/5
A. Associative
B. Physical access
C. Direct access
 
D. Sequential access

 
Q20. Internal memory capacity is typically expressed in terms of _________.
5/5
A. Hertz
B. Nanos
C. Bytes
 
D. LOR

5:

Q1. The ________ enables the RAM chip to preposition bits to be placed on the
databus as rapidly as possible.
5/5
A. Flash memory
B. Hamming code
C. RamBus
D. Buffer
 
 
Q2. A DDR3 module transfers data at a clock rate of __________ MHz.
5/5
A. 600 to 1200
B. 800 to 1600
 
C. 1000 to 2000
D. 1500 to 3000

 
Q3. Theoretically, a DDR module can transfer data at a clock rate in the range of
__________ MHz.
5/5
A. 200 to 600
 
B. 400 to 1066
C. 600 to 1400
D. 800 to 1600

 
Q4. Which access time RAM is fastest?
0/5
A. SDRAM
 
B. DDR
C. RDRAM

Correct answer
C. RDRAM

 
Q5. Compare transfer rate of SDRAM, RDRAM, DDR.
5/5
A. SDRAM > RDRAM > DDR
B. SDRAM > DDR > RDRAM
C. RDRAM > DDR > SDRAM
 
D. RDRAM > SDRAM > DDR

 
Q6. ________ increases the prefetch buffer size to 8 bits.
5/5
A. CDRAM
B. RDRAM
C. DDR3
 
D. All of the above

 
Q7. __________ increases the data transfer rate by increasing the operational
frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits
per chip.
5/5
A. DDR2
 
B. RDRAM
C. CDRAM
D. DDR3

 
Q8. ________ can send data to the processor twice per clock cycle.
5/5
A. CDRAM
B. SDRAM
C. DDR-DRAM
 
D. RDRAM

 
Q9. The _________ exchanges data with the processor synchronized to an external
clock signal and running at the full speed of the processor/memory bus without
imposing wait states.
5/5
A. DDR-DRAM
B. SDRAM
 
C. CDRAM
D. None of the above

 
Q10. _________ can be caused by power supply problems or alpha particles.
5/5
A. Soft errors
 
B. AGT errors
C. Hard errors
D. SEC errors

 
Q11. __________ can be caused by harsh environmental abuse, manufacturing
defects, and wear.
5/5
A. SEC errors
B. Hard errors
 
C. Syndrome errors
D. Soft errors

 
Q12. With _________ the microchip is organized so that a section of memory cells are
erased in a single action.
5/5
A. Flash memory
 
B. SDRAM
C. DRAM
D. EEPROM

 
Q13. A __________ contains a permanent pattern of data that cannot be changed, is
nonvolatile, and cannot have new data written into it.
5/5
A. RAM
B. SRAM
C. ROM
 
D. Flash memory

 
Q14. In a _________, binary values are stored using traditional flip-flop logic-gate
configurations.
5/5
A. ROM
B. SRAM
 
C. DRAM
D. RAM

 
Q15. Which of the following memory types are nonvolatile?
5/5
A. Erasable PROM
B. Programmable ROM
C. Flash memory
D. All of the above
 
 
Q16. One distinguishing characteristic of memory that is designated as _________ is
that it is possible to both to read data from the memory and to write new data into the
memory easily and rapidly.
5/5
A. RAM
B. ROM
C. EPROM
 
D. EEPROM

 
Q17. Which properties do all semiconductor memory cells share?
5/5
A. They exhibit two stable states which can be used to represent binary 1 and 0
B. They are capable of being written into to set the state
C. They are capable of being read to sense the state
D. All of the above
 
 
Q18. The basic element of a semiconductor memory is the…………….
5/5
A. Memory cell
 
B.RAM.
C.DRAM.
D. ROM

 
Q19. A characteristic of ……. is that it is volatile
0/5
A.ROM
 
B.RAM.
C.SRAM.
D. DRAM

Correct answer
B.RAM.

 
Q20. The traditional forms of RAM used in computers are………..
5/5
A. DRAM.
B. SRAM
C. DDR SRAM
D. DRAM and SRAM
6:

Q1. The areas between pits are called _________.

5/5
A. lands
 
B. sectors
C. cylinders
D. strips

 
Q2. Two different parity calculations are carried out and stored in separate blocks on
different disks
5/5
A. RAID level 6 disadvantage
B. RAID level 6 characteristics
 
C. RAID level 2 advantage
D. RAID level 0 applications

 
Q3. FThe ________ consists of the access time plus any additional time required
before a second access can commence.
5/5
A. latency
B memory cycle time
 
C. direct access
D. transfer rate

 
Q4. Contiguous blocks data are read and written in
5/5
A. Physical records
 
B. Magnetic disk
C. RAID level 0 advantage
D. Parallel Recording

 
Q5. The sum of the seek and the rotational delay; the time it takes to get into position
to read/write.
5/5
A. Seek time
B. CAV advantage
C. Striping
D. Access time
 
 
Q6. A typical computer system is equipped with a hierarchy of memory subsystems,
some internal to the system and some external.
5/5
A. True
 
B. False

 
Q7. An error-correcting code enhances the reliability of the memory at the cost of
added complexity.
5/5
A. True
 
B. False

 
Q8. Semiconductor memory comes in packaged chips
5/5
A. True
 
B. False

 
Q9. Individual blocks of data can be directly addressed by track and sector
5/5
A. Physical records
B. Magnetic disk
C. MZR disadvantage
D. CAV advantage
 
 
Q10. Which is not a magnetic disk?
0/5
A. Floppy
 
B. HDD
C. SSD
D. A&C

Correct answer
C. SSD

 
Q11. Data are transferred to and from the disk in __________.
0/5
A. Tracks
 
B. Gaps
C. Sectors
D. Pits

Correct answer
C. Sectors

 
Q12. The SSDs now on the market use a type of semiconductor memory referred to
as flash memory.
5/5
A. True
 
B. False

 
Q13. The set of all the tracks in the same relative position on the platter is referred to
as a _________.
5/5
A. Floppy disk
 
B. Single-sided disk
C. Sector
D. Cylinder

 
Q14. What is the purpose of RAID system?
0/5
A. It increases the processor speed
B. It increases the disk storage capacity
 
C. It increases the disk storage capacity and availability
D. It increases operating system efficiency
E. It decreases operating system efficiency

Correct answer
C. It increases the disk storage capacity and availability

 
Q15. Gaps that separate blocks on the tape
5/5
A. Serial Recording
B. RAID level 5 advantage
C. Parallel Recording
D. Inter-record gaps
 
 
Q16. A _________ is a high-definition video disk that can store 25 Gbytes on a single
layer on a single side.
5/5
A. DVD
B. DVD-R
C. DVD-RW
D. Blu-ray DVD
 
 
Q17. A circular platter constructed of nonmagnetic material coated with a
magnetizable material.
0/5
A. Magnetic Disk
B. Seek time
C. Access time
D. CAV advantage
 
Correct answer
A. Magnetic Disk

 
Q18. External hard drives HDD is a _____.
5/5
A. Non-removable disk
B. Double sided disk
C. Removable disk
 
D. Movable-head disk

 
Q19. How many bytes can be used in one sector (winchester disk format)?
5/5
A. 600
B. 256
C. 16
D. 512
 
 
Q20. __________ is the standardized scheme for multiple-disk database design.
0/5
A. RAID
B. CAV
C. CLV
D. SSD
 
Correct answer
A. RAID

7:

Q1. It is a(n) _________ design issue whether a computer will have a multiply
instruction.
5/5
A. Architectural
 
B. Memory
C. Elementary
D. Organizational

 
Q2. The ________ contains I/O protocols that are mapped on to the transport layer
5/5
A. cable
B. application
 
C. common transport
D. physical

 
Q3. The 8237 DMA is known as a _________ DMA controller.
5/5
A. command
B. cycle stealing
C. interrupt
D. fly-by
 
 
Q4. A ________ is used to connect storage systems, routers, and other peripheral
devices to an InfiniBand switch.
0/5
A. target channel adapter
 
B. InfiniBand switch
C. host channel adapter
D. subnet

Correct answer
B. InfiniBand switch

 
Q5. The ________ layer is the key to the operation of Thunderbolt and what makes it
attractive as a high-speed peripheral I/O technology.
5/5
A. cable
B. application
C. common transport
 
D. physical

 
Q6. ________ is a digital display interface standard now widely adopted for computer
monitors, laptop displays, and other graphics and video interfaces.
5/5
A. DisplayPort
 
B. PCI Express
C. Thunderbolt
D. InfiniBand

 
Q7. ________ is when the DMA module must force the processor to suspend
operation temporarily.
5/5
A. Interrupt
B. Thunderbolt
C. Cycle stealing
 
D. Lock down
 
Q8. An I/O module that is quite primitive and requires detailed control is usually
referred to as an _________.
5/5
A. I/O command
B. I/O controller
 
C. I/O channel
D. I/O processo

 
Q9. The I/O function includes a _________ requirement to coordinate the flow of
traffic between internal resources and external devices.
5/5
A. cycle
B. status reporting
C. control and timing
 
D. data

 
Q10. I/O channels are commonly seen on microcomputers, whereas I/O controllers
are used on mainframes.
5/5
A. True
B. False
 
 
Q11. The _________ command causes the I/O module to take an item of data from
the data bus and subsequently transmit that data item to the peripheral.
5/5
A. control
B. test
C. read
D. write
 
 
Q12. Which one of the following can be called as a peripheral?
0/5
A. Control Unit
 
B. Arithmetic Unit
C. Speakers
D. Logic Unit
E. Main Memory

Correct answer
C. Speakers

 
Q13. A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a
network such as a local area network, wide area network, or storage area network.
5/5
A. memory controller
B. TCA
C. HCA
D. router
 
 
Q14. The ________ command is used to activate a peripheral and tell it what to do.
5/5
A. control
 
B. Test
C. read
D. write

 
Q15. An I/O module that takes on most of the detailed processing burden, presenting
a high-level interface to the processor, is usually referred to as an _________.
5/5
A. I/O channel
 
B. I/O command
C. I/O controller
D. device controller

 
Q16. The most common means of computer/user interaction is a __________.
5/5
A. keyboard/monitor
 
B. mouse/printer
C. modem/printer
D. monitor/printer

 
Q17. _________ attributes include hardware details transparent to the programmer.
5/5
A. Interface
B. Organizational
 
C. Memory
D. Architectural

 
Q18. An I/O device is referred to as a __________.
5/5
A. CPU
B. Control device
C. Peripheral
 
D. Register

 
Q19. A set of I/O modules is a key element of a computer system.
5/5
A. True
 
B. False

 
Q20. The disadvantage of the software poll is that it is time consuming.
5/5
A. True
 
B. False

8:

Q1. Facilities and services provided by the OS that assist the programmer in creating
programs are in the form of _________ programs that are not actually part of the OS
but are accessible through the OS.
5/5
a. utility
 
b. multitasking
c. JCL
d. logical address

 
Q2. ________ is when the processor spends most of its time swapping pages rather
than executing instructions.
5/5
a. Swapping
b. Thrashing
 
c. Paging
d. Multitasking

 
Q3. A _________ is a collection of memory regions.
5/5
a. APX
b. nucleus
c. domain
 
d. page table Peripheral.

 
Q4. ________ is an I/O operation.
5/5
a. Swapping
 
b. Partitioning
c. Paging
d. Segmentation

 
Q5. A/An ________ is a hardware-generated signal to the processor.
5/5
a. Partitioning
b. Interrupt
 
c. Paging
d. Segmentation
 
Q6. The OS maintains a __________ for each process that shows the frame location
for each page of the process.
5/5
a. kernel
b. page table
 
c. TLB
d. logical address

 
Q7. A _________ is an actual location in main memory.
5/5
a. logical address
b. partition address
c. base address
d. physical address
 
 
Q8. A _________ is a special type of programming language used to provide
instructions to the monitor.
5/5
a. job control language
 
b. multiprogram
c. kernel
d. utility

 
Q9. The ________ gives a program access to the hardware resources and services
available in a system through the user instruction set architecture supplemented with
high-level language library calls.
5/5
a. JCL
b. ISA
c. ABI
d. API
 
 
Q10. In Address Spaces of Pentium Memory Management, this memory is viewed as
a paged linear address space. Protection and management of memory is done via
paging. This is favored by some operating systems. So, what kind is the memory
type?
5/5
a. Unsegmented unpaged memory
b. Unsegmented paged memory
 
c. Segmented unpaged memory
d. Segmented paged memory

 
Q11. The __________ is a program that controls the execution of application
programs and acts as an interface between applications and the computer hardware.
5/5
a. job control language
b. operating system
 
c. batch system
d. nucleus

 
Q12. Uniprogramming is the central theme of modern operating systems.
5/5
a. True
b. False
 
 
Q13. Data that has been organized and logically related to allow access, retrieval, and
use of that data is called a _____.
5/5
a. store
b. database
 
c. field
d. record

 
Q14. Techniques that automatically move program and data blocks into the physical
main memory when they are required for execution are called ________.
0/5
a. Associative-Mapping techniques
b. Main Memory techniques
c. Virtual Memory techniques
d. Cache Memory techniques
e. Paging techniques
 
Correct answer
c. Virtual Memory techniques

 
Q15. How many bits of segment reference and offset contained in each virtual
address?
5/5
a. 16-bit segment reference and 16-bit offset
b. 16-bit segment reference and 32-bit offset
 
c. 32-bit segment reference and 64-bit offset
d. 8-bit segment reference and 16-bit offset

 
Q16. The __________ is a program that controls the execution of application
programs and acts as an interface between applications and the computer hardware.
5/5
a. job control language
b. operating system
 
c. batch system
d. nucleus

 
Q17. The _________ defines the repertoire of machine language instructions that a
computer can follow.
5/5
a. ABI
b. API
c. HLL
d. ISA
 
 
Q18. A _________ system works only one program at a time.
5/5
a. batch
b. uniprogramming
 
c. kernel
d. privileged instruction

 
Q19. The _________ scheduler determines which programs are admitted to the
system for processing.
5/5
a. long-term
 
b. medium-term
c. short-term
d. I/O

 
Q20. Privileged instructions are certain instructions that are designated special and
can be executed only by the monitor.
5/5
a. True
 
b. False

9:

Q1: The decimal system has a base of _________.

5/5
a. 0
b. 10
 
c. 100
d. 1000

 
Q2: Which digit represents "hundreds" in the number 8732?
5/5
a. 8
b. 7
 
c. 3
d. 2
 
Q3: Which of the following is correct?
5/5
a. 25 = (2 x 10^2) + (5 x 10^1)
b. 289 = (2 x 10^3) + (8 x 10^1) + (9 x 10^0)
c. 7523 = (7 x 10^3) + (5 x 10^2) + (2 x 10^1) + (3 x 10^0)
 
d. 0.628 = (6 x 10^-3) + (2 x 10^-2) + (8 x 10^-1)

 
Q4: In the number 3109, the 3 is referred to as the _________.
5/5
a. most significant digit
 
b. least significant digit
c. radix
d. base

 
Q5: In the number 3109, the 9 is referred to as the _________.
5/5
a. most significant digit
b. least significant digit
 
c. radix
d. base

 
Q6: Numbers in the binary system are represented to the _________.
5/5
a. base 0
b. base 1
c. base 2
 
d. base 10

 
Q7: Hexadecimal has a base of _________.
5/5
a. 2
b. 8
c. 10
d. 16
 
 
Q8: The binary string 110111100001 is equivalent to __________.
5/5
a. FF6
b. C16
c. DE1
 
d. B16

 
Q9: The _________ system uses only the numbers 0 and 1
5/5
a. positional
b. binary
 
c. hexadecimal
d. decimal

 
Q10: The binary string 100010010011101 is equivalent to __________.
5/5
a. A13B
b. 42D9
c. 44D9
d. 449D
 
 
Q11: The binary string 110111100001 is equivalent to __________.
5/5
a. 3355
b. 5335
c. 3553
 
d. 5353

 
Q12: The binary string 110101100101 is equivalent to __________.
5/5
a. 3421
b. 3241
c. 3492
d. 3429
 
 
Q13: Decimal "284" is.............. in binary.
5/5
a. 001011000100
b. 000100011100
 
c. 010001010100
d. 000100111000

 
Q14: Decimal "8.75" is.............. in binary.
5/5
a. 0110.01
b. 0110.11
c. 1000.11
 
d. 0110.10

 
Q15: Hexadecimal "786" is............... in binary.
5/5
a. 011110000110
 
b. 001100010010
c. 101110000110
d. 011010000110

 
Q16: Hexadecimal "A5BC" is............... in binary.
5/5
a. 0101010111011011
b. 1010100011110100
c. 1010010110111100
 
d. 010010110111100

 
Q17: Decimal "248" is.............. in hexadecimal .
5/5
a. E8
b. F8
 
c. D8
d. D9

 
Q18: Decimal "469" is.............. in hexadecimal .
5/5
a. 1D5
 
b. 2D4
c. 2D6
d. 1D6

 
Q19: Hexadecimal "78" is............... in decimal.
5/5
a. 130
b. 140
c. 110
d. 120
 
 
Q20: Hexadecimal "124" is............... in decimal.
5/5
a. 292
 
b. 293
c. 294
d. 295

10:

Q1: 0111 x1101 =?

0/5
a. 01110001
b. 11101011
 
c. 11011011
d. 01011011

Correct answer
d. 01011011
 
Q2: The most common scheme in implementing the integer portion of the ALU is:
5/5
a. sign-magnitude representation
b. biased representation
c. twos complement representation
 
d. ones complement representation

 
Q3: __________ representation is almost universally used as the processor
representation for integers.
5/5
a. Biased
b. Twos compliment
 
c. Sign-magnitude
d. Decimal

 
Q4: Moving the sign bit to the new leftmost position and filling in with copies of the
sign bit is called _________.
5/5
a. sign extension
 
b. range extension
c. bit extension
d. partial extension

 
Q5: 0111 x 0011 =?
5/5
a. 10010101
b. 11010101
c. 11101010
d. 00010101
 
 
Q6: In ________ representation the rule for forming the negation of an integer is to
invert the sign bit.
5/5
a. ones complement
b. twos complement
c. biased
d. sign-magnitude
 
 
Q7: ________ is when the result may be larger than can be held in the word size
being used.
5/5
a.Overflow
 
b. Arithmetic shift
c. Underflow
d. Partial product

 
Q8: Twos Complement Integers of 0111 ?
5/5
a. 1010
b. 1100
c. 1001
 
d. 1110

 
Q9: Twos Complement Integers of 11101 ?
5/5
a. 11010
b. 00011
 
c. 10011
d. 11000

 
Q10: Twos Complement Integers of 01001011 ?
5/5
a. 10110101
 
b. 11010101
c. 11101010
d. 11010010

 
Q11. __________ involves the generation of partial products, one for each digit in the
multiplier, which are then summed to produce the final product.
5/5
a. Addition
b. Subtraction
c. Multiplication
 
d. Division

 
Q12. 0011+1001 =?
0/5
a. 0100
 
b. 1100
c. 1010
d. 1001

Correct answer
b. 1100

 
Q13: 1011 - 1110 =?
0/5
a. 1100
b. 1001
 
c. 1101
d. 0011

Correct answer
c. 1101

 
Q14. Negative numbers less than -(2 - 2^-23) x 2 128 are called _________.
5/5
a. positive underflow
b. positive overflow
c. negative underflow
d. negative overflow
 
 
Q15. Positive numbers less than 2^-127 are called ________.
5/5
a. positive underflow
 
b. positive overflow
c. negative underflow
d. negative overflow

 
Q16: _________ formats extend a supported basic format by providing additional bits
in the exponent and in the significand.
5/5
a. Arithmetic
b. Basic
c. Extended precision
 
d. Interchange

 
Q17: _________ are included in IEEE 754 to handle cases of exponent underflow.
5/5
a. Subnormal numbers
 
b. Guard bits
c. Normal numbers
d. Radix points

 
Q18: 1010-1100=?
5/5
a. 1101
b. 0101
c. overflow
 
d. 1100

 
Q19: __________ is when a positive exponent exceeds the maximum possible
exponent value.
5/5
a. Significand underflow
b. Significand overflow
c. Exponent overflow
 
d. Exponent underflow

 
Q20: 1001 + 1010 =?
5/5
a. 1101
b. overflow
 
c. 1001
d. 1011

11:

Q1. The operand ________ yields true if and only if both of its operands are true.
5/5
A. XOR
B. OR
C. AND
 
D. NOT

 
Q2. The operation _________ yields true if either or both of its operands are true.
5/5
A. NOT
B. AND
C. NAND
D. OR
 
 
Q3. The ________ exists in one of two states and, in the absence of input, remains in
that state.
5/5
A. assert
B. complex PLD
C. decoder
D. flip-flop
 
 
Q4. The ________ flip-flop has two inputs and all possible combinations of input
values are valid.
5/5
A. J-K
 
B. D
D. clocked S-R
C. S-R
Other:

 
Q5. A _________ accepts and/or transfers information serially.
5/5
A. S-R latch
B. shift register
 
C. FPGA
D. parallel register

 
Q6. The _________ table provides the value of the next output when the inputs and
the present output are known, which is exactly the information needed to design the
counter or any sequential circuit.
5/5
A. excitation
 
B. Kenough
C. J-K flip-flop
D. FPGA

 
Q7. A _________ is a PLD featuring a general structure that allows very high logic
capacity and offers more narrow logic resources and a higher ration of flip-flops to
logic resources than do CPLDs.
5/5
A. SPLD
B. FPGA
 
C. PAL
D. PLA
 
Q8. IEEE 754-2008 defines the following different types of floating-point formats:
0/5
A. Arithmetic format
 
B. Basic format
C. Interchange format
D. A, B and C

Correct answer
D. A, B and C

 
Q9. CPUs make use of _________ counters, in which all of the flip-flops of the counter
change at the same time.
5/5
A. synchronous
 
B. asynchronous
C. clocked S-R
D. timed ripple

 
Q10. For more than four variables an alternative approach is a tabular technique
referred to as the _________ method.
5/5
A. DeMorgan
B. Quine-McCluskey
 
C. Karnaugh map
D. Boole-Shannon

 
Q11. Which of the following is a functionally complete set?
5/5
A. AND, NOT
B. NOR
C. AND, OR, NOT
D. all of the above
 
 
Q12. A _______ is an electronic circuit that produces an output signal that is a simple
Boolean operation on its input signals.
5/5
A. gate
 
B. decoder
C. counter
D. flip-flop

 
Q13. How many ways can floating-point number be expressed?
5/5
A. One
B. Two
C. Five
D. Many ways
 
 
Q14. In division of Unsigned Binary Integers, the result of 00111010 / 1010 is: Q =
Quotient, R = Remainder:
5/5
A. Q = 00100101 , R = 100
B. Q = 01001001, R = 1000
C. Q = 00000101, R = 1000
 
D. Q = 00000101, R = 100

 
Q15. The unary operation _________ inverts the value of its operand.
5/5
A. OR
B. NOT
 
C. NAND
D. XOR

 
Q16. The unary operation _________ inverts the value of its operand.
5/5
A. OR
B. NOT
 
C. NAND
D. XOR

 
Q17. ________ are used in digital circuits to control signal and data routing.
5/5
A. Multiplexers
 
B. Program counters
C. Flip-flops
D. Gates

 
Q18. What is this logic gate?
5/5

A. AND
B. OR
C. NOT
D. NAND
 
 
Q19. Logic function Y=?
5/5
A. Y=AB+BC
 
B. Y= BC+B
C. Y= ACB +AB
D. Y = CB + ABC

 
Q20. Out-state of the circuit?
5/5

A. 1
 
B. 01
C. 0
D. 11
12:

1. __________ is a design principle employed in designing the PDP-10 instruction set.

5/5
a. Orthogonality
b. Completeness
c. Direct addressing
d. All of the above
 
 
2. Let LDMIA r10, {r0, r1, r4} with value of r10 = 0x20C, r1 has value:
5/5
a. 0x20C
b. 0x210
 
c. 0x214
d. 0x218

 
3. The __________ byte consists of three fields: the Scale field, the Index field and the
Base field.
5/5
a. SIB
 
b. VAX
c. PDP-11
d. ModR/M

 
4. The _________ was designed to provide a powerful and flexible instruction set
within the constraints of a 16-bit minicomputer.
5/5
a. PDP-1
b. PDP-8
c. PDP-11
 
d. PDP-10

 
5. _________ is a principle by which two variables are independent of each other.
5/5
a. Opcode
b. Orthogonality
 
c. Completeness
d. Autoindexing

 
6. Which of the following interrelated factors go into determining the use of the
addressing bits?
5/5
a. number of operands
b. number of register sets
c. address range
d. all of the above
 
 
7. The only form of addressing for branch instructions is _________ addressing.
5/5
a. register
b. relative
c. base
d. immediate
 
 
8. For the _________ mode, the operand is included in the instruction.
5/5
a. immediate
 
b. base
c. register
d. displacement

 
9. Indexing performed after the indirection is __________.
5/5
a. relative addressing
b. autoindexing
c. postindexing
 
d. preindexing

 
10. For _________, the address field references a main memory address and the
referenced register contains a positive displacement from that address.
5/5
a. indexing
 
b. base-register addressing
c. relative addressing
d. all of the above

 
11. The advantage of __________ is that no memory reference other than the
instruction fetch is required to obtain the operand.
5/5
a. direct addressing
b. immediate addressing
 
c. register addressing
d. stack addressing

 
12. The advantages of _________ addressing are that only a small address field is
needed in the instruction and no time-consuming memory references are required.
5/5
a. direct
b. indirect
c. register
 
d. displacement

 
13. __________ has the advantage of large address space, however it has the
disadvantage of multiple memory references.
5/5
a. Indirect addressing
 
b. Direct addressing
c. Immediate addressing
d. Stack addressing

 
14. The principal advantage of ___________ addressing is that it is a very simple form
of addressing.
5/5
a. displacement
b. register
c. stack
d. direct
 
 
15. __________ has the advantage of flexibility, but the disadvantage of complexity.
5/5
a. Stack addressing
b. Displacement addressing
 
c. Direct addressing
d. Register addressing

 
16. What is the result in the R2 register?
5/5

A. 0x00000007
B. 0x00000005
C. 0x0000000c
 
D. 0x00000003

 
17. What is the value in the R2 register?
5/5

A. 00000012
 
B. 00000013
C. 00000014
D. 00000015

 
18. What is the value in the R8 register?
5/5

A. 00000014
B. 00000011
C. 00000006
 
D. 00000016

 
19. What is the value in the R2 register?
5/5

A. 00000000
B. 00000001
C. 00000002
 
D. 00000003

 
20. What is the value in the R3 register?
5/5
A. 00000001
B. 00000002
C. 00000003
D. 00000004
14:

Câu 1: __________ are a set of storage locations.

5/5
a. Processors
b. PSWs
c. Registers
 
d. Control units

 
Câu 2 : The ________ controls the movement of data and instructions into and out of
the processor.
5/5
a. control unit
 
b. ALU
c. shifter
d. branch

 
Câu 3: _________ is a pipeline hazard.
5/5
a. Control
b. Resource
c. Data
d. All of the above
 
 
Câu 4: The _________ stage includes ALU operations, cache access, and register
update.
5/5
a. decode
b. execute
 
c. fetch
d. write back

 
Câu 5 : ________ is used for debugging.
5/5
a. Direction flag
b. Alignment check
c. Trap flag
 
d. Identification flag

 
Câu 6 : The ARM architecture supports _______ execution modes.
5/5
a. 2
b. 8
c. 11
d. 7
 
 
Câu 7 : __________ are bits set by the processor hardware as the result of
operations.
5/5
a. MIPS
b. Condition codes
 
c. Stacks
d. PSWs

 
Câu 8 : The ________ determines the opcode and the operand specifiers.
5/5
a. decode instruction
 
b. fetch operands
c. calculate operands
d. execute instruction
 
Câu 9 : A _________ is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently fetched
instructions in sequence.
5/5
a. loop buffer
 
b. delayed branch
c. multiple stream
d. branch prediction

 
Câu 10 : The _________ is a small cache memory associated with the instruction
fetch stage of the pipeline.
5/5
a. dynamic branch
b. loop table
c. branch history table
 
d. flag

 
Câu 11 : The OS usually runs in ________.
5/5
a. supervisor mode
 
b. abort mode
c. undefined mode
d. fast interrupt mode

 
Câu 12 : The _________ contains the address of an instruction to be fetched.
5/5
a. instruction register
b. memory address register
c. memory buffer register
d. program counter
 
 
13. A memory cell in the data processing process is conceived of size:
5/5
A. 8 bits
B. 16 bits
 
C. 20 bits
D. 24 bits

 
Câu 14 : The _________ contains a word of data to be written to memory or the word
most recently read.
5/5
a. MAR
b. PC
c. MBR
 
d. IR

 
Câu 15 : ________ registers may be used only to hold data and cannot be employed
in the calculation of an operand address.
5/5
a. General purpose
b. Data
 
c. Address
d. Condition code

 
16. A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions in
sequence.
5/5
a. multiple stream
b. branch prediction
c. loop buffer
 
d. delayed branch

 
17. The RD / WR signal in the control bus of the CPU has the function:
5/5
A. Control read / write data
 
B. Control the decoding of data
C. Control the counting of commands
D. Control CPU hanging

 
18: Which register group has the common function among the following groups:
5/5
a. CS, DS, ES, SS
b. SI, DI, IP
c. AX, BX, CX, DX
 
d. SP, BP, FLAGS

 
19. Which register group has the function of indicating paragraphs of the following
groups:
5/5
a. SI, DI, IP
b. CS, DS, ES, SS
 
c. AX, BX, CX, DX
d. SP, BP, FLAGS

 
20. While the processor is in user mode the program being executed is unable to
access protected system resources or to change mode, other than by causing an
exception to occur.(T/F)
5/5
a. T
 
b. F
15:

Q1: _________ determines the control and pipeline organization.

5/5
A. Calculation
B. Execution sequencing
 
C. Operations performed
D. Operands used

 
Q2: The Patterson study examined the dynamic behavior of _________ programs,
independent of the underlying architecture. *
5/5
A. HLL
 
B. RISC
C. CISC
D. all of the above

 
Q3: _________ is the fastest available storage device.
5/5
A. Main memory
B. Cache
C. Register storage
 
D. HLL

 
Q4: The first commercial RISC product was _________.
5/5
A. SPARC
B. CISC
C. VAX
D. the Pyramid
 
 
Q5: _________ instructions are used to position quantities in registers temporarily for
computational operations.
5/5
A. Load-and-store
 
B. Window
C. Complex
D. Branch

 
Q6: Which stage is required for load and store operations?
5/5
A. I
B. E
C. D
D. all of the above
 
 
Q7: A ________ instruction can be used to account for data and branch delays. *
5/5
A. SUB
B. NOOP
 
C. JUMP
D. all of the above

 
Q8: The instruction location immediately following the delayed branch is referred to as
the ________.
5/5
A. delay load
B. delay file
C. delay slot
 
D. delay register

 
Q9: The _________ stage includes ALU operations, cache access, and register
update.
5/5
A. decode
B. execute
 
C. fetch
D. write back
Option 5

 
Q10: The MIPS R4000 uses ________ bits for all internal and external data paths and
for addresses, registers, and the ALU.
5/5
A. 16
B. 32
C. 64
 
D. 128
 
Q11: All MIPS R series processor instructions are encoded in a single ________ word
format.
5/5
A. 4-bit
B. 8-bit
C. 16-bit
D. 32-bit
 
 
Q12: A _________ architecture is one that makes use of more, and more fine-grained
pipeline stages.
5/5
A. parallel
B. superpipelined
 
C. superscalar
D. hybrid

 
Q13: The R4000 can have as many as _______ instructions in the pipeline at the
same time.
5/5
A. 8
 
B. 10
C. 5
D. 3

 
Q14: The R4000 pipeline stage where the instruction result is written back to the
register file is the __________ stage.
5/5
A. write back
 
B. tag check
C. data cache
D. instruction execute

 
Q15: SPARC refers to an architecture defined by ________.
5/5
A. Microsoft
B. Apple
C. Sun Microsystems
 
D. IBM

 
Q16: The _________ contains a word of data to be written to memory or the word
most recently read
5/5
A. MAR
B. PC
C. MBR
 
D. IR

 
Q17: The ________ determines the opcode and the operand specifiers.
5/5
A. decode instruction
 
B. fetch operands
C. calculate operands
D. execute instruction

 
Q18: A ________ hazard occurs when there is a conflict in the access of an operand
location.
5/5
A. resource
B. data
 
C. structural
D. control

 
Q19: A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions in
sequence.
5/5
A. loop buffer
 
B. delayed branch
C. multiple stream
D. branch prediction

 
Q20: The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
5/5
A. dynamic branch
B. loop table
C. branch history table
 
D. flag

Test_SFE_01_CEA201_SE1623_Spring
Total points84/100
The respondent's email address (anhhvhe153549@fpt.edu.vn) was recorded on submission of
this form.

 
Q1. The ________ enables the RAM chip to preposition bits to be placed on the
databus as rapidly as possible.
2/2
A. Flash memory
B. Hamming code
C. RamBus
D. Buffer
 
 
Q2. Two different parity calculations are carried out and stored in separate blocks on
different disks
2/2
A. RAID level 6 disadvantage
B. RAID level 6 characteristics
 
C. RAID level 2 advantage
D. RAID level 0 applications

 
Q3. The ________ contains I/O protocols that are mapped on to the transport layer
2/2
A. cable
B. application
 
C. common transport
D. physical

 
Q4. Facilities and services provided by the OS that assistrm of _________ programs
that are not actually part of the OS but are accessible through the OS.
2/2
a. utility
 
b. multitasking
c. JCL
d. logical address

 
Q5. A _________ is a special type of programming language used to provide
instructions to the monitor.
2/2
a. job control language
 
b. multiprogram
c. kernel
d. utility

 
Q6. A(n) _________ expresses operations in a concise algebraic form using variables.
2/2
a. opcode
b. high-level language
 
c. machine language
d. register

 
Q7 : ________ is used for debugging.
2/2
a. Direction flag
b. Alignment check
c. Trap flag
 
d. Identification flag

 
Q8: The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
2/2
a. dynamic branch
b. loop table
c. branch history table
 
d. flag

 
Q9: The _________ contains the address of an instruction to be fetched.
2/2
a. instruction register
b. memory address register
c. memory buffer register
d. program counter
 
 
Q10. A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions in
sequence.
2/2
a. multiple stream
b. branch prediction
c. loop buffer
 
d. delayed branch

 
Q11: The _________ is a small cache memory associated with the instruction fetch
stage of the pipeline.
2/2
a. dynamic branch
b. loop table
c. branch history table
 
d. flag
 
Q12 : ________ registers may be used only to hold data and cannot be employed in
the calculation of an operand address.
2/2
a. General purpose
b. Data
 
c. Address
d. Condition code

 
Q13. The entire set of parameters, including return address, which is stored for a
procedure invocation is referred to as a _________.
2/2
a. branch
b. stack frame
 
c. pop
d. push

 
Q14. The most fundamental type of machine instruction is the _________ instruction.
2/2
a. conversion
b. data transfer
 
c. arithmetic
d. logical

 
Q15. In Twos Complement Representation 4 bit, 1100 + 1111 = X, X = ?
2/2
A. 1011
 
B. 1111
C. 1000
D. 1010

 
Q16. In division of Twos Complement, the result of 1010 / 1110 is: Q = Quotient, R =
Remainder:
2/2
A. Q = 0011 , R = 0001
B. Q = 0011 , R = 0000
 
C. Q = 0100 , R = 0001
D. Q = 0111 , R = 0001

 
Q17. -1001 0010 1001.001= -1.001 0010 1001 001 x 2^x , x=?
2/2
A. 11
 
B. 12
C. 13
D. 14

 
Q18. A _______ is an electronic circuit that produces an output signal that is a simple
Boolean operation on its input signals.
2/2
A. gate
 
B. decoder
C. counter
D. flip-flop

 
Q19. What’s the function of ALU?
2/2
A. Control the operation of the CPU and the computer
B. Perform the computer’s data processing function Right
 
C. Provide storage internal to the CPU
D. Connect internal and exteral of CPU

 
Q20. C16= 82; C2=?
2/2
A. 10000000
B. 01001111
C. 10000010
 
D. 11010100

 
Q21. What is this logic gate?
2/2

A. OR
B. AND
C. XOR
 
NAND

 
Q22. C16= AB6E; C10=?
2/2
A. 42886
B. 43886
 
C. 44886
D. 41886

 
Q23. In Address Spaces of Pentium Memory Management, this memory is viewed as
a paged linear address space. Protection and management of memory is done via
paging. This is favored by some operating systems. So, what kind is the memory
type?
2/2
a. Unsegmented unpaged memory
b. Unsegmented paged memory
 
c. Segmented unpaged memory
d. Segmented paged memory

 
Q24. ________ is when the DMA module must force the processor to suspend
operation temporarily.
2/2
A. Interrupt
B. Thunderbolt
C. Cycle stealing
 
D. Lock down

 
Q25. The Thunderbolt protocol _________ layer is responsible for link maintenance
including hot-plug detection and data encoding to provide highly efficient data transfer.
2/2
A. cable
B. application
C. common transport
D. physical
 
 
Q26. An I/O module that takes on most of the detailed processing burden, presenting
a high-level interface to the processor, is usually referred to as an _________.
2/2
A. I/O channel
 
B. I/O command
C. I/O controller
D. device controller

 
Q27. Set of physical disk drives viewed by the OS as a single logical drive
2/2
A. With RAID level 2, if a disk fails
B. Rotational delay (latency)
C. Redundant array of independent disks (RAID)
 
D. Non-redundant RAID (RAID level 0)

 
Q28. The set of all the tracks in the same relative position on the platter is referred to
as a _________.
2/2
A. Floppy disk
B. Single-sided disk
C. Sector
D. Cylinder
 
 
Q29. A circular platter constructed of nonmagnetic material coated with a
magnetizable material.
2/2
A. Magnetic Disk
 
B. Seek time
C. Access time
D. CAV advantage

 
Q30. Theoretically, a DDR module can transfer data at a clock rate in the range of
__________ MHz.
2/2
A. 200 to 600
 
B. 400 to 1066
C. 600 to 1400
D. 800 to 1600

 
Q31. One distinguishing characteristic of memory that is designated as _________ is
that it is possible to both to read data from the memory and to write new data into the
memory easily and rapidly.
0/2
A. RAM
B. ROM
C. EPROM
D. EEPROM
 
Correct answer
C. EPROM

 
Q32: ________ is used for debugging.
2/2
a. Direction flag
b. Alignment check
c. Trap flag
 
d. Identification flag

 
Q33. The ________ flip-flop has two inputs and all possible combinations of input
values are valid.
2/2
A. J-K
 
B. D
D. clocked S-R
C. S-R

 
Q34. In Twos Complement Representation 4 bit, 1100 + 1111 = X, X = ?
2/2
A. 1011
 
B. 1111
C. 1000
D. 1010

 
Q35. 0.625(10) = X(2) , X = ?
2/2
A. 0.001
B. 0.100
C. 0.101
 
D. 0.110

 
Q36. In division of Twos Complement, the result of 1010 / 1110 is: Q = Quotient, R =
Remainder:
2/2
A. Q = 0011 , R = 0001
B. Q = 0011 , R = 0000
 
C. Q = 0100 , R = 0001
D. Q = 0111 , R = 0001

 
Q37. A _________ is a PLD featuring a general structure that allows very high logic
capacity and offers more narrow logic resources and a higher ration of flip-flops to
logic resources than do CPLDs.
2/2
A. SPLD
B. FPGA
 
C. PAL
D. PLA

 
Q38. IEEE 754-2008 defines the following different types of floating-point formats:
2/2
A. Arithmetic format
B. Basic format
C. Interchange format
D. A, B and C
 
 
Q39. C2= 1101.11; C10=?
2/2
A. 13.75
 
B. 13.5
C. 13.25
D. 14.25

 
Q40 : A _________ is a small, very-high-speed memory maintained by the instruction
fetch stage of the pipeline and containing the n most recently fetched instructions in
sequence.
0/2
a. loop buffer
b. delayed branch
 
c. multiple stream
d. branch prediction

Correct answer
a. loop buffer

 
Q41: The _________ contains the address of an instruction to be fetched.
0/2
a. instruction register
b. memory address register
c. memory buffer register
 
d. program counter

Correct answer
d. program counter

 
Q42. After learning the chapter 2, what followings should be understood:
0/2
A. The basic elements of an instruction cycle and the role of interrupts
B. Decoding ability
C. Present an overview of Computer game
 
D.history of computer

Correct answer
A. The basic elements of an instruction cycle and the role of interrupts

 
Q43. Which classes of Interrupts allow the operating system to perform certain
functions on a regular basis?
2/2
A. Program interrupt
B. Hardware failure interrupt
C.Timer interrupt
 
D. I/O interrupt

 
Q44. A(n) _________ is generated by a failure such as power failure or memory parity
error.
2/2
A. I/O interrupt
B. Hardware failure interrupt
 
C. Timer interrupt
D. Program interrupt

 
Q45. Let LDMIA r10, {r0, r1, r4} with value of r10 = 0x20C, r1 has value:
2/2
a. 0x20C
b. 0x210
 
c. 0x214
d. 0x218

 
Q46. Indexing performed after the indirection is __________.
0/2
a. relative addressing
 
b. autoindexing
c. postindexing
d. preindexing

Correct answer
c. postindexing

 
Q47. __________ has the advantage of flexibility, but the disadvantage of complexity.
0/2
a. Stack addressing
 
b. Displacement addressing
c. Direct addressing
d. Register addressing

Correct answer
b. Displacement addressing

 
Q48. What is the value in the R2 register?
2/2

A. 00000000
B. 00000001
C. 00000002
 
D. 00000003

 
Q49. When does program execution halt?
0/2
A. When the machine is turned off
 
B. Some sort of unrecoverable error occurs
C. A program instruction that halts the computer is encountered
D. All of the above

Correct answer
D. All of the above

 
Q50. During the _________ the opcode of the next instruction is loaded into the IR
and the address portion is loaded into the MAR.
0/2
A. Execute cycle
 
B. Fetch cycle
C. Instruction cycle
D. Clock cycle

Correct answer
B. Fetch cycle

Test_SFE_02_CEA201_SE1623_Spring
Total points74/100
The respondent's email address (anhhvhe153549@fpt.edu.vn) was recorded on submission of
this form.

 
_________ attributes include hardware details transparent to the programmer
2/2
organization
 
specifics
design
architecture

 
When data are moved over longer distances, to or from a remote device, the process
is known as __________.
2/2
data communications
 
registering
structuring
data transport

 
An I/O device is referred to as a __________.
2/2
CPU
control device
peripheral
 
register

 
A __________ system is a set of interrelated subsystems.
2/2
secondary
hierarchical
 
complex
functional

 
The ENIAC is an example of a _________ generation computer.
2/2
first
 
second
third
fourth

 
The __________ interprets the instructions in memory and causes them to be
executed.
2/2
main memory
control unit
 
I/O
arithmetic and logic unit

 
Choose the wrong answer Method of Accessing Units of Data have…?
2/2
A. Memory is organized into units of data called records
B. Access time is variable
C. Access time is fixed
 
D. Access must be made in a specific linear sequence

 
We was learned about diagram Memory Hierarchy. In inboard memory have:
2/2
A. Registers, cache, DVD-RAM
B. Registers, cache, main memory
 
C. CD-ROM, cache, main memory
D. Registers, cache, magnetic tape

 
What is Volatile memory?
2/2
A. Information decays naturally or is lost when electrical power is switched off
 
B. May be either volatile or nonvolatile
C. Once recorded, information remains without deterioration until deliberately changed
D. A place to store all computer data

 
The IAS operates by repetitively performing an instruction cycle.
2/2
True
 
False

 
The data lines provide a path for moving data among system modules and are
collectively called the _________.
2/2
control bus
address bus
data bus
 
system bus

 
The ________ enables the RAM chip to preposition bits to be placed on the databus
as rapidly as possible.
0/2
A. Flash memory
B. Hamming code
 
C. RamBus
D. Buffer

Correct answer
D. Buffer

 
Which access time RAM is fastest?
0/2
A. SDRAM
 
B. DDR
C. RDRAM

Correct answer
C. RDRAM

 
_________ can be caused by power supply problems or alpha particles.
0/2
A. Soft errors
B. AGT errors
 
C. Hard errors
D. SEC errors

Correct answer
A. Soft errors

 
A __________ contains a permanent pattern of data that cannot be changed, is
nonvolatile, and cannot have new data written into it.
2/2
A. RAM
B. SRAM
C. ROM
 
D. Flash memory

 
With asynchronous timing the occurrence of events on the bus is determined by a
clock.
2/2
True
False
 
 
The correspondence between the main memory blocks and those in the cache is
specified by
0/2
Mapping function
Replacement algorithm
 
Hit rate
Miss penalty
Segment function

Correct answer
Mapping function

 
The ________ consists of the access time plus any additional time required before a
second access can commence.
2/2
latency
memory cycle time
 
direct access
transfer rate

 
An error-correcting code enhances the reliability of the memory at the cost of added
complexity.
2/2
True
 
False

 
________ is when the DMA module must force the processor to suspend operation
temporarily.
0/2
Interrupt
Thunderbolt
 
Cycle stealing
Lock down

Correct answer
Cycle stealing

 
Semiconductor memory comes in packaged chips.
2/2
True
 
False

 
A _________ is a high-definition video disk that can store 25 Gbytes on a single layer
on a single side.
0/2
DVD
 
DVD-R
DVD-RW
Blu-ray DVD

Correct answer
Blu-ray DVD

 
A number of chips can be grouped together to form a memory bank.
2/2
True
 
False

 
Adjacent tracks are separated by _________.
2/2
sectors
gaps
 
pits
heads

 
The SSDs now on the market use a type of semiconductor memory referred to as
flash memory.
2/2
True
 
False

 
The 8237 DMA is known as a _________ DMA controller.
2/2
A. command
B. cycle stealing
C. interrupt
D. fly-by
 
 
The ________ layer is the key to the operation of Thunderbolt and what makes it
attractive as a high-speed peripheral I/O technology.
0/2
A. cable
B. application
 
C. common transport
D. physical

Correct answer
C. common transport

 
_______ is when the DMA module must force the processor to suspend operation
temporarily.
0/2
A. Interrupt
 
B. Thunderbolt
C. Cycle stealing
D. Lock down

Correct answer
C. Cycle stealing

 
An I/O device is referred to as a __________.
0/2
A. CPU
B. Control device
 
C. Peripheral
D. Register

Correct answer
C. Peripheral

 
The disadvantage of the software poll is that it is time consuming.
2/2
True
 
False

 
Facilities and services provided by the OS that assist the programmer in creating
programs are in the form of _________ programs that are not actually part of the OS
but are accessible through the OS.
2/2
a. utility
 
b. multitasking
c. JCL
d. logical address

 
________ is an I/O operation.
2/2
a. Swapping
 
b. Partitioning
c. Paging
d. Segmentation

 
The OS maintains a __________ for each process that shows the frame location for
each page of the process.
2/2
a. kernel
b. page table
 
c. TLB
d. logical address

 
A _________ is a special type of programming language used to provide instructions
to the monitor.
0/2
a. job control language
b. multiprogram
c. kernel
d. utility
 
Correct answer
a. job control language

 
The __________ is a program that controls the execution of application programs and
acts as an interface between applications and the computer hardware.
2/2
a. job control language
b. operating system
 
c. batch system
d. nucleus
 
Techniques that automatically move program and data blocks into the physical main
memory when they are required for execution are called ________.
2/2
a. Associative-Mapping techniques
b. Main Memory techniques
c. Virtual Memory techniques
 
d. Cache Memory techniques
e. Paging techniques

 
The _________ scheduler determines which programs are admitted to the system for
processing.
2/2
a. long-term
 
b. medium-term
c. short-term
d. I/O

 
With isolated I/O there is a single address space for memory locations and I/O
devices.
0/2
True
 
False

Correct answer
False

 
A _________ is a special type of programming language used to provide instructions
to the monitor.
2/2
job control language
 
multiprogram
kernel
utility
 
Scheduling and memory management are the two OS functions that are most relevant
to the study of computer organization and architecture.
2/2
True
 
False

 
The OS must determine how much processor time is to be devoted to the execution of
a particular user program
2/2
True
 
False

 
With demand paging it is necessary to load an entire process into main memory.
0/2
True
 
False

Correct answer
False

 
Privileged instructions are certain instructions that are designated special and can be
executed only by the monitor.
2/2
True
 
False

 
The unary operation _________ inverts the value of its operand.
2/2
OR
NOT
 
NAND
XOR

 
________ are used in digital circuits to control signal and data routing.
2/2
Multiplexers
 
Program counters
Flip-flops
Gates

 
The memory transfer rate has not kept up with increases in processor speed.
2/2
True
 
False

 
The disadvantage of immediate addressing is that the size of the number is restricted
to the size of the address field.
2/2
True
 
False

 
The method of calculating the EA is the same for both base-register addressing and
indexing.
2/2
True
 
False

 
A control hazard occurs when two or more instructions that are already in the pipeline
need the same resource.
0/2
True
 
False
Correct answer
False

 
One of the major problems in designing an instruction pipeline is assuring a steady
flow of instructions to the initial stages of the pipeline.
2/2
True
 
False 

Test_SFE_03_CEA201_Spring 2021
Total points98/100
 
The respondent's email address (anhhvhe153549@fpt.edu.vn) was recorded on submission of
this form.

 
The operation _________ yields true if either or both of its operands are true.
2/2
A. NOT
B. AND
C. NAND
D. OR
 
 
The ________ flip-flop has two inputs and all possible combinations of input values
are valid.
2/2
A. J-K
 
B. D
D. clocked S-R
C. S-R
Other:
 
A _________ is a PLD featuring a general structure that allows very high logic
capacity and offers more narrow logic resources and a higher ration of flip-flops to
logic resources than do CPLDs.
2/2
A. SPLD
B. FPGA
 
C. PAL
D. PLA

 
CPUs make use of _________ counters, in which all of the flip-flops of the counter
change at the same time.
2/2
A. synchronous
 
B. asynchronous
C. clocked S-R
D. timed ripple

 
How many ways can floating-point number be expressed?
2/2
A. One
B. Two
C. Five
D. Many ways
 
 
Logic function Y=?
0/2
A. Y=AB+BC
B. Y= BC+B
C. Y= ACB +AB
D. Y = CB + ABC

 
_________ attributes include hardware details transparent to the programmer.
2/2
Interface
Organizational
 
Memory
Architectural

 
Computer _________ refers to those attributes that have a direct impact on the logical
execution of a program.
2/2
organization
specifics
design
architecture
 
 
Interfaces between the computer and peripherals is an example of an organizational
attribute.
2/2
True
 
False

 
A sequence of codes or instructions is called __________.
2/2
software
 
memory
an interconnect
a register

 
An I/O device is referred to as a __________.
2/2
a. CPU
b. control device
c. peripheral
 
d. register

 
_________ provide storage internal to the CPU.
2/2
a. Control units
b. ALUs
c. Main memory
d. Registers
 
 
The processing required for a single instruction is called a(n) __________ cycle.
2/2
a. execute
b. fetch
c. instruction
 
d. packet
 
The von Neumann architecture is based on which concept?
2/2
a. data and instructions are stored in a single read-write memory
b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above
 
 
The PDP-8 used __________.
2/2
a. vacuum tubes
b. integrated circuits
 
c. Microelectronic
d. Transistor

 
Because all devices on a synchronous bus are tied to a fixed clock rate, the system
cannot take advantage of advances in device performance.
2/2
True
 
False

__________ refers to whether memory is internal or external to the computer.

Location
Access
Hierarchy
Tag

 
In a volatile memory, information decays naturally or is lost when electrical power is
switched off.
2/2
True
 
False

 
individual blocks or records have a unique address based on physical location with
__________.
2/2
associative
physical access
direct access
 
sequential access

 
__________ is the simplest mapping technique and maps each block of main memory
into only one possible cache line.
2/2
Direct mapping
 
Associative mapping
Set associative mapping
None of the above

 
With _________ the microchip is organized so that a section of memory cells are
erased in a single action.
2/2
flash memory
 
SDRAM
DRAM
EEPROM

 
The areas between pits are called _________.
2/2
A. lands
 
B. sectors
C. cylinders
D. strips

 
A typical computer system is equipped with a hierarchy of memory subsystems, some
internal to the system and some external.
2/2
A. True
 
B. False

 
Semiconductor memory comes in packaged chips
2/2
A. True
 
B. False

 
The set of all the tracks in the same relative position on the platter is referred to as a
_________.
2/2
A. Floppy disk
 
B. Single-sided disk
C. Sector
D. Cylinder

 
Gaps that separate blocks on the tape
2/2
A. Serial Recording
B. RAID level 5 advantage
C. Parallel Recording
D. Inter-record gaps
 
 
How many bytes can be used in one sector (winchester disk format)?
2/2
A. 600
B. 256
C. 16
D. 512
 
 
A static RAM will hold its data as long as power is supplied to it.
2/2
True
 
False

 
The disadvantage of _________ is that the amount of data that can be stored on the
long outer tracks is only the same as what can be stored on the short inner tracks.
2/2
SSD
CAV
 
ROM
CLV

 
All DRAMs require a refresh operation.
True
 
False

 
The sum of the seek time and the rotational delay equals the _________, which is the
time it takes to get into position to read or write.
2/2
access time
 
gap time
transfer time
constant angular velocity

 
There are typically hundreds of sectors per track and they may be either fixed or
variable lengths.
2/2
True
 
False

 
The disadvantage of the software poll is that it is time consuming.
2/2
True
 
False

 
What interface is used to connect the processor to I/O devices that require
transmission of data one bit at a time?
2/2
Parallel
Serial
 
Output
Input
Bus

 
The I/O function includes a _________ requirement to coordinate the flow of traffic
between internal resources and external devices.
2/2
cycle
status reporting
control and timing
 
data

 
An interrupt is a hardware-generated signal to the processor.
2/2
True
 
False

 
The ________ gives a program access to the hardware resources and services
available in a system through the user instruction set architecture supplemented with
high-level language library calls.
2/2
JCL
ISA
ABI
API
 
 
__________ is a design principle employed in designing the PDP-10 instruction set.
2/2
a. Orthogonality
b. Completeness
c. Direct addressing
d. All of the above
 
 
_________ is a principle by which two variables are independent of each other.
2/2
a. Opcode
b. Orthogonality
 
c. Completeness
d. Autoindexing

 
For the _________ mode, the operand is included in the instruction.
2/2
a. immediate
 
b. base
c. register
d. displacement

 
The advantages of _________ addressing are that only a small address field is
needed in the instruction and no time-consuming memory references are required.
2/2
a. direct
b. indirect
c. register
 
d. displacement

 
The unary operation _________ inverts the value of its operand.
2/2
OR
NOT
 
NAND
XOR
 
The operand ________ yields true if and only if both of its operands are true.
2/2
XOR
OR
AND
 
NOT

 
Three of the most common uses of stack addressing are relative addressing, base-
register addressing, and indexing.
2/2
True
False
 
 
Register indirect addressing uses the same number of memory references as indirect
addressing.
2/2
True
False
 
 
In a system without virtual memory, the effective address is a virtual address or a
register.
2/2
True
False
 
 
Typically an instruction set will include both preindexing and postindexing.
2/2
True
False
 
 
Register addressing is similar to direct addressing with the only difference being that
the address field refers to a register rather than a main memory address.
2/2
True
 
False

 
It is possible to improve pipeline performance by automatically rearranging instructions
within a program so that branch instructions occur later than actually desired.
2/2
True
 
False

 
The predict-never-taken approach is the most popular of all the branch prediction
methods.
2/2
True
 
False

 
Interrupt processing allows an application program to be suspended in order that a
variety of interrupt conditions can be serviced and later resumed.
2/2
True
 
False

 
Microprogramming eases the task of designing and implementing the control unit and
provides support for the family concept.
2/2
True
 
False