Hardware/Software Co-Design:

Principles and Practice

Hardware/Software Co-Design:
Principles and Practice

edited by

J0 rgen Staunstrup
Technical University,
Lyngby, Denmark

and

Wayne Wolf
Princeton University,
Princeton, NJ, U.S.A.

Springer-Science+Business Media, B.Y:

A C.I.P.Catalogue record for this book is avallable from the L1brary of Congress.

Printed on acid-tree paper

All RightsReserved

ISBN 978-1-4419-5018-5 ISBN 978-1-4757-2649-7 (eBook)

DOI 10.1007/978-1-4757-2649-7

© 1997 Springer Science+Business Media Dordrecht. Third Printing 2002.

Originally published by Kluwer Academic Publishers in 1997.
Softcover reprint ofthe hardcover 1st edition 1997

No part of the materialprotected by this copyright notice may be reproduced or

utilizedin any form or by any means, electronic or mechanical,
includlng photocopying, recording or by any information storageand
retrieval system, withoutwritten permission from the copyright owner.
This printing ls a digital duplication of the original edition.
Contents

Contributing Authors xi

Preface xvii

1
Essential Issues in Codesign 1
Daniel D. Gajski, Jianwen Zhu, and Rainer Domer
1.1 Models 1
1.1.1 Models and Architectures 2
1.1.2 Finite-State Machines 3
1.1.3 Dataflow Graph 5
1.1.4 Finite-State Machine with Datapath 6
1.1.5 Hierarchical Concurrent Finite-State Machines 8
1.1.6 Programming Languages 10
1.1.7 Program-State Machines 11
1.2 Architectures 13
1.2.1 Controller Architecture 13
1.2.2 Datapath Architecture 13
1.2.3 FSMD Architecture 17
1.2.4 C1SC Architecture 18
1.2.5 RISC Architecture 20
1.2.6 VLlW Architecture 21
1.2.7 Parallel Architecture 22
1.3 Languages 24
1.3.1 Concurrency 24
1.3.2 State Transitions 26
1.3.3 Hierarchy 27
1.3.4 Programming Constructs 29
1.3.5 Behavioral Completion 30
1.3.6 Exception Handling 30
1.3.7 Timing 31
v
vi HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

1.3.8 Communication 32
1.3.9 Process Synchronization 34
1.4 A Generic Co-Design Methodology 36
1.4.1 System Specification 36
1.4.2 Allocation and Partitioning 38
1.4.3 Scheduling 40
1.4.4 Communication Synthesis 41
1.4.5 Analysis and Validation Flow 43
1.4.6 Backend 44
1.5 Conclusions 44
2
Hardware/Software Co-Synthesis Algorithms 47
Wayne Wolf
2.1 Introduction 47
2.2 Preliminaries 51
2.3 Architectural Models 53
2.4 Hardware/Software Partitioning 56
2.4.1 Architectural Models 57
2.4.2 Performance Estimation 57
2.4.3 Vulcan 58
2.4.4 Cosyma 61
2.4.5 Other Partitioning Systems 62
2.5 Distributed System Co-Synthesis 62
2.5.1 An Integer Linear Programming Model 63
2.5.2 Performance Analysis 65
2.5.3 Heuristic Algorithms 66
2.5.4 System Partitioning 70
2.5.5 Reactive System Co-Synthesis 71
2.5.6 Communication Modeling and Co-Synthesis 72
2.6 Conclusions 73
3
Prototyping and Emulation 75
Wolfgang Rosenstiel
3.1 Introduction 75
3.2 Prototyping and Emulation Techniques 78
3.3 Prototyping and Emulation Environments 83
3.3.1 The Weaver Prototyping Environment 85
3.3.2 Quickturn Emulation Systems 90
3.3.3 Mentor SimExpress Emulation System 93
3.3.4 Zycad Paradigm RP and XP 94
3.3.5 Aptix Prototyping System 97
3.3.6 Arkos (Synopsys) and CoBalt (Quickturn) Emulation Systems 100
3.4 Future Developments in Emulation and Prototyping 101
3.4.1 Target Architecture 103
3.5 Example 106
 Contents vii

3.6 Results 109

3.7 Conclusions 111
4
Target Architectures 113
Rolf Ernst
4.1 Introduction 113
4.2 Architecture Specialization Techniques 116
4.2.1 Component specialization techniques 116
4.2 .2 System Specialization 117
4.2.3 System Specialization Techniques 118
4.2 .4 Memory Architectures 120
4.3 System Communication Infrastructure 122
4.4 Target Architectures and Application System Classes 125
4.5 Architectures for Control-Dominated Systems 126
4.5.1 8051- An 8-bit Microcontroller Architecture 127
4.5 .2 Architectures for High-Performance Control 131
4.6 Architectures for Data-Dominated Systems 135
4.6.1 ADSP21060 SHARC 136
4.6 .2 TMS320C80 MVP 141
4.7 Mixed Systems and Less Specialized Systems 145
4.8 Selected co-design problems 147
4.9 Conclusions 147
5
Compilation Techniques and Tools for Embedded Processor Architectures 149
Clifford Liem and Pierre Paulin
5.1 Introduction 149
5.2 Continued Integration Leads to Embedded Processors 150
5.3 Modern Embedded Architectures 151
5.3.1 Architectures in Multimedia . Wireless, and Telecommunications 151
5.3.2 Examples of Emerging Architectures 153
5.4 Embedded Software Development Needs 160
5.4.1 Commercial Support of Embedded Processors 160
5.4.2 Design Tool Requirements 161
5.5 Compilation Technologies 162
5.5.1 Are Traditional Compilation Techniques Enough? 163
5.5.2 Retargetability. Specification Languages , and Models 166
5.5 .3 Compiler Techniques for Specialized Architectures 170
5.5.4 Optimizations for embedded processors 176
5.6 Practical Considerations in a Compiler Development Environment 179
5.6.1 Compiler Validation 184
5.6.2 Source-Level Debugging 187
5.6.3 Architecture and Algorithm Exploration 189
5.7 Conclusions 191
 viii HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

Design Specification and Verification 193

J . Staunstrup
6.1 Introduction 193
6.1.1 Design 194
6.1.2 Co-design 195
6.1.3 The Co-design Computational Model 196
6.2 Concurrency 198
6.2.1 Components 199
6.2.2 Nondeterminism 200
6.2.3 Concurrency in Standard Languages 203
6.2.4 Synchronous and Asynchronous Computations 205
6.2.5 Classification of High-Level Languages 207
6.3 Coordinating Concurrent Computations 208
6.3.1 Classification 210
6.3.2 Shared State Versus Messages 210
6.3.3 Open Versus Closed Operations 213
6.3.4 Blocking Versus Nonblocking Operations 214
6.3.5 Remote Procedure Calls 216
6.3.6 Classification of Coordination Paradigms 217
6.4 Interfacing Components 217
6.4.1 Physical Realization of State Variables 220
6.5 Verification 222
6.5.1 Design Verification 225
6.5.2 Implementation Verification 225
6.5.3 Verification Tools 228
6.5.4 Interface Verification 229
6.6 Conclusions 232
7
Languages for System-Level Specification and Design 235
A.A . Jerraya, M. Romdhani, G.A . Valderrama, Ph. Le Marrec, F. Hessel, G.F. Marchioro, and
J.M. Daveau
7.1 Introduction 235
7.2 System-Level Specification 236
7.2.1 Homogeneous Specification 236
7.2.2 Heterogeneous Specification 237
7.3 Design Representation for System Level Synthesis 238
7.3.1 Synthesis Intermediate Forms 238
7.3.2 Basic Concepts and Computational Models 240
7.3.3 language Oriented Intermediate Forms 241
7.3.4 Architecture Oriented Intermediate Forms 242
7.3.5 Distributed Intermediate Forms 244
7.4 System level Specification languages 245
7.4.1 The Plethora of System Specification languages 245
7.4.2 Comparing Specification Languages 248
7.5 Heterogeneous Specification and Multi-language Co-simulation 251
 Contents ix

7.5.1 Basic Concepts for Multi-Language Design 251

7.5.2 Co-simulation Models 253
7.5.3 Automatic Generation of Co-Simulation Interfaces 255
7.5.4 Application: C-VHDL Specificat ion and Co-Simulation 257
7.5.5 Towards System Level Multi-language Specification and Co-Simulation
260
7.6 Conclusions 261
8
The Cosyma System 263
Achim Osterling, Thomas Benner, Rolf Ernst, Dirk Herrmann, Thomas Scholz, and Wei Ye
8.1 Overview 263
8.2 Cosyma architecture and input languages 264
8.2.1 Cosyma design flow and user interaction 265
8.3 Hardware/Software Partitioning 267
8.4 Hardware and software synthesis 268
8.5 Communication Estimation and Code Optimization 269
8.6 The Scalable-Performance Scheduler 271
8.6.1 An Example 272
8.7 System Opt imization Example 273
8.7.1 Architecture Template 273
8.7.2 Example: Smooth Image Filter 273
8.7.3 Real World Example 277
8.8 New approaches in Cosyma 278
8.8.1 Multi-Way Partitioning for Heterogeneous Systems 278
8.8 .2 SYMTA- Symbolic Timing Analysis 281
8.9 Conclusions 281
9
Hardware/Software Partitioning using the LYCOS System 283
Jan Madsen, Jesper Grode, and Peter V. Knudsen
9.1 Introduction 283
9.2 Partitioning and Design Space Exploration 284
9.3 Overview of the LYCOS System 285
9.4 A Partitioning Session in LYCOS 288

9.5 Design Space Exploration with LYCOS 302

9.6 Summary 305
9.7 Acknowledgments 305
10
Cosmos: A Transformational Co-Design Tool for Multiprocessor Architectures 307
C. A. Valderrama, M. Romdhani, J.M. Daveau, G.Marchioro, A. Changuel, and A . A. Jerraya
10.1 Introduction 307
10.1.1 Requirements for Co-Design of Multiprocessor Systems 308
10.1.2 Previous Work 309
x HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

10.1.3 Contributions 310

10.2 Cosmos: A Global View 311
10.3 Design Models Used By Cosmos 314
10.3.1 Target Architecture 314
10.3.2 System Specification With SDl 315
10.3.3 Solar: A System-level Model for Co-Design 317
10.3.4 Communication Modeling and Refinement Concepts 321
10.3.5 Communication Refinement 322
10.3.6 Virtual Prototyping Using C-VHDl Models 325
10.3.7 C-VHDl Communication Model 325
10.4 Design Steps 327
10.4.1 SDl Compilation 328
10.4.2 Restrictions for Hardware Synthesis 328
10.4.3 Hardware/Software Partitioning And Communicat ion Refinement 330
10.4.4 Architecture Generation 336
10.4.5 VHDljC Cosimulation Interface 337
10.4.6 C-VHDl Model Generation 338
10.4.7 Prototyping 340
10.4.8 Hardware Design 341
10.4.9 Software Design 343
10.5 Application 344
10.5.1 Robot Arm controller co-design example. 344
10.5.2 C-VHDl Co-Simulation 348
10.5.3 Architecture Generation 352
10.6 Evaluation 354
10.7 Conclusions 356
10.8 Acknowledgements 357

References 359

Index 387
Contributing Authors

Thomas Benner
Institut fiir Datenverarbeitungsanlagen
Hans-Sommer-Strafie 66
D-38106 Braunschweig
Germany

A . Changuel
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

J. M. Daveau
System-Level Synthesis Group
TIMAjINPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

Rainer Domer
Department of Information and Computer Science
University of California at Irvine
Irvine CA 92691-3425
doemer@ics.uci.edu

Rolf Ernst
xi
xii HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

Institut fur Datenverarbeitungsanlagen

Hans-Sommer-StraBe 66
D-38106 Braunschweig
Germany
ernst@ida.ing.tu-bs.de

Dirk Hermann
Institut fiir Datenverarbeitungsanlagen
Hans-Sommer-StraBe 66
D-38106 Braunschweig
Germany

F. Hessel
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

Daniel D. Gajski
Department of Information and Computer Science
University of California at Irvine
Irvine CA 92691-3425
gajski@ics.ucLedu

Jesper Grode
Department of Information Technology
Technical University of Denmark
DK-2800, Lyngby
Denmark

Peter V. Knudsen
Department of Information Technology
Technical University of Denmark
DK-2800, Lyngby
Denmark

Ph. Le Marrec
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
 CONTRIBUTING AUTHORS xiii

F-38031 Grenoble cedex

France

Ahmed Amine Jerraya

System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France
jerraya@tima.inpg.fr

Clifford Liem
Laboratorie TIMA
Institut National Polytechnique de Grenoble
46, ave Felix Viallet
F-38031 Grenoble cedex
France
liem@tima.inpg.fr

Jan Madsen
Department of Information Technology
Technical University of Denmark
DK-2800, Lyngby
Denmark
jan@it.dtu.dk

G. F. Marchioro
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

Achim Osterling
Institut fiir Datenverarbeitungsanlagen
Hans-Sommer-StraBe 66
D-38106 Braunschweig
Germany

Pierre Paulin
SGS- Thomson Microelectronics
xiv HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

850, rue Jan Monnet

BP 16,38921 Crolles cedex
France
pierre.paulin@st.com

M. Romdhani
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

Wolfgang Rosenstiel
Universitat Tiibingen
Technische Informatik
Sand 13
72076 Tiibingen
Germany
rosenstiel@informatik .uni-tuebingen.de

Thomas Scholz
Institut fiir Datenverarbeitungsanlagen
Hans-Sommer-StraJ3e 66
D-38106 Braunschweig
Germany

J¢rgen Staunstrup
Department of Information Technology
Technical University of Denmark
DK-2800, Lyngby
Denmark
jst@it.dtu.edu

C. A . Valderrama
System-Level Synthesis Group
TIMA/INPG
46, ave Felix Viallet
F-38031 Grenoble cedex
France

Wayne Wolf
 CONTRIBUTING AUTHORS xv

Department of Electrical Engineering

Princeton University
Princeton NJ 08544 USA
wolf@princeton.edu

Wei Ye
Institut fiir Datenverarbeitungsanlagen
Hans-Sommer-StraBe 66
D-38106 Braunschweig
Germany

Jianwen Zhu
Department of Information and Computer Science
University of California at Irvine
Irvine CA 92691-3425
jzhu@ics.uci.edu
Preface

This book presents a number of issues of fundamental importance for the design
of integrated hardware software products such as embedded, communication,
and multimedia systems. Co-design is still a new field but one which has
substantially matured over the past few years. The book is inteded to provide:

• material for an advanced course,

• an overview of fundamental concepts in hardware/software co-design, and

• the necessary background for practioners who wants to get, an overview

of the area.

As an interdisciplinary field, co-design touches on a number of established dis-

ciplines . We assume at various points in the book that the reader has some
familiarity with a variety of topics ranging from concurrent programming lan-
guages through field-programmable gate arrays. Hopefully, our demands are
not too strenuous and the bibliography will supply readers with necessa ry back-
ground.
This book is the result of a series of Ph.D. courses on hardware/software co-
design held over the past two-and-a-half years . The first of these courses were
held at the Technical University of Denmark in August, 1995 and was sponsored
in part by the Danish Technical Research Council and the EUROPRACTICE
program. The second was taught at the Institut National Poly technique de
Grenoble in October of 1996 and was sponsored in part by the European Com-
mission under project EC-US-045. The third course will be held in Tokyo just
after the publication of this book, in December, 1997 and is sponsored by the
!EICE and Institute of System and Information Technologies, Kyushu. We
xvii
xviii HARDWARE/SOFTWARE CO-DESIGN: PRINCIPLES AND PRACTICE

would like to thank the sponsors of these courses for their generous support.
We would also like to thank the students for their patience and insight.

The Authors and Editors