Seat No.: ________ Enrolment No.

___________
GUJARAT TECHNOLOGICAL UNIVERSITY
BE - SEMESTER–VIII (NEW) - EXAMINATION – SUMMER 2018
Subject Code: 2181107 Date: 30/04/2018
Subject Name: Testing And Verification(Departmental Elective - III)
Time: 10:30 AM to 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

Q.1 (a) Describe VLSI development process with block diagram. 03

(b) Explain transistor fault model in detail. 04
(c) Describe importance of testing for VLSI design. 07

Q.2 (a) Give the definition of yield and explain different types of yield loss. Also 03
explain in detail reject rate.
(b) Explain in detail the cost of scan design in VLSI circuit. 04
(c) Write short-note on random access scan design. 07
OR
(c) Explain Muxed-D full scan design architecture in detail. 07

Q.3 (a) Explain how the problem of tri state buses can be overcome by scan design 03
rules.
(b) Explain wire delay model in detail. 04
(c) Explain with example deductive fault simulation method in detail. 07
OR
Q.3 (a) Explain how the problem of bidirectional I/O ports can be overcome by scan 03
design rules.
(b) Explain logic optimization process for logic simulation. 04
(c) Describe serial fault simulation method with example in detail. 07

Q.4 (a) Explain following terms: (i) Controllability (ii) Observability 03

(b) Draw and explain verification flow for VLSI circuits in detail. 04
(c) Describe simulation based verification method in detail. 07
OR
Q.4 (a) What do you mean by testability? Also explain the meaning of testability 03
analysis.
(b) Draw and explain scan design flow in brief. 04
(c) Consider the combinational logic circuit in Figure 1. How many possible 07
single stuck-at faults does this circuit have? How many collapsed single stuck-
at faults does this circuit have? Determine input test vectors that can detect all
single stuck-at fault.

1
 Figure 1

Q.5 (a) What is meant by test bench? Write advantages of test bench. 03
(b) Compare and contrast between compiled-code simulation and event-driven 04
simulation.
(c) Describe different types of test benches. 07
OR
Q.5 (a) What do you mean by hazards? Give definition of static and dynamic hazards. 03
(b) Explain in detail how a problem of node driven by unknown logic state is 04
overcome in simulation model.
(c) Write a VHDL program and test bench for half adder circuit. 07

*************