tA FETs AND DIGITAL . CIRCUITS Q1. Sketch the simple FET. ‘Ans: ‘The symbol for N-channel JFET is as shown in figure. | | 8 eas Figure: Symbol for N-channel JFET ' The field effect transistor is a three terminal semiconductor device that is similar to bipolar ‘transistor, that is, it can be used as amplifier and switch, bibik f * G2. What is JFET and give its different modes of operation?..: a Model Papers, tle) 5+ Junction Field Effect’ controlled by applied electric field. JFET can be operated in following three regions 1. Ohmic region ; | 2. Pinch-off region or saturation region “Transistor (JFET isan electronic device in which the flow of eurtent through conducting region is 3. Breakdown or cut-off region. | @3. Give some applications of JFET- Ans: ‘The applications of FET are given a8 follows, ‘ 1. Switches ES ie \ \ \ 2 Amplifier circuits 3, Voltage variable resistor (or) voltage dependent resistor‘ANALOG "AND DIGITAL ELECTRONICS (JNTU-HYDE} Jeulate the, pincholt Voltage of an.n — channel JFET having following specitentone Te 10". cm and metallurgical channel thickness is 0.75 um. . hf oe “. TM Given that, ' For.anin channel JFET, “Temperature, 7= 300K "Acceptor doping concentration, N, = 10" Donor doping concentration, N= 10'em?. ‘Thickness of channel, a= 0.75 am Pinch-off voltage,” =? . ‘The expression for pinch-off voltage of an N-channel JFET is given by, Here, > . ¢~Blectron change (1,6 10" C) fan £, ~Diclectric constant For silicon, 6, 11.7 * 8.85 % 10" From equation (1), we get, : ; Ty LGC SIO- PIO" 7 BH. 78.85%10-4 < Pinch-off voltage, V,= 4.35 V * Q5. What is MOSFET? Give its principle. “| Ans: % MOSFET: The acronym for MOSFET is Metal Oxide Semiconductor Field Effet Transistor. Its also known as insulted pt) field effect transistor (IGFET). TH fon Principle of MOSFET: The thickness ind resisaoe of conidudting channel of MOSFET are couitolied by applying trnsrem electric field across the insulator deposited on oxide layer. te Q6. State the significance of MOSFET devices. none 2NEAeT a OY Ans: a) Model Papers ‘MOSFET has high input impedance andlow output impedance, It provides less noise than BYT and hence used in gal processing application. The silicon area utilized by the MOSFET is less compared to that of BJT and hence used in ligestalt integration circuit. G7. Draw the circult diagram of common source FET amplifier. ‘Ans: The circuit diagram of common source FET ainplifier is shown in figure. Vo er fedooitee UNIT-3.(FETs and Digital circuits) : 3.3 FET - | Ther two ty = ~ oe HOSE re are two types of t Spe FET Thy Nhat | 1 | Tasan no ps or MOSER DO A JFET and P-channel JFET, 2, | JFETs can only be operated in the depletion mode. enhancement MOSFET and depletion MOSFET: It can be operated in the depletion mode and enhancement mode. 3, |- When a MOSFET is operated with reves ‘bias on the junction, the gate current is less, Compared to MOSFET, itis difficult to manufietufe. | 4. Most ie eal 4o manufacture. 5,.| FETS are widely used in analog circuits «| 5, | MOSFET are widely used in digital circuits. Q9. Why MOSFETs are used? — ‘Anst MOSFET are used due to following reasons, 1. MOSFET provides better system reliability i 2, The cost of MOSFEF is low and cireuit is very simple. 3. 4 3, | When a JFET is operated with rev junetion, the gate current is larger, read MOSFET can operate more efficiently at higher frequencies. * MOSFET has positive temperature coefficient which gives beter performance in linear applications and also iteliminstes the complexity of feedback circuitry. 5, The leakage current of MOSFET is very low. 6 Gate has full control over the operation of MOSFET and itis a majority carrier device. ‘10, Why the binary numbers system is used in digital systems? ‘Ans: : + Model Papert, a4) Generally, the devices employed in digital system operie in two modes ie, ON and OFF. Moreover, the signals consist | Feo tevels that are designated using inary mmber sem. Hence, the binary number systems are used in digital systems. | Git “Subtract (1070), from (1000), using 2’s complement method. ° ‘Ans: ~ Given that, (1000), ~ (1010), Where, * Subtrahend ~ 1010 ‘ Minuend- 1000 © Subtraction using 2s Complement |, + Sep 1: Finding 2s complement of sibtrahend, fo10 | 0101 (1's complement), joule +1. (@’s complement) o110 “Step 2: ‘Aang 2's copaperent of (1010);10(0000 : Pole O10 ‘ : +1000 aii ail S 1110 (Partial rest!)ANALOG i ies that ce of carry in the partial results speci ber. The final resuit is obtained by taking Step 3: The absent iti negative num! 2's complement of partial result. 1110 (Partial result). (0001 (1's complement) +1 @'s complement) 0010 (Final result) (1000), (1010), = (0010),= 2). [AND DIGITAL ELECTRONICS [JNTU-HYDERABAG) 101, from 1001, ‘The given binary numbers are, 101 and 1001 ’ ‘Then, the subtraction of binary numbers from 100} iy obtained as, 1001 =101 0100 F-clooty,- on), = 00); ‘GIZ_Add the following binary numbers, {a) 1041, and 1110, {b) 1101, and 110, ind 1110, The given binary numbers are, 1011. and 1110 The addition of above given binary numbers is obtained (011) +0110), =(101), 1101, and 110,: The given binary numbers are, 1101 and 110 ‘Theadgiton of above given binary nimmbers is obtained as, o —¢ Tior 110 1001 (10); +110), = Gooih, o) Ad. Divide the binary number 1100, by 100, An: Mode! Paper a4) ‘The given binary numbers are 1100 and. 100 ‘The division of binary number 1100 with 100s obtained 100)1100(11 too} 100 100 TW (1100), (100), = (11) Q15. Why NAND and NOR gates are called Universal gates? Ans: Model Paper, a1) Ingeneral, any Boolean expression can be implemented using AND, OR and NOT gates. While, these basic gates canbe implemented using NAND or NOR gate alone. This specifies that NAND or NOT gate alone can be used to implement any. Boolean expression, Hence, NAND and NOR gates are called universal logic gates, 13. Subtract the following binary numbers, fats: feornen ay a erie (a) 1001, from 1011, nisi (6). 101, from 1001, (@) 1001, from 1011, 7 man, eit Use to ignore delays ‘The given binary numbers are, 1001 and 1011 * Then,the subtraction of 1001 is obtained as, 1011 1001 binary numbers from 1011 to and to reduce the size and 61 mplexity of the circuit, Q17. Write short notes of Boose Writo short notes on Boolean algebra, Ans:uNIT-3_(FETS and Digital Circuits) ‘The basio operations performed by Boolemvalgebna are, 1, AND : 2 OR 3. Completnent (inverse), It is the basic mathematics used for the shidy of the gtal systems logic design. It has wide range of applications in various.areas such as, set theory, mathematical logic and switching circuits. So re 18. State DeMorgan’s theorem and mention its ‘Ans De Morgan’s Law: For any two variables, ‘4° and ‘B? in Boolean algebra, this theorem states that the complement of sum of logic variables is equal o the product oftheir individual ‘complements. ie, = A+B = AB For any two variables ‘A’ and ‘B" in Boolean algebra this theorem states that the product of logic variables is equal to the sum of their individual complements. ic, B= 447 Ans: Positive Logic Level: If the more positive or higher voltage level represents logie ‘1’ and more negative or lower voltage level represents logic ‘0” then, itis known as positive logic level. ‘The positive logic level representation is as shown in. figure (1) and table (1). Logic Level Signal Level 1 : 3.5 | ‘Negative Logie Level: If the more negative ox lower: oe . level represents logic ‘1" and more positive or higher vo ae represents logic ‘0' then itis known as negative logic level: ‘The negative logic level representation is as shown in figure (2) and table (2). Logis Level 0 Signal Level Q20. Draw the CMOS inverter circuit. Ans: |The cuit diagram of CMOS inverters shown in igure. ‘Voo Vr A Y= Vey v oD Figure: CMOS Inverter Q21. State the advantages of CMOS logic. Ans ‘Advantages of CMOS logic are as mentioned below. 1. Very low cost | 2. They run on ultra-low operating current ; | 2 sac | 4. High reliabitity ti 5. Simplified circuitina wide variety ofejuipmentdesign 6. Operate with wide voltage range.[ANALOG AND DIGITAL ELECTRONICS [JNTU-HYDERABAD) “PART-B ESSAY QUESTIONS WITH SOLUTIONS a 3.4 FETs isin 3.111. FET, Vl Charactorieties. 0) 22. Briefly explain about FET and its Importance. ue ; . thee terminal semiconductor device that i simile to biplat junction transistor. 1 cag Id effect transistors are the second generation transistors, developed after bipolar jurtction ‘Ans: The field effect transist be used as amplifier and switch, transistors (BIT"s). bo ‘The construction and operation of FETs is very different as compared to the bipolar junction transistors. : ‘The main difference is, oa 1. The operation of FET depends only on one type’of charge caries, ether free electrons or holes, rite the operation of BIT depends on both free electrons and holes. Hence FET is known as a unipolar device and BIT is known as bipolar device. 2. The operation of FET depends on drift of charge carriers under applied field, whereas the operation of BIT depends on Operation: The operation of P-channel JFET is as follows, ‘t jnals as shown in figure (3) Initially, with Vz, = OV and application of a voltage V, across the drain and souree terminals as shown in figure (3) ‘causes a current to flow from drain to source, Figure (3: Application of V,, Bete Ca Tae ate? chantel can be controled by spplyng a poditivé vonage to the gate and source términals 3 hewn in igure (8). The postive V, reverse bases the two PNsunction aad creases the Width of depletion regions. ca epletion region extends (or spreads) more into the P-channel becanee og doped lightly compared to n-regions. In other words, to make the depletion region extend more into, the P-channel, the two nregions are doped very heavily. Te Paation of depletion region decreases the width ofthe channel as showe’ ‘igure (4). This in tum decreases the current J, flowing through the channel, 3 saltv UNIT-3_ (FETs and Digital Circuits) 2 ~~inee the Girrent 1, Howing Through WS Sep ge ae oF pate 10 ‘ince the current J, flowing through the channel Is ‘éntrolled by gate voltage V,-, RET i ‘oc Iso known controlled device. ae een . Vest | Figure (5|: Channel at V,, Threshold 3. Continuous increase in the positive voltage Vj, can cause the depletion region to extend more and more into ‘the channel. Finally, the entire channel gets occupied by the depletion region and depleted of charge carriers (holes) as shown in figure (5). The value of V,at which | ‘the entire channel gets occupied bythe depletion-region js known as threshold voltage of the device ‘1. For 1 JFETs the threshold voltage is called the pinch-off | voltage and is denoted by “7,” i 26. Explain drain and transfer characteristics of ' JFET. } ‘Ans: ote Pape. a8 ‘A ploi of the drain current J, a8 a function of din to source voltage V;, keeping V,,constantis known as drain curve 1 or drain characteristics. Further, these are also known as VI ! characteristics or output characteristics of the JFET. Figure (1 illustrates the 7 characteristics, thats, the characteristics between drain current and the drain to source voltage Vp, for various values of gate to source voltage Vos, 39 "The VI characteristics are for varios values of ate t0 source voltage (V,) rom zero to negative, because Vcannot be positive. Case (i): Fér Vg= OV: Fixing the value of Voy t0 2270 volts (short circuiting gate ani source) and increasing the drain to source vltage fom OV in steps, causes a dain cuent Ip to flow through the channel. Initially, the current J, increases Finearly with Vag and becomes constant for Vn, V», The minimum drain-source voltage at which the drain current becomes constant is known 25 “pinch of voltage” denoted as *Y,’- When Vp Vy the depletion layers almost touch each other. channel width becomes 210). This pinches off or prevents a further increase in eurent. [An important thing o be observed in the characteristics is that when Vg,~ 0 V the current which is flowing between drain and source due to presence of small positive voltage Vg saturating value of that current is known 25 Ioss- T psi maximum current flowing in the device when V;,=0V-In other words, this is the maximum drain current 2 JFET can produce. Case (i): For Voy = Negative Value: Figure (1) illustrates the plot of F, versus Voq for negative values of Vi It can be ‘observed thats 7, becomes more and more negative, the drain current becomes very less. This is because the cross-sectional area of the channel decreases. At some value of gate to souree voltage Vj» the depletion layers extend completely across the channel and the channel is cut-off. Asa consequence, the drain current J; becomes zer0, The value of Vc,at which the channel is cut-offs called gate-source cut-off voliage Vos. Itis interesting to observe that the value of Vg... is equal and opposite to V,, that is if V,= 6 V then Vgg.5=— 6 V. Regions in the Characteristics: The V-Icharacteristics or drain characteristics of the junction ‘field effect transistor shown in. figure (1) is divi onic region Figure (1): VA Character (a: SPECTROM @LLAN-ONE JOURNAL FOR ENGINEERING STODENTS —— . SIA GROUP@ ~The region between 0- | | | ©© "Fei equation (2), equation (4) can be written as, | =2pss [Tos _ = 20 Ins “Ios Be Vp Voss Vp “ VossTos | 2 Eales Tos I — Q29. A FET follows the relation |, = - al : ep What are the values of |, and g,, for Vg, =— 1.5 | Vif ggg and V,are given as 8.4 mA and -3 V respectively? Given that, Fora Field Effect Transistor, Gate to source voltage, V,,=— 1.5 V Drain current when gate Source voltage is short circuited, Ig,= 8.4 mA Pinch-off voltage, V,=—3 V Drain current, J, ‘Transconductance, g = 2° ‘The expression for drain current, is given by, Vek 1,=1,,|i-"a3] fo“ aa]32, ANALOG Al “On substituting the corresponding values in equation (1), we get, 930. AFET has a drain current of 4 mA. If],,,=8 mA and V,,(off) = ~ 6 V find the values of V,, and Ve Ans: Given that, Fora FET, Drain current (/,) = 4 mA =4 « 1051 Source to drain curent (,) =8 mA = 8 10°A Curoff voltage, Yogyy=—6V ‘The expression for drain current in JFET is given as, 2 V% Ips| 1-—Las |) ag | Foster e Substituting the given values in equation:(1), we ge, : 4x10 = an>[i- fax ; ©). =-140.707=~0.293 6 «0.293 1.758 souree and drain, @. L ELECTRONICS [JNTU-HYDERABAD), \ND DIGITAL = nce, Pingh-of volia6®: Vp ¥,=F61 > =6V » 34.2 MOSFET Q31, Discuss your understanding on MOSFET detailing the types, construction and its cha: racteristics. 5 ‘Ans: Metal, oxide semiconductor field effect transistor (MOSFET) is a type of FET and is commonly constructed through the, controlled oxidation of silicon material. It is also, known as insulated gate field effect transistor (IGFET). It ig * further classified into two types as, ‘1, Depletion MOSFET 2. Enhancement MOSFET. 1.” Depletion MOSFET Construction: The N-channel depletion MOSFET is constructed on a P-type silicon substrate as shown in figure (1). The substrate is a single crystal silicon wafer that provides Physical support for the device. Paype substrate re (1): Ptypo Substrate ‘two "regions, thats, an N-channel is implanted as. ‘shown in figure » Ly | N P-type substrate TFigure (3) A thin layer of silicon dioxide (SiO.) that wn} face ofthe substrate through oxidation ioxide (SiO.) that is an electrical insulator | i s shithors wom to electrical insulator grown on the surface ofthe rough oxidatic ‘N-channel P-type substrate Figure (4) Formation of metal and oxide layer creates a MOS capacitor, ‘The metal of the gate and the semiconductor acts as plates rasulator of the MOS capacitor. Finally, metal is deposited on.top of the oxide layer t© ‘contacts are also made tothe source region, the drain Fegion and the substrate, The ‘terminal (G), source terminal (S), drain terminal (D), and the substrate (also of capacitor and the oxide layer acts asi foim the gate electrode of the device. Meta device is packed and four terminals namely gate known as body) terminal (B) are taken out as shown in figure (5). Source _ Gate Drain ‘N-channel Payjpe substrate Figure (5): Structure of Depletion MOSFET «The principle of operation of MOSFET depends onthe MOS capacitor. D-MOSFET requires th e gate Principle of Operation’ f " ernce yliage- Vio wwii tbe devin OFF Te aan of D-MOSFET is as follows. . - iL FOR ENGINEERING STUDENTS z z ———_— ‘SPECTRUM ALL-IN-ONE OURNA! SIA GR N OUP 5ITU-HYDEI 3.14 ANALOG AND DIGITAL ELECTRONICS [NT an Tet a .: in appl ; Tnitially, when gate to source voltage Vis equal to zero and positive voinwe ere dran-to-a0urve voltage. There Jharge earers ie, electrons inthe N-channel ae attracid by the positive termi tage is made negative anda posite eect the N-channel between the two 1" regions. When gate-to-source v ative terminal of gatetosou | peridiriacieiers cies Vay the electrons in the N-channel are repelled by the negé vend | ‘voltage is applied between drain and source, V,, the el ive terminal of gate to source Voltage. Inthy ‘voltage and the holes which are majority carriers in p-substrate are attragted by the negative ris the gute terminal. Asa the electrons moving away from the gate terminal recombine with holes moving en han ci is ten ‘anh number of free electrons involving in the conduction of gurrent are dela ‘current . flowing ’ through the device. Finally, at Vj, = Vaeonmy Jpbecomes zero and the device operates s Fi 4 Incontrast tothe JFET, the D- MOSFET can be operated for positive value of gate to — ieee) yor ‘! pas the insulation of gate terminal from the semiconductor body. Increase in the value otros vege en os 1 i of free electrons flowing though the channel. This in tum nicreases the current /,, The charac shown, in figure (6). ~ 1, Enhancement Toss, (6): Vs Characteristies . 2. * Enhancement MOSFET: i i Construction: The N-channel depletior °n MOSFET is constructed on a P-type silicon bar knot (7). The substrate is a single erystal sil wn as substrate as shown in figure licon wafer that provides physical support for the devi 4 Paype substrate ~ Figure (7: Pype Substrate ‘Two heavily doped n-regions are diffused into the substrate'as shown in figure (8). The n-regi indi ‘i the figure, The wo W: regions act as source and dain forthe MOSFET. (Te mein cinta "a { wv] Ne P-type substrate | a HOM Figure (8) Look. for thé SIA GROUP Loco SOVER before you buyUNIT-3_ (FETs and Digital Circuits) 4 thin-layer of silicon dioxi “The 1 f ioxide (SiO,) that i electrical insulator is grown on the surface of ro heen through oxidation’ process as shown in figure (0). Ptype substrate Figure (8) Formation of metal and oxide layer creates a MOS capacitor. The metal of the gate and the semiconductor acts as plates of capacitor and the oxide layer acts as insulator of the ‘MOS capacitor. Finally, metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are also made to the source region, the’ drain region anid the substrate. The device is packed and four terminals as the gate ‘terminal (G), the source terminal (S), the drain terminal (D), and the substrate (also known as body) terminal (B)are indicated as shown in figure (10). Drain Source _ Gate P-type substrate Body (or) Substrate Figure 10}: Structure of Enhancement MOSFET Principle of Operation: The principle of operation of MOSFET depends on the MOS capacitor E-MOSFET requires the ante source voltage V0 switch the device “ON”. The operation of E-MOSFET is as follows. Initially, ven gate to source voltage Voss eH¥81 102570 and’ postive voltage is applied between drat snd source becailse, there is no inand source, Vos, no current flows between drain a ‘When gate to source voltage Vis made positive and positive voltage is applied between drain and. source, the positive voltage repels the holes present below the oxide layer and attracts the electrons present in the substrate towards the insulator. The electrons attracted get accumulated’ between source and drain beneath the insulator forming an N-channel. ‘This isan induced channel. Bécause of positive Vg, there is @ flow of current between source and drain through the induced channel. The value of Vg. above which current starts lowing, between drain and source is known as threshold voltage Vive Tn other words, the minimum value of Vx that induces chanel is known as threshald voltage denoted a8 Vy If drain to source voltage Vj increased continuously keepinig Vj, constant, then the width of the channel! changes. “The width is maximum atthe source and is less riear drain. At a particulat value of Vg the channel reduces to a point whiere the drain current gets saturated. The V-I'characteristics of, E-MOSFET are as shown in figure (11). 1 Figure (11): V4 Characteristics Q32. Discuss the characteristics of P-channel MOSFET. Ans: Phi WOOP ts Vaupagslian Chloe Hides G) shows the construction of P-channel enhancement type MOSFET. Two highly doped P* regions work as source and drain, Between these two P* regions a P-type channel is induced. A thin layer of SiO, is deposited over the surface. ‘The gate, source and drain connections are made by depositing Aluminium ver SO, lye,rs 3:16 : * ‘Operation: Ifthe gate voltage is made negative and N-type substrate (with minority charge carriers as holes) is grounded, then due to the capacitor action the positive charges are ‘induced near the semiconductor layer. This in turn, generates an inversion layer. As the negative gate voltage is increased, the induced positive charge (P-type éarriers which are restricted to, enter into the thin channel) diffused into the semiconductor. For an applied positive voltage between the source and drain, the induced P-type carriers transmit current from source to drain. From this, itis observed that for negative gate voltage the conductivity of the induced channel increases, ‘which intum enhances the drain current. This can be seen in drain characteristics ofthe device for varying drain current, with drain-to-source voltage, Vp, and constant gate-to-source voltage, V,, as shown in figure (2). (mA) Figure (2k: Drain Charaterists of Pchanel Enhancement MosFET Figure (3) shows the transfer characteristics of thé enhancement mode P-type MOSFET, describing variations in drain current J, with input gate Voltage V,. for'constant values of Fag n(mA) Vol) « 6 $4321 Vy Figure (3: Transfor Characteristic of PchannelEahancement ‘ANALOG AND DIGITAL El LECTRONICS [JNTU-HYDERABAD, points are observed from the above gue” Following (For Pgy 2 sf is very small. » : (i) For Vay <0, magnitude of Zp slowly increases iniay | and then increases rapidly with [Yo ] (ii) The voltage at which a small value off, is obtained jg ‘known as gate to source threshold voltage, Y, which jg | typically ~4 V for P-channel MOSFET and the én | supply voltage is ~12 V. P-channel Depletion MOSFET: Figure (4) shows the constructin of P-channel depletion type of MOSFET, jj consists of N-type substrate and P-ype source and din terminals and a channel. 7 iP ‘ja P) Figure (4: P-channel Depletion Type MOSFET Operation: Depletion occurs when a semiconductor substrate (here N-type) is diffsed with the similar impurity used in forming source and drain prior to the deposition of oxide layer. ‘The drain characteristics of P-channel depletion type MOSFET are shown in figure (5). x Figur (5: Drain Characteristics of P-chanial Depletion Type MosFet Type MOSFET ion betiveen J, and Vz, are as shown figure ( Look for the SIA GROUP Loco n the TITLE COVER before you bi Qu buy cxf charts of P-chann} ?. i ics of P-channel depletion MOSFETUNIT-3 (FETs and Digital Circuits) sani ay gins I,(mA) 123.456 Vos), v, Figure (6): Transfer Characteristics of P-channel Depletion Type MosreT ‘This is a mirror image of transfer characteristics of. ‘N-channel depletion type MOSFET about the y-axis ie, ee Ee Q33.. Discuss the effect of channel length modulation. Ans: i “The actual characteristics of MOSFET are illustrated in figure below. Jo, | Vo n 3 Te Manny : 4 Figure: MOSFET | Charatteristics i jion indicates the ‘non-zero slope in saturation region in Aes GeMe ‘due to channel length modulation i.e., decrease in length of the channel above Saturation point. ForanN-channel MOSFET, the slope ofthe characteristic curve is defined interms of drain current aS, ae KylVos-Yn 1 *¥os) Where, K, ~ Conduetion parameter (1) + Vy~ Threshold voltage 4. Channel length modulation parameter. ‘The expression for output resistance is obtained: a5; f , Slope of curve © * yo jew ‘Alyy » (ae) thsdanatt _ . “ay : fares ‘Substituting equation (1) in above equation, we get, 3 I 1+ AV, : [spclelPs Fry} ( ol 1 = [Ky os Pn OY “Henle At operating point, besos, % ag pune ¥, Il = Pool". ee, Ugg Quien current Vase 1 "e Expression for Drai Current in. MOSFET: Equation (1) signifies that in saturation, J, is independent of V. Hence, there isno change in J, fora small change in the drain to source ‘voltage. This indicates thatthe increasing resistance looking into the drain of a saturated MOSFET is infinite. Once the channel is pinched-off at the drain end, an additional increase in V,,, hhas no effect on the shape of the channel. However, in practice, increasing Vj, above Vi... effects the channel. Specifically, 48 Fog inereases, the channel pinch-off point moves slightly away from the drain the additional voltage applied to the drain ~appears as a voltage drop across the narrow depletion region between the end of chiannel and drain region. The electron moving from source to’ drain terminal increases the width of depletion-layer asia result; the channel length is reduced, This phenomenon is known as channel I modulation. length PD i a, SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS ei ep weD DIGITAL ELECTRONICS [JNTU-HYDERA\ 3.18. ANALOG.AN! “spring KVL to output loop, We Be ; i The expreston for current [,, of an N-channel | ‘enhancement MOSFET in saturation is, i 1 Wt | fog = RT Wos- Ad ow (@) | To explain the dependence of J, on V,, in saturation, | replacing Z in equation (1) with (LAL), we get, K _W | Jos =F THE Vos Vn” BEE (ri) arta? = @) AEE BO ry Since, 44 < Vos = Von * tos =5-(04x5) =3V : Saturation voltage, Vs yay = Vos Fw : =0-(2) =2v Since, Vag > Vos any the MOSFET is operating iq saturation region. 0.4 mA . ¥ v Drain currents, Drain to source voltage, Vay Q35. When the gate to source voltage V,. of 4 ‘ MOSFET with threshold voltage of 400 mV is. "900 mY, the drain current is observed to bet mAand assuming that the MOSFET is operating in saturation, calculate'the drain current foran_ applied V., of 1400 mV. Ans: Given that, “Fora MOSFET, Threshold voltage, ¥, =400 mV Gate to source voltage, V;., = 900 mV. ‘At Vg, observed drain current, J, =1mA Gate to source saturation voltage, Vou = 1400m¥_ At Voy drain current, J,,~? ‘The expression for drain cutent is given by, T= KV Vat cinta From the above relation, it can be seen tha te dia oat ditectly proportional to square of difference of the saturation Voltage and threshold Voltage. ©? P= Vos)? to