Thermally Stable Iridium Contacts to Highly Doped p-In0.53 Ga0.

47 As for Indium
Phosphide Double Heterojunction Bipolar Transistors

M. Brahem1,* , A. Mogilatenko1,2 , D. Stoppel1 , D. Berger3 , S. Hochheim1 , D. Rentner1 ,

I. Ostermay1 , M. Reiner 1 , S. Boppel1 , K. Nosaeva1 and N. Weimann1,4
1 Ferdinand-Braun-Institut, Berlin, Germany
2Humboldt-Universität, Berlin, Germany
3 Technische Universität Berlin, Berlin, Germany
4 Universität Duisburg-Essen, Duisburg, Germany

* Corresponding author : mohamed.brahem@fbh-berlin.de

Abstract
We report on surface pretreatment for ohmic contacts to p-doped In0.53 Ga0.47 As with improved thermal stability. It
is found that the cleaning of In0.53 Ga0.47 As surface by ammonium sulfide or sulfuric acid offers the optimum surface
treatment prior to metal deposition. Contacts using an iridium contact layer and palladium diffusion barrier were
fabricated and compared to a conventional platinum-based contact Pt/Ti/Pt/Au . Pt-based metal stack suffered from
void formation and high reactivity with the semiconductor when annealed at 240°C for a few hours, as examined by
transmission electron microscopy. As a result, the Pt-based stack exhibited strong deterioration of the resistivity. On the
other hand, the Ir contact maintained its integrity during thermal stress. The improved contact exhibited a void and
reaction-free microstructure and offered stable resistivity values with annealing.

Keywords : InP, HBT, ohmic contacts, InGaAs, Iridium, Platinum

1. Introduction desirable feature of Pd/Pt is the observed penetration or

Ohmic contacts to p-type In0.53 Ga0.47 As have been ex-
tensively analyzed because of their important applications
as base contacts for InP DHBTs. The InP transistors offer
fast diffusive and ballistic electron transport, low noise fig-
ures and high breakdown voltage compared to their silicon
or SiGe competitors. This makes them particularly attrac-
tive for ultra-high speed applications such as optical ICs
operating at over 100 Gbit/s and high data-rate wireless
communications at frequencies beyond 100 GHz. Transis-
tors using the InP/InGaAs material system with fT /fmax in
excess of 0.5/1 THz have already been demonstrated by
some research groups [1, 2] . Pushing these transistors to
THz frequencies is directly related to the quality of their
ohmic contacts and in particular to the p-In0.53 Ga0.47 As
base resistance. Hence there is a strong incentive to de-
velop low resistance ohmic contacts to p-InGaAs.
There have been several reports on non-alloyed ohmic
contacts to p-In0.53 Ga0.47 As. Pt/Pd-based contacts to p-
In0.53 Ga0.47 As are the standard metal scheme in III-V de-
vice fabrication processes [3, 4, 5, 6]. Studies with
these metals, particularly Pd as first layer, yielded ex-
tremely low as-deposited contact resistance, in the or-
der of 2×10−8 Ω.cm2 [7, 8, 9], thanks to uniform and
metastable Pdx InGaAs phase formation. Another reported
Preprint submitted to Elsevier
displacement of the native oxide [10, 11]. All these fa-
vorable attributes made these contacts attractive for fab-
rication of early generations of InP transistors. With the
contineous maturing of the In0.53 Ga0.47 As technology, reli-
ability studies concluded that the thermal and mechanical
stability of Pt/Pd-based contacts are limited. Dormaier et
al. observed a formation of voids inside the Pt layer with
long thermal exposure [11]. This mechanism, known as
Kirkendall voids, was attributed to the diffusion of the Pt
and its reaction with adjacent materials.
Therefore contacts that can guarantee a thermally sta-
ble behavior and resist rapid chemical reactions are re-
quired. Recently, low in-situ specific contact resistance
(5.8×10−9 Ω.cm2 ) was reported by Baraskar [12] on a rela-
tively thick (100 nm) 2.2×1020 cm−3 carbon doped (p-type)
InGaAs layer using an iridium-based metal stack (deposi-
tion of metals immediately after epitaxial growth, with-
out breaking vacuum). Values of 5.5 × 10−9 Ω.cm2 to a
similar epitaxial configuration was reported by Lobisser
[13] using tungsten contact, with a pretreatment consist-
ing of multiple cycles of ultraviolet (UV) ozone oxidation
and subsequent HCl 1:10 etching.
In this report, the surface preparation and the ther-
mal stability of contacts to p-In0.53 Ga0.47 As are addressed.
The effectiveness of oxide removal of different pretreat-
May 16, 2019
ment solutions and their impact on the resistivity were
analyzed. Afterwards, the interfacial microstructure and
the electrical behavior of contacts made of noble (Pt) and
refractory (Ir) metals were investigated as the contact is
aged. The need for a more detailed understanding of
the refractory metals was motivated by the scarce num-
ber of studies using these metals as contact layers to p-
In0.53 Ga0.47 As despite their promising potential. This arises
from complications related to their integration into a full
DHBT process, where the evaporation at a high melting
point can damage the photoresist making the liftoff pro-
cess difficult.
and emitter layers located on top of the stack were re-
moved in a successive H2 SO4 : H2 O2 :H2 O and HCL:H3 PO4
wet etching solution. The In0.53 Ga0.47 As mesa isolation
was defined after a second lithography and wet etch using
the same solutions. After collector lithography and wet
etch mesa formation, the resist was lifted off and the final
lithography step was carried out by spin coating, exposing
and developing 1.7 µm of AZ nLof 5510 negative resist.

2. Fabrication

Three epitaxial wafers were grown by Solid Source

Molecular Beam Epitaxy (SSMBE) on a semi-insulating
(001) InP substrate. (Table 1)
Various test features were included in the layout, such
as refined Transfer Length Method (TLM) structures, (see
[14]), with nominal gap varying between 1 and 5 µm.
Gaps greater than 5 µm were avoided considering that
large exposed semiconductor areas can suffer from pro-
cessing damage and surface oxidation. This will give rise
to fluctuating sheet resistance resulting in noisy extracted
contact resistance. In addition, Van Der Pauw structures as
well large area transistors were part of the layout. These
additional structures were implemented to provide an al-
ternative method of extracting the contact resistance and
to assess the impact of the metalization scheme on the sta-
bility of the transistor’s current gain.

Layer Material d (nm) Doping (cm−3 )

Emitter Cap In0.85→0.53 Ga0.15→0.47 As 30 5×1019 :Si
Emitter 1 InP 80 3×1019 :Si
Emitter 2 InP 10 8×1017 :Si
Emitter 3 InP 40 5×1017 :Si
Base In0.53 Ga0.47 As 30 7→4×1019 :C
Setback In0.53 Ga0.47 As 20 6.5×1016 :Si
Grade InGaAs/InAlAs 24 6.5×1016 :Si
Delta Doping InP 3 2.75×1018 :Si
Collector InP 73 6.5×1016 :Si
Sub collector InP 5 1.0×1019 :Si Figure 1: A sketch illustrating the patterning and the passivation of the
p-type structures.
Sub collector In0.53 Ga0.47 As 30 3.0×1019 :Si
At this stage, just before the metal deposition, the
Table 1: The epitaxial structure used in this experiment. A compositional wafers were laser-diced and each die was marked on the
grading is present on the topmost layer while the carbon p-doped region backside. Contacts were then sequentially e-beam evapo-
has its doping graded from 7→4×1019 cm−3 from top to bottom. rated on carbon doped In0.53 Ga0.47 As. The p-type region is
30 nm thick and has its dopant concentration graded from
The process flow is illustrated in figure 1. A combina- 4-7×1019 cm−3 in the growth direction, providing a quasi-
tion of optical lithography and selective wet etching using electric field that accelerates the electrons in the base and
the resist as a photomask was used to define the test struc- therefore reduces transit times. A scanning electron micro-
tures. Prior to every lithography step, the wafers were de- scope (SEM) image of the final structure is shown in figure
greased in IPA and rinsed in de-ionised water (ρ > 15 MΩ). 2. On each fully processed chip, the width of the gap sep-
To access the p-InGaAs layer, the transistors were masked, arating adjacent metal contacts was verified by SEM for
2
accurate TLM contact resistance extraction.
Non-alloyed metal layer sequences were deposited onto
the samples using electron beam evaporation (Pfeiffer
Classic 580) in a single pumpdown cycle, under 2×10−7
mbar chamber pressure. In our InP DHBT MMIC process,
there is a considerable thermal budget associated with
repeated benzocyclobutene (BCB) deposition and curing
cycles, which require a process temperature of around
240°C. To better understand the impact of the thermal
budget on p-InGaAs contact resistance, selected samples
were annealed in a nitrogen environment at 240°C for
7 hours and measured every few hours. The p-InGaAs
surface is extremely sensitive to any organic residues
or oxidation, which makes it challenging to obtain ul-
tra low contact resistance. Therefore, considerable at-
tention is required to cleaning the surface without in-
troducing damage to the semiconductor. Samples were
kept under nitrogen atmosphere to ensure minimal expo-
sure to clean room air and reduce contamination prior
to processing. Three samples were chosen as our refer-
ence measurement. The configuration was made identi-
cal to the metalization scheme and pretreatment for our
baseline transistors, i.e. a metal stack of Pt/Ti/Pt/Au
10/15/15/200 nm and a surface cleaning using dilute sul-
furic acid H2 SO4 :H2 O 1:10.
To exclude the influence of surface oxidation during
the long-time annealing experiment, a surface passivating
layer consisting of 80nm of silicon nitride (SiNx ) was de-
posited in a low-temperature (70 °C) inductively coupled
plasma-enhanced chemical vapor deposition system (Sen-
tech SI500D) prior to annealing. Openings for the mea-
surement needles were etched using SF6 reactive ion etch-
ing. The SiNx is instrumental to passivate the semiconduc-
tor and reduce surface recombination. Four-points probe
measurements were performed using a Keithley 7000 An-
alyzer. Transistor Gummel plots, I-V curves and TLM mea-
surements of as-deposited and annealed samples were car-
ried out to evaluate the stability of the contact under long
term thermal stress.
Specific contact resistance (ρC ), sheet resistance (RSH ),
contact resistance (RC ) and transfer length (Lt ) were ex-
tracted using the TLM method. The data were averaged
over a large number of samples, consisting of tens of data
points from the same die or from separate samples pro-
cessed under the same conditions, indicating intra-die,
inter-die and inter-wafer process variability.
3. Surface pretreatment
The metal-semiconductor interface directly influences
the barrier height and thus the current transport mecha-
nism. In theory, the heavily doped bulk region is expected
to guarantee pure field emission. However native oxides,
ion damage defects and metallurgical modifications dete-
riorate the tunneling process or displace the Fermi level.
It is therefore desirable to remove surface residues and to
minimize the thickness of the interfacial oxide layer.
3
Gap
Metal
W
p-In0.53Ga0.47As
Figure 2: SEM micrograph of the TLM structures before the SiNx passi-
vation.The In0.53 Ga0.47 As mesa isolation is visible on the image. Various
gaps and widths configurations were carefully chosen to maximize yield
and ensure reliable extraction of the results.
The objective of this experiment was to establish the op-
timum chemical surface treatment that provides a reduced
level of native oxide while minimizing the In0.53 Ga0.47 As
consumption. The sample treatment consisted of dip-
ping in various aqueous solutions : hydrofluoric acid (HF,
49%), hydrochloric acid (HCl, 39%), ammonium sulfide
((NH4 )2 S, 20%) and sulfuric acid (H2 SO4 , 96%), followed
by a rinse in DI water and surface drying with a N2 gun. All
chemicals were diluted 1:10 in water, except the HF which
was diluted 1:20. The summarized results are shown in
table 2.
The HF-treated samples consistently exhibited the low-
est ρC throughout the experiment. It was possible to
achieve specific contact resistance values of 28.3 Ω.µm2
(Figure 3) .
It is thought that the HF chemistry ensures the complete
removal of In2 O3 and As2 O5 native oxides [15]. The inti-
mate nature of the contact was elucidated by the slightly
higher sheet resistance, suggesting that the etching solu-
tion suppressed the entire interfacial oxide and consumed
a few nanometers of semiconductor material. However,
the benefits of using the pure hydrofluoric acid are off-
set by its incompatibility with the PMMA e-beam resist.
Samples treated with HF experienced cracks and delam-
inations in the resist chemistry rendering any liftoff or
evaporation unusable. This limit its practical application
to optical lithography or a pretreament before a blanket
deposition.
Samples treated with HCl 1:10 for 20 s repeatedly
showed a large statistical variation of resistivity among
the structures 3. This might be attributed to an inhomo-
geneous oxide removal. In addition, within all the sam-
ples treated with HCl, no relation between the metal work
function and the specific contact resistance was found.
This result can be explained by the Fermi level pinning
in the valence band due to the high level of surfaces states
associated with the interfacial oxide film [16].
To prove the assumption of incomplete oxide removal
 Pretreatment, Pt/Ti/Pt/Au metal stack
H2 SO4
ρC [Ω.µm ] 2
40.1 ± 1.68
RSH [Ω/] 710 ± 15.9
RC [Ω.mm] 0.18±0.02
Lt [µm] 0.24±0.11
Table 2: Summarized results of the surface pretreatment comparison,
using the baseline Pt/Ti/Pt/Au 10/15/15/200 nm metal stack and an
acceptor doping linearly graded from 7 to 4×1019 cm−3 .
by the HCl treatment, structural analysis by transmission
electron microscope was carried out. Figure 4a shows
the results of the TEM on a cross-sectional lamella pre-
pared by focused ion beam (FIB). The lamella consisted
of a Pt/Ti/Pt/Au 10/15/15/200 nm metal stack deposited
onto an In0.53 Ga0.47 As surface pre-treated with HCl. The
analysis revealed an about 4 nm thick amorphous layer
at the interface between the Pt layer and the semicon-
ductor. Electron energy loss spectroscopy (EELS) analy-
sis showed the presence of an oxygen signal in the inter-
facial layer (Fig. 4b), proving the presence of a surface
oxide despite the HCl treatment prior to the metal depo-
sition. No Pt/InGaAs interdiffusion was observed in the
as-deposited sample. Even though the formation of a thin
oxide layer adjacent to the semiconductor can sometimes
exhibit a high quantum tunneling transparency [17, 18],
it often can result in a severe degradation of the transport
mechanism properties. Thus, it is important to be able to
remove the remaining oxide reproducibly.
1 0 0
9 0
8 0
7 0
2
]
R e s i s t i v i t y [ Ω. µm
6 0
5 0 H 2 S O 4
4 0
3 0
2 0
1 0
M e ta l s ta c k : P t/T i/P t/A u 1 0 /1 5 /1 5 /2 0 0 n m
0 and an ion current of 15.6 A. The Ar+ bombardment was
Figure 3: Comparison of the measured as-deposited resistivity of the
different surface treatment. Consistent testing was used for metal stack
and processing conditions.
In contrast, the samples treated with H2 SO4 and
(NH4 )2 S emerged as a good compromise. Both solutions
showed similar behavior, with relatively low resistivity,
reasonably low sheet resistance and transfer length (Table
2). It is well documented in the literature [19, 20, 21] that
the sulfur passivation can effectively inhibit oxide growth.
Sulfur atoms tend to form strong bonds with the InGaAs
and act as a passivating agent against re-oxidation after
removal from the solution and exposure to air. Numer-
HCl HF (NH4 )2 S
ous studies [22, 23] observed that Schottky diodes treated
55.0 ± 19 28.3 ±5.7 36.5 ±2.34 with (NH4 )2 S exhibited reduced barrier height and leak-
672± 10.9 788±15.2 740±4.95 age current compared to HCl.
0.21±0.03 0.14±0.01 0.16±0.004
0.25±0.06 0.19±0.02 0.22±0.007
Figure 4: a) Cross-sectional TEM micrograph showing as-deposited metal
/InGaAs interface for baseline metallization Pt/Ti/Pt/Au 10/15/15/200
nm. The InGaAs surface was pretreated by HCl prior to the contact de-
position. b) EELS spectrum obtained using an electron probe size of 0.7
nm at the amorphous interfacial layer. The spectrum shows the O-K edge
indicating the presence of an oxide layer.
Of particular concern was the precleaning of the surface
with low-energy Ar+ ions. In contrast to the chemical pre-
cleaning, the Ar+ bombardment is an in-situ, non-selective
etching process. The Ar+ ions ensure the removal of the
native oxides, but introduce radiation damage to the sub-
surface layer, vacancies, interstitials and other complex
defects [17]. Typically a thermal processing step is re-
quired after Ar+ bombardment to restore the stoichiome-
try of the damaged layer [17].
There have been a number of different successful attempts
[24, 25] demonstrating a particularly low contact resistiv-
ity (6×10−8 Ω.cm2 ) using argon bombardment as a replace-
H C l
ment to wet pre-cleaning, however, since the process is
H S O + A r +
S p u tte r in g
2 4
non-selective, a certain amount of semiconductor will be
etched unavoidably. This is highly undesirable considering
that the base in a modern InP-DHBT is typically less than
30 nm thick. Even the removal of a thin layer of semi-
conductor will increase the sheet resistance. Moreover, in
(N H )2S
H F
4
a graded doping base design, it is critical to preserve the
highly doped surface layer in order to minimize the tun-
neling barrier thickness.
In this experiment, medium voltage argon sputtering at
90 V for 120 s was used with an Ar-gas load of 8.25 sccm
combined with a chemical pretreatment by H2 SO4 , con-
sidering that a thin layer of oxide readily forms while
loading the sample into the vacuum chamber. Moreover,
reaching the required chamber pressure takes a couple of
hours. This processing sequence has been established as
optimal on a similarly doped n-type In0.53 Ga0.47 As based
on previously carried out TLM measurements. On the p-
In0.53 Ga0.47 As surface, however, this process introduced an
extensive damage to the surface layer leading to higher
resistivity values. Therefore, it is desirable to have a de-
tailed understanding of the Ar+ bombardment etch rate
4
and the exact thickness of the p-In0.53 Ga0.47 As native oxide
before proceeding with this process in order to neutral-
ize its detrimental effects. In summary, the H2 SO4 and
(NH4 )2 S pretreatments offered an acceptable consump-
tion of In0.53 Ga0.47 As and an effective removal of native
oxides. The cleaning of the surface with Ar+ ions should
be used with caution, as it can introduce ion damage, re-
sulting in poor electrical performances.
4. Thermal Stability
Boosting the operation speed of DHBTs requires the
scaling of transistors for parasitic capacitance reduction
and increasing the current density for faster charging
times. Both approaches lead to significant heat genera-
tion inside the device and thus an instability at the metal-
semiconductor interface. In addition, the devices have to
withstand a considerable amount of heat exposure during
the BCB planarization processes and other thermal fabri-
cation steps, such as InP dry etching or plasma-enhanced
chemical vapor deposition of nitride layers.
Thus, to evaluate the contact thermal stability, sam-
ples with Pt/Ti/Pt/Au 10/15/15/200 nm contact to p-
In0.53 Ga0.47 As, cleaned with H2 SO4 were annealed for 7
hours at 240°C under constant flow of N2 . The first layer
of platinum is the contact layer, the thin Ti layer acts as an
adhesion film and the second Pt is the diffusion barrier.
Following the annealing process, a microstructural in-
vestigation using TEM revealed two major phenomena:
extensive void formation in the nearly unreacted region
of the platinum layer as shown in Figure 5, and deep pen-
etration of the platinum into the semiconductor. The voids
are thought to be caused by a Pt flux toward the lower re-
action region that is not being balanced by a correspond-
ing flux of group III and group V elements in the opposite
direction [11]. No oxide layer was detected, confirming
previous studies that Pt disperses the native oxide in III-V
semiconductors during annealing [11, 10, 26, 27]. The
decomposition of the native oxide could be a contribu-
tor to the formation of voids, although this theory would
have to be examined more thoroughly. Throughout the
experiment, the semiconductor sheet resistance between
the structures remained fairly constant suggesting that the
heat treatment has minimal impact on the carrier density
at the exposed semiconductor surface. This result also in-
dicates that the metal diffusion in the semiconductor was
mainly vertical. The SiNx passivation effectively protected
the gap region from charge related degradation, but did
not thermally isolate the contact. The voids in the metal
stack, however, represent a serious mechanical degrada-
tion, an issue to be addressed in order to ensure long-term
device reliability.
The second mechanism responsible for the deterioration
of the contact is the diffusion of the platinum and its re-
action with In0.53 Ga0.47 As. During annealing, the platinum
moves deeply into the reaction region. Because of the ex-
istence of a doping gradient in the base layer, the metal-
5
Figure 5: High-angle annular dark-field scanning transmission elec-
tron microscopy (HAADF STEM) micrograph of the Pt/Ti/Pt/Au
10/15/15/200 nm contact structure after annealing at 240°C for 7 hours.
Voids appeared in the non reacted Pt layer, and strong intermixing is ob-
served between the In0.53 Ga0.47 As and Pt lower region.
semiconductor interface will be pushed to a lower-doped
region. As the contact is exposed to more heat, the plat-
inum continues to sink into the InGaAs, consuming more
semiconductor material and leading to severe degrada-
tion of the tunneling proprieties due to the wider space-
charge extension. This adds further metallurgical insta-
bility and compromises yield and reliability of the device.
Figure 6 illustrates the EDX depth profile of a Pt/Ti/Pt/Au
metal stack after annealing for 7 hours. The platinum
intensity does not drop sharply at the interface with the
In0.53 Ga0.47 As and the intermixing between the layers ex-
tends over several nanometers.
The process produces a Pt-In-Ga-As sublayer and si-
multaneously depletes the Pt film as a result of the out-
diffusion, resulting in void formation and the intermixing.
The second reaction region was not conclusively identi-
fied, although other studies speculate it may consist of the
following intermetallics : Ga3 Pt5 , GaPt, In2 Pt, InAs, InTi3 ,
Ti2 Ga3 , and GaPt3 [28, 29]. Further exposure to the ele-
vated temperature results in increased vertical spreading
of the sub-layers, leading ultimately to the failure of the Pt
diffusion barrier and the penetration of Au into the semi-
conductor.
Therefore, shallow contacts with stable morphology are
required. Refractory metals such as W, Mo, and Ir, are
good candidates for a new generation of contacts. These
metals have the advantage of lower diffusivity through
the semiconductor at high temperature and offer a higher
resistance to chemical reaction with the semiconductor
when exposed to thermal processing. In addition, they
are extremely resistant to corrosion and heat due to their

Figure 6: EDXS line profile showing elemental distribution across the Pt-
based metal stack and metal-semiconductor interface after aging at 240
°C for 7 hours.
high melting point. The major disadvantage of the refrac-
tory metals is their inability to penetrate the native oxide,
as opposed to noble metals. Hence, before the deposition,
the semiconductor surface has to be pristine.
In this report we choose iridium since it possesses a rel-
atively high conductivity (2.1×107 S/m), and a similar
workfunction (5.2 eV) as noble metals. A novel base met-
alization scheme has been developed using iridium as a
contact layer, with the objective of establishing a shallow
and low resistivity contact. The Pt diffusion barrier was re-
placed by Pd, which offered a lower metal sheet resistance
and resistivity values after annealing, as our previous ex-
periment demonstrated.
Multilayer ohmic contacts Ir/Ti/Pd/Au of
10/10/15/200 nm were evaporated with low depo-
sition rate of 2 Å/s to avoid source spitting and to
minimize surface roughness. Prior to metal deposition,
the surface was treated with sulfuric acid to have a
consistent and effective oxide removal.
Figure 7: Cross-sectional HAADF STEM micrographs showing Ir-based
metal stack on InGaAs after annealing at 240°C for 7 hours, b) a higher
magnification image of Ir/InGaAs interface. Metal diffusion into the
semiconductor material was prevented by the Ir contact layer.
After annealing for 7 hours, a metallurgical stability
6
analysis using TEM was performed on the Ir sample.
As observed in figure 7, the contact shows a chemically
abrupt interface. Electron diffraction experiment did not
reveal any presence of intermixing compounds showing
only textured Ir layers (Figure 8). The out-diffusion ap-
pears to be suppressed effectively. No voids in the upper
layers were observed, even when annealed for 7 hours,
demonstrating excellent microstructual stability.
Figure 8: Electron diffraction pattern obtained at the Ir/InGaAs interface
after 7 hours of annealing at 240 °C. The pattern shows strong InGaAs
reflections as well as (111) reflections of Ir suggesting the following tex-
ture: (111) Ir || (001) InGaAs. No Ir-In-Ga-As alloying was detected.
Figure 9 shows the resistivity as a function of annealing
time for the Ir-based and the Pt-based metal stack. As-
deposited, the Ir contact yielded ρc values comparable to
the Pt-based contact, of around 35 Ω.µm2 .
3 5 0
A n n e a lin g c o n d itio n s : 2 4 0 ° C , N 2
3 0 0
P t/T i/P t/A u 1 0 /1 5 /1 5 /2 0 0 n m
Ir /T i/P d /A u 1 0 /1 5 /1 5 /2 0 0 n m
2 5 0
2
R e s i s t i v i t y / Ω.µm
2 0 0
1 5 0
1 0 0
5 0
0 1 3 7
A n n e a lin g tim e / h
Figure 9: Comparison between the measured contact resistivity of the
Pt-based and Ir-based metalization scheme as a function of annealing
time. results are averaged over many samples processed using the same
conditions.
As expected with the conventional metal stack, strong
degradation occurs due to the reason mentioned above, Conclusion
the Ir stack in contrast exhibited small deviations from the
as-deposited values, thus supporting the expectation that In this report, the influence of surface treatment and
field emission is the prevailing current transport mecha- stability of multilayer ohmic contacts to p-type InGaAs
nism due to the limited reaction between the semiconduc- were examined. The H2 SO4 and (NH4 )2 S pretreatment
tor and the refractory metal. offered an acceptable consumption of InGaAs and an ef-
fective removal of native oxides. It was also found that Pt-
Time As dep. 1h 3h 7h based metal exhibit low long-term reliability under ther-
mal stress, as they suffer from high reactivity along with
Pt Ir Pt Ir Pt Ir Pt Ir
a deep penetration into the semiconductor when exposed
ρC [Ω.µm ] 2
40.1 34.4 108 41.9 210 44.5 249 48 to N2 atmosphere at 240°C over several hours. The an-
RSH [Ω/] 710 769 650 788 564 787 536 785 nealing process results in the formation of Pt-In-Ga-As in-
RC [Ω.mm] 0.18 0.16 0.26 0.18 0.34 0.18 0.36 0.19 terlayers and simultaneously depletes the Pt film leading
Lt [µm] 0.24 0.21 0.4 0.23 0.6 0.23 0.68 0.24 to an observed void formation. This results in a resistiv-
ity increase from 40 Ω.µm2 to 240 Ω.µm2 , as the current
transport mechanism is severely deteriorated. A novel Ir-
Table 3: Summarized measurement results of the contact resistivity with based metal stack was successfully demonstrated. TEM
annealing temperature for the Pt and Ir contacts. All samples were
treated with the H2 SO4 and processed under the same conditions.
analysis showed that iridium can effectively inhibit inter-
mixing due to its strong resistance to reactions with met-
On the other hand, The resistivity of the Iridium-based als or semiconductors. The new contact maintained its
contact remained practically unchanged throughout the integrity during thermal stress, yielding a stable metallur-
annealing process. With variation less then 20% for ρC gical interface and low resistivity values.
after 7h of annealing at 240°C, the Ir clearly presents su-
perior thermal stability compared to the conventional Pt
Acknowledgment
contact. The results are summarized in table 3. The ab-
sence of reactions at the Ir/InGaAs interface is further con-
The authors would like to thank the FBH process tech-
firmed by the stable electrical measurement of the sheet
nology department, especially A. Dounia and J. Cwynar
resistance.
for chip measurement, N. Thiele and A. Runge for the
S tre s s c o n d itio n s : 9 h , N 2 4 0 ° C
3 0 metal deposition, B. Janke, M. Matalla for photomask cre-
2
1 0 -2
P t-b a s e d c o n ta c t
ation and U. Zeimer for the constructive discussions. This
Ir-b a s e d c o n ta c t 2 5
work has been partially supported by the Horizon 2020
research and innovation program under grant agreement
-3 IC 2 0
1 0
no. 762119 (ULTRAWAVE) and the Leibniz Gemeinschaft
C u r r e n t g a in

under the SAW project ”InP THz transistors”.

C u rre n t / A

1 5
-4
1 0

-5
1 0
0 .4 0 .5
Figure 10: Comparison of the Gummel plots of two large area devices
(LAD) transistors having a different base metalization after aging. The Ir
contact exhibited a higher current gain and lower base current.
The observed deterioration in the transport mechanism
can be directly reflected in the DC characteristics of the
large area transistors, as shown in figure 10. The parasitic
base current is significantly higher with a Pt contact than
for the Ir-based device. The results indicate degradation
in the crystal quality beneath the Pt contact, generation of
defects at the interface is responsible for increased recom-
bination and trap states [30, 31]. As a result, a higher base
current and base ideality factor are observed for the con-
ventional contact, along with a drop in the current gain.
β 1 0
IB References
5
[1] M. Urteaga et al., InP HBT Technologies for THz Integrated Circuits,
Proceedings of the IEEE Vol. 105, No. 6, June 2017
0 [2] J. C. Rode et al, Indium Phosphide Heterobipolar Transistor Technol-
0 .6 0 .7 0 .8 0 .9
ogy Beyond 1-THz Bandwidth, IEEE Transactions On Electron De-
V B E / V vices, Vol. 62, No. 9, September 2015
[3] E. F. Chor et al., Metallurgical Stability of Ohmic Contacts in Base
InP/InGaAs/InP HBT’s, IEEE Electron Device Letters, Vol 17, No. 2
February 1996.
[4] J. Rode et al., An InGaAs/InP DHBT With Simultaneous fτ /fmax
404/901 GHz and 4.3 V Breakdown Voltage, Journal of Eletron De-
vice Society., 2014
[5] N.G. Weimann et al., SciFab – a wafer-level heterointegrated InP
DHBT/SiGe BiCMOS foundry process for mm-wave applications,
Phys. Status Solidi A, 1–8 (2016)
[6] H. Masuda et al., Device Technology of InP/InGaAs HBTs for 40-Gb/s
Optical Transmission Application, GaAs IC Symposium. IEEE Gal-
lium Arsenide Integrated Circuit Symposium. 19th Annual Techni-
cal Digest 1997.
[7] E. F. Chor et al. Electrical characterization, metallurgical investiga-
tion, and thermal stability studies of Pd, Ti, Au-based ohmic contacts,
Journal of Applied physics 2000, Volume 87, Number 5.
[8] J. C. Lin, Characterization of low-resistance ohmic contacts to n- and
p-type InGaAs, Journal of Applied Physics 114, 044504 (2013)

7
 [9] J.S Yu et al., Pt/Ti/Pt/Au and Pd/Ti/Pt/Au ohmic contacts to p-
InGaAs, Compound Semiconductors 1997, Proceedings of the IEEE
Twenty-Fourth International Symposium on Compound Semicon-
ductors.
[10] J. A.Robinson et al., Solid-State Phase Formation between Pd Thin
Films and GaSb, Journal of Electronic Materials , Vol. 35, No. 1,
2006
[11] R. Dormaier Thermal stability of Pd/Pt/Au Ohmic contacts to In-
AlSb/InAs heterostructures for HEMT, Journal of Applied Physics
105, 044505 (2009);
[12] Baraskar, Development of Ultra-Low Resistance Ohmic Contacts for
InGaAs/InP HBTs, UCSB 2011 Doctoral Dissertation.
[13] E. Lobisser et al., Ex-situ Tungsten Refractory Ohmic Contacts to p-
InGaAs, 38th International Symposium on Compound Semiconduc-
tors, Berlin 2011
[14] H.H. Berger, Model for contacts to planar devices,Solid States Elec-
tronics, Vol. 15 pp. 145-158, 1972
[15] F.L. Lie et al., In0.53 Ga0.47 As (100) native oxide removal by Liquid
and Gas phase HF/H2O chemistry, Microelectronic Engineering 87
: 1656-1660 November 2010
[16] J. Bardeen, Surface states and rectification at a metal-semiconductor
contact, Physical review Volume 71 Number 10, 1947
[17] G. Strateev et al., A controllable mechanism of forming extremely
low-resistance non-alloyed ohmic contacts to III-V semiconductors, J.
App. Phys. 74 (12) 1993
[18] V. L. Rideout, A review of the theory and technology for ohmic con-
tacts to group III-V compound semiconductor, Solid state electronic
Vol 18 pp 541-550. 1975
[19] T.P. Chen et al, Surface treatment effect on temperature dependent
properties of InGaP/GaAs heterobipolar transistors, Journal of Ap-
plied Physics 101, 034501 (2007).
[20] R. Driad et al, Passivation of InGaAs surfaces and InGaAs/InP het-
erojunction bipolar transistors by sulfur treatment, Appl. Phys. Lett.
73, 665 (1998)
[21] H. Wang et al, Design Of Shallow And Thermally Stable Contacts On
Antimonide-Based Semiconductors, Doctoral dissertation, The Penn-
sylvania State University, 2004
[22] X.A. Cao et al., Effects of interfacial oxides on Schottky barrier con-
tacts to n- and p-type GaN, Applied Physics Letter, Volume 75 Num-
ber 26 (1999)
[23] M. Diale et al., Effects ofchemical treatment on barrier height and
ideality factors of Au/GaN Schottky diodes, Physica B: Condensed
Matter Volume 404, Issue 22, 1 December 2009, Pages 4415-4418
[24] G. Stareev et al., A Reliable Fabrication Technique for Very Low Resis-
tance Ohmic Contacts to p-InGaAs Using Low Energy Ar+ Ion Beam
Sputtering, Proceedings 1991 of Third International Conference In-
dium Phosphide and Related Materials.
[25] M. Alexandrova et al., Development and Optimization of High-Speed
InP/GaAsSb Double Heterojunction Bipolar Transistors, Dissertation.
ETH Zürich No. 23197, 2015
[26] T. Sands et al., Ni, Pd, and Pt on GaAs: A comparative study of
interfacial structures, compositions, and reacted film morphologies,
Journal of Material Research, Volume 2, Issue 2 April 1987 , pp.
262-275
[27] J.A. Robinson et al., Pd/Pt/Au ohmic contact for AlSb/InAs0.7Sb0.3
heterostructures, Solid-State Electronics Volume 50, Issue 3, March
2006, Pages 429-432
[28] D. G. Ivey et al, Microstructural analysis of Au/Pt/Ti contacts top-
type InGaAs, Journal Of Materials Science: Materials In Electronics
6 (1995) 219-227
[29] A. Katz et al, Pt/Ti ohmic contacts to ultrahigh carbon-doped p-
GaAs formed by rapid thermal processing, Appl. Phys. Lett. 56, 1028
(1998)
[30] Yoshino K. Fukai and Kenji Kurishima, Reliability Study of InP-
Based HBTs Operating at High Current Density, Material and Reli-
ability Handbook for Semiconductor Optical and Electron Devices,
Springer Science and Business Media New York 2013
[31] K.T. Feng et al, Investigation of reliability for C-doped
InP/InGaAs/InP HBTs under high current density operation,
Proceedings of GaAs Reliability Workshop, 2003, pp. 117–120.