Microprocessors

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 INTRODUCTION

• A Microprocessor is a pre-programmed and multipurpose logic

device that reads binary instructions from a storage device called
memory, accepts binary data as input and processes the data
according to those instructions, and provides results as output.

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Typical programmable machine has
three components :

1. MICROPROCESSOR

2. MEMORY

3. I/O DEVICES

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 Typical Programmable machine

Memory

Micro processor

I/O

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 Hardware

• The physical components of the system are called hardware.

• A set of instructions written for the microprocessor to perform
a task is called a Assembly Language.

Microprocessor applications are used in

* Programmable systems

* Embedded systems

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 Microprocessor as a CPU

• Microprocessor is a primary component of a computer CPU

consists of arithmetic logic unit(ALU) and control unit and
various registers to store data, instruction decoders, Counters
and control lines .

• The ALU performs arithmetic and logical operations.

• The CPU reads instructions from the memory and

perform the task specified.

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• CPU communicates with I/O devices either to accept or to
send data.
• Timing of the communication process is controlled by
CONTROL UNIT.

Computer with Microprocessor as CPU

CPU (Microprocessor)

A ALU
L
U

input Control unit output

Memory

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 Organization of a Microprocessor-Based system

• These type of systems Basically have five components :

1) Microprocessor , 2) Input, 3) Output,
4) Memory (read/write and read only memory)
5) System Bus

Microprocessor input output

ALU Register
System Bus
Array

Control ROM RAM

Memory

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 Microprocessor

• The Microprocessor is capable of performing various Computing

functions and making decisions to change the sequence of
program execution.

• This can be divided into three segments :

Arithmetic / Logic unit

Register Array
Control unit

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O Arithmetic/Logic Unit: In this various computing Functions
are performed on data such as arithmetic operations
(addition, subtraction) and logical operation (AND, ORXOR).
Result are store either in register or in memory.

z Register Array: These registers are primarily used to store

data temporarily during the execution of problem. some of the
registers are accessible to user.

z Control Unit: The control unit provides necessary timing

and controlling signals. It controls the flow of data between the
microprocessor, memory and peripherals.

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• Input : The input section transfers data and instructions in binary
from the outside world to the microprocessor. Some of the input
devices are keyboard, analog to digital converter.

• Output : The output section transfers data from the

microprocessor. Some of the output devices are such as LED,
CRT, Printer, Magnetic tape.

• Memory: Memory stores binary information as instructions

and data. The memory block has two sections:
Read Only Memory (ROM), Read/Write Memory (RAM)
ROM is used to store programs that do not need alteration.

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• System Bus: It is a group of wires to carry bits.
Any Communication Path is called a BUS. The components are
organized around a common BUS. The System Bus is a
communication path between the Micro processor and
peripherals.

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 8085 Microprocessor Architecture
• This is an 8-bit General Purpose Microprocessor.

• It is capable of addressing 64k of memory, 16 address lines

• It can operate at 3-MHz and 5-MHz .

• The signals of 8085 are classified into :

Data Bus( AD7-AD0 ) and Address Bus( A15-A8 and AD7-AD0 )
Control and Status Signals( ALE,RD,WR,IO/M,S1 and S0 )
Power Supply and Frequency Signals ( VCC,VSS,X1,X2,CLK(out) )
Externally Initiated Signals
( INTR, INTA, RESET, HOLD, HLDA, READY, TRAP )
Serial I/O ports ( SID, SOD )

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 INTA RST 6.5 TRAP
SID SOD
INTR RST 5.5 RST 7.5
Functional Block
Interrupt Control Serial I/O Control
Diagram :

8-Bit Internal Data Bus

Accumulator Temp. Reg.. Instruction

(8) (8) Register (8) Multiplexer
W (8) Z (8)
Temp. Reg.. Temp. Reg..
B (8) C (8)
Flag (5) Reg.. Reg..
Flip-Flops D (8) E (8)

Reg.. Select
Instruction Reg.. Reg.. Register
Decoder H (8) L (8) Array
Arithmetic Reg.. Reg..
and
Logic Stack Pointer (16)
Unit Machine
(ALU) Cycle (16)
(8) Program Counter
Encoding
Incrementer/Decrementer
Power Supply +5V Address Latch (16)
GND

Training and Control

X1 CLK
Reset
X2 GEN Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK OUT HLDA RESET OUT

RD WR ALE S0 S1 10/M A15-A8 AD7-AD0
READEY HOLD RESET IN Address Bus Address/Data Bus

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 ALU
• The arithmetic/logic unit performs the computing functions.

• It includes the accumulator, the temporary registers.

• It consists of the Arithmetic and logic circuits, and five flags.

• The temporary registers are used to hold data during an

Arithmetic/logic operations.

• The results are stored in accumulator.

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• The five flags are :
S- Sign flag
Z- Zero flag
AC - Auxiliary carry flag
P- Parity flag
CY - Carry flag

• Bit positions of flags in flag register

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

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Timing and Control Unit: This unit synchronizes all the
microprocessor operations with the clock and generates the control
signals. The RD and WR signals are sync pulses indicating the
availability of data on the Data Bus.

Instruction Register and Decoder : Instructions are loaded into

instruction Register which are fetched from memory. The decoder
decodes the instruction and establishes the sequence of events to
flow.

Register Array: The additional Registers are called temporary

registers W and Z are included in the register array. These are 8-bit
registers, and these are not available to the programmer.

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 Interfacing 8255 (PPI)
Programmable Peripheral Interface

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Requirement of a programmable interfacing device:
• Many a times, I/O devices may not be always ready for data
transfers.
• For example, when the microprocessor sends data bytes to a
printer, the microprocessor can execute the instructions to
transfer a byte in microseconds; on the other hand, the printer can
take 10 to 25 ms to print a character. After transferring a character
to the printer, the processor should wait until the printer is ready
for the next character;otherwise data will be lost.
• This can be achieved by exchanging some sort of handshake
signals between the microprocessor and the printer , so we need
an additional circuitry for this purpose.
• And 8255 is designed to fulfill this requirement and it also
provides provision for bi-directional data transfers. Also this
device is highly programmable.
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• The 8255 is a widely used programmable parallel I/O device.

• It can be programmed to transfer data under various Conditions,

from simple I/O to interrupt I/O.

• The 8255 has 24 I/O pins that can be grouped in two 8-bit
Parallel ports (A&B) and remaining 8-bits act as port C.

• Port C can be used as individual bits or be grouped in two 4-bit

ports (C upper and C lower).

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 Modes of 8255

• The functions of 8255 is classified According to two modes:

* Bit Set/Reset(BSR) mode
* I/O mode

• BSR mode is used to Set or Reset the bits in the port C.

• The I/O mode is divided into three modes:

* Mode 0
* Mode 1
* Mode 2

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Mode 0 : In mode 0 all ports function as simple I/O Ports.

Mode 1 : Mode 1 is a handshake mode whereby port A and /or B

use bits from port C as handshake signals.

Mode 2 : In mode 2 port A can be set up for bi-directional Data

transfer using handshake signals from port C, and Port B
can be set up either in mode 0 or mode 1.

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Functional block diagram of 8255

Power +5V Group

GND A I/O
Supplies
Group Port PA7-PA0
A A
Control (8)

Group
Bidirectional Data Bus A I/O
Port C PC7-PC4
Data Upper
D7-D0 Bus (4)
Buffer
8-Bit
Internal Group
Data B
Bus Port C I/O
Lower PC3-PC0
(4)

RD
Read Group Group
WR Write B I/O
B
A1 Control Control PB7-PB0
Port
A0 Logic B
RESET (8)

CS

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RD (Read) : This signal enables the read operation.When signal
is low, the processor reads data from a selected I/O port or 8255.

WR (Write) : This signal enables the write operation. When signal

goes low, the processor writes into a selected I/O port or the
control register.

RESET (Reset) : This is an active high signal; it clears the

Control register and sets all ports in the input mode.

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CS, A0, and A1: These are device select signals. CS is connected to
decoded address, and A0 and A1 are connected to processor
address lines A0 and A1.

CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X 8255A is not selected

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 Control Word

There is a register called control register which holds the

control word, to specify I/O function for each port.

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 Control Word
D7 D6 D5 D4 D3 D2 D1 D0 Group B

} Port C ( Lower — PC3 _ PC 0 )

1 = Input
0 = Output
Port B
1 = Input
0 = Output
Mode Selection
0 = Mode 0
1 = Mode 1
Group A
Port C (Upper – PC7 – PC 4 )
1 = Input
0 = Output
Port A
1 = Input
0 = Output
Mode Selection
00 = Mode 0
01 = Mode 1
IX = Mode 2

1 = I/O Mode
0 = BSR Mode

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 Application

Design an interfacing circuit to read data from an A/D converter,

using the 8255 in the memory-mapped I/O.
• Set up port A to read data
• Set up bit PC0 to start conversion and bit PC7 to read the
ready status of the converter.

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Analysis of the interfacing circuit:

Assume that port A is addressed by processor address 8000H,

port B by 8001H, port C by 8002H and control register by 8003H.
And MEMR and MEMW are connected to RD and WR signals of
the 8255. Processor address line A15 is inverted and connected to
CS of 8255. Why ? Address lines A1 and A0 are connected to A1
and A0 of 8255.

Processor Data bus is connected to data bus of the 8255. And port
A of 8255 is connected to the data out of A/D converter. PC0 is
connected to B/C of the A/D converter. PC7 is connected to
DR of the A/D converter.

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 +5V
- 15 V +5V
26 7
VCC GND 12 10

NC 1 18 NC
27
D7 D7 37
PA7 2 D7 13
38 Analog Impute
Data Bus PA6 3
39
PA5 4
34 40 16
D0 D0 PA4 5 AD570 Digital Common (+ 5 V Common
1 15
PA3 6 Shorted to Common
2
PA2 7 For Unipolar ( 0 to 10 V)
3
PA1 8 D0
4 14
PA0 9
DR B/C

6 17 11 Analog
A15 CS PC7 Common
A1 8 (- 15 V Common)
A1
A0 9 PC0
A0 14 START Plus
5
MEMR RD At least
36
MEMW WR Port B Not Used 2µs
RESET
35

RESET
OUT (8085)

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• The control word to be programmed in the control register should
satisfy these requirements:

* Port A as an input port.

* Port CU: As an input port to read the status at PC7.
* Port CL: As an output port because bit PC0 is used to start
A/D conversion.
• So the control word to satisfy these requirements is 98H. Why?
• To generate a start pulse on PC0 to start A/D conversion, the
control register need to be programmed in BSR mode and PC0
has to be set and then reset after a programmed delay. To set
PC0, the BSR control word is 01H (why ?) and to reset PC0,
the BSR control word is 00H (why?)

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The sequence of operations the microprocessor need to perform
to get the A/D converted output shall be:

* Programming Port A and port CU as an input ports and

port CL as an output port.
* Writing BSR control word 01H to set PC0 bit to start
A/D conversion.
* Wait for appropriate time to reset PC0, this time
depends on the requirement of start pulse HIGH time
for the A/D converter.
* Writing BSR control word 00H to reset PC0 bit.
* Keep on reading PC7 to notice that the conversion is
over.
* Read port A to get the converted value.

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 Interfacing 8254
Programmable Interval Timer

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• The 8254 programmable interval timer/counter is functionally
similar to the software designed counters and timers.

• It generates accurate time delays and can be used for applications

such as a real time clock, an event counter.

• The 8254 includes three identical 16-bit counter that can operate
independently in any one of the six modes.

• To operate a counter, a 16-bit count is loaded in its register and,

on command, begins to decrement the count until it reaches 0 and
it generate a pulse that can be used to interrupt the processor.

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• The counter can count either in binary or BCD.
• It can operate from 0 to 8MHz and 10MHz.
• Control Logic : The control logic section has five signals

RD (read)
WR (write)
CS (chip select)
Address Lines (A0,A1)

• Peripheral I/O mode : In this mode the RD and WR signals are

Connected to IOR and IOW, respectively.
• Memory-mapped I/O mode: In this mode the RD and WR
signals are connected to MEMR (Memory Read) and MEMW.

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• Address lines A0 and A1 of the processor are connected to
lines A0 and A1 of the 8254.
• CS is tied to decoded address

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Functional block diagram
CLK 0
Date
Counter
D7-DO 8 Bus GATE 0
Buffer = 0
OUT 0

RD CLK 1
Read/
WR Counter
Write = 1 GATE 1
AO Logic
A1 OUT 1

CS

CLK 2
Control
Counter GATE 2
Word
= 2
Register
OUT 2

Internal Bus

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Selecting of counters

A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Register

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 Modes of 8254

Mode 0 : Interrupt on terminal count.

Mode 1 : Hardware-Retriggerable one-shot

Mode 2 : Rate Generator

Mode 3 : Square-Wave Generator

Mode 4 : Software-Triggered Strobe

Mode 5 : Hardware-Triggered Strobe

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Control word
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

SC-Select Counter: M-Mode:

SC1 SC 0 M2 M1 M0
0 0 Select Counter 0 0 0 0 Mode 0
0 0 1 Mode 1
0 1 Select Counter 1
X 1 0 Mode 2
1 0 Select Counter
• 1 Read-Back Command X 1 1 Mode 3
(See Read Operations) 1 0 0 Mode 4
RW-Read/Write: 1 0 1
RW1 RW0
Mode 5

0 0 Counter Latch Command BCD:

0 1 Read/Write least significant byte only. 0 Binary Counter 16-bits

1 0 Read/Write most significant byte only. 1 Binary Coded Decimal Counter
1 1 Read/Write LSB first, then MSB

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