74VHC273 Octal D-Type Flip-Flop

April 1994
Revised May 2003

74VHC273
Octal D-Type Flip-Flop
General Description Features
The VHC273 is an advanced high speed CMOS Octal ■ High Speed: fMAX = 165 MHz (typ) at VCC = 5V
D-type flip-flop fabricated with silicon gate CMOS technol- ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low ■ High noise immunity: VNIH = VNIL = 28% VCC (min)
power dissipation. ■ Power down protection is provided on all inputs
The register has a common buffered Clock (CP) which is ■ Low noise: VOLP = 0.9V (max)
fully edge-triggered. The state of each D input, one setup
■ Pin and function compatible with 74HC273
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master ■ Leadless DQFN Package
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.

Ordering Code:
Package
Order Number Package Description
Number
74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273BQ MLP020B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241,
(Preliminary) (Preliminary) 2.5 x 4.5mm
74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

© 2003 Fairchild Semiconductor Corporation DS011670 www.fairchildsemi.com

74VHC273
Logic Symbols Connection Diagrams
Pin Assignments for PDIP, SOIC, SOP, and TSSOP

IEEE/IEC

Pad Assignments for DQFN

Pin Descriptions
Pin Names Description
D0–D7 Data Inputs
MR Master Reset
CP Clock Pulse Input
Q0–Q7 Data Outputs

Function Table
Inputs Outputs
Operating Mode
MR CP Dn Qn

Reset (Clear) L X X L
Load '1' H  H H
Load '0' H  L L
H = HIGH Voltage Level
L = LOW Voltage Level


X = Immaterial
(Top Through View)
= LOW-to-HIGH Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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 74VHC273
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V Conditions (Note 2)
DC Input Voltage (VIN) −0.5V to +7.0V Supply Voltage (VCC) 2.0V to +5.5V
DC Output Voltage (VOUT) −0.5V to VCC + 0.5V Input Voltage (VIN) 0V to +5.5V
Input Diode Current (IIK) −20 mA Output Voltage (VOUT) 0V to VCC
Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) −40°C to +85°C
DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf)
DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V
Storage Temperature (TSTG) −65°C to +150°C VCC = 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V
Lead Temperature (TL) Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
(Soldering, 10 seconds) 260°C tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
VCC TA = 25°C TA = −40°C to +85°C
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
VIH HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 VCC 0.7 VCC
VIL LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 VCC 0.3 VCC
VOH HIGH Level Output 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA
Voltage 3.0 2.9 3.0 2.9 V or VIL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 IOH = −4 mA
V
4.5 3.94 3.80 IOH = −8 mA
VOL LOW Level Output 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA
Voltage 3.0 0.0 0.1 0.1 V or VIL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL = 4 mA
V
4.5 0.36 0.44 IOL = 8 mA
IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND
ICC Quiescent Supply Current 5.5 4.0 40.0 µA VIN = VCC or GND

Noise Characteristics
VCC TA = 25°C
Symbol Parameter Units Conditions
(V) Typ Limits
VOLP Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 V CL = 50 pF
(Note 3)
VOLV Quiet Output Minimum Dynamic VOL 5.0 −0.6 −0.9 V CL = 50 pF
(Note 3)
VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF
(Note 3)
VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF
(Note 3)
Note 3: Parameter guaranteed by design.

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74VHC273
AC Electrical Characteristics
VCC TA = 25°C TA = −40°C to +85°C
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
fMAX Maximum Clock 3.3 ± 0.3 75 120 65 CL = 15 pF
MHz
Frequency 50 75 45 CL = 50 pF
5.0 ± 0.5 120 165 100 CL = 15 pF
MHz
80 110 70 CL = 50 pF
tPLH Propagation Delay 3.3 ± 0.3 8.7 13.6 1.0 16.0 CL = 15 pF
ns
tPHL Time (CK - Q) 11.2 17.1 1.0 19.5 CL = 50 pF
5.0 ± 0.5 5.8 9.0 1.0 10.5 CL = 15 pF
ns
7.3 11.0 1.0 12.5 CL = 50 pF
tPHL Propagation Delay 3.3 ± 0.3 8.9 13.6 1.0 16.0 CL = 15 pF
ns
Time (MR - Q) 11.4 17.1 1.0 19.5 CL = 50 pF
5.0 ± 0.5 5.2 8.5 1.0 10.0 CL = 15 pF
ns
6.7 10.5 1.0 12.0 CL = 50 pF
tOSLH Output to 3.3 ± 0.3 1.5 1.5 (Note 4) CL = 50 pF
ns
tOSHL Output Skew 5.0 ± 0.5 1.0 1.0 CL = 50 pF
CIN Input Capacitance 4.0 10.0 10.0 pF VCC = Open
CPD Power Dissipation 31 (Note 5)
pF
Capacitance
Note 4: Parameter guaranteed by design tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin|.
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pieces of the Flip-Flop operates can
be calculated by the equation: CPD (total) = 22 + 9n.

AC Operating Requirements
VCC TA = 25°C TA = −40°C to +85°C
Symbol Parameter (V) Units
(Note 6) Typ Guaranteed Minimum

tW(L) Minimum Pulse Width (CK) 3.3 5.5 6.5

ns
tW(H) 5.0 5.0 5.0

tW(L) Minimum Pulse Width (MR) 3.3 5.0 6.0

ns
5.0 5.0 5.0
tS Minimum Setup Time 3.3 5.5 6.5
ns
5.0 4.5 4.5
tH Minimum Hold Time 3.3 1.0 1.0
ns
5.0 1.0 1.0

tREC Minimum Removal Time (MR) 3.3 2.5 2.5

ns
5.0 2.0 2.0
Note 6: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V

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 74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B

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74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D

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 74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package Number MLP020B
(Preliminary)

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74VHC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20

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 74VHC273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

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