TMS370Cx0x 8-Bit Microcontroller: FZ and FN Packages (Top View)

TMS370Cx0x
8-BIT MICROCONTROLLER
SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997
D CMOS/ EEPROM/ EPROM Technologies on FZ AND FN PACKAGES

a Single Device ( TOP VIEW )
RESET
– Mask-ROM Devices for High-Volume
V CC
Production
D7
D6
D3
D4
A7
– One-Time-Programmable (OTP) EPROM
4 3 2 1 28 27 26
Devices for Low Volume Production 5
XTAL2 / CLKIN 25 SCITXD
– Reprogrammable EPROM Devices for XTAL1 6 24 SCICLK
Prototyping Purposes A6 7 23 SCIRXD
D Internal System Memory Configurations A5 8
9
22 T1IC / CR
A4 21 T1PWM
– On-Chip Program Memory Versions
A3 10 20 T1EVT
– ROM: 8K Bytes A2 11 19 MC
– EPROM: 8K Bytes 12 13 14 15 16 1718
– Data EEPROM: 256 Bytes
INT1
INT2
INT3
A1
A0
VSS
D5
– Static RAM: 256 Bytes Usable as
Registers
D Flexible Operating Features D Serial Communications Interface 1 (SCI1)
– Low-Power Modes: STANDBY and HALT – Asynchronous Mode: 156K bps
– Commercial, Industrial, and Automotive Maximum at 5 MHz SYSCLK
Temperature Ranges – Isosynchronous Mode: 25M bps
– Clock Options Maximum at 5 MHz SYSCLK
– Divide-by-4 (0.5 to 5 MHz SYSCLK) – Full Duplex, Double-Buffered Receiver
– Divide-by-1 (2 to 5 MHz SYSCLK) (RX) and Transmitter (TX)
Phase-Locked Loop (PLL) – Two Multiprocessor Communication
– Supply Voltage (VCC) 5 V ±10% Formats
D 16-Bit General-Purpose Timer D TMS370 Series Compatibility
– Software Configurable as – Register-to-Register Architecture
a 16-Bit Event Counter, or – 256 General-Purpose Registers
a 16-Bit Pulse Accumulator, or – 14 Powerful Addressing Modes
a 16-Bit Input Capture Functions, or – Instructions Upwardly Compatible With
Two Compare Registers, or a All TMS370 Devices
Self-Contained Pulse-Width-Modulation D CMOS/ TTL Compatible I / O Pins / Packages
(PWM) Function – All Peripheral Function Pins Software
– Software Programmable Input Polarity Configurable for Digital I / O
– Eight-Bit Prescaler, Providing a 24-Bit – 21 Bidirectional Pins, 1 Input Pin
Real-Time Timer – 28-Pin Plastic and Ceramic Leaded Chip
D On-Chip 24-Bit Watchdog Timer Carrier Packages
– EPROM / OTP Devices: Standard D Workstation / Personal Computed-Based
Watchdog Development System
– Mask-ROM Devices: Hard Watchdog, – C Compiler and C Source Debugger
Simple Counter, or Standard Watchdog – Real-time In-Circuit Emulation
D Flexible Interrupt Handling – Extensive Breakpoint / Trace Capability
– Two Software-Programmable Interrupt – Multi-Window User Interface
Levels – Microcontroller Programmer
– Global- and Individual-Interrupt Masking
– Programmable Rising or Falling Edge
Detect
– Individual Interrupt Vectors
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1

TMS370Cx0x
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Pin Descriptions
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28 PINS
LCC
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I / O† DESCRIPTION
NAME NO.
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A0
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A1 ÁÁÁ
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14
13
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A2 11
A3 10
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I/O Port A is a general-purpose bidirectional I / O port.
A4 9
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A5 8
A6 7
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A7 3
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D3 28
D4 26
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D5 15 I/O Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK.
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D6 1
D7 2
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INT1
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INT2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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16 I
17 I/O
External interrupt (non-maskable or maskable) / general-purpose input pin
External maskable interrupt input / general-purpose bidirectional pin
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INT3 18 I/O External maskable interrupt input / general-purpose bidirectional pin
T1IC / CR 22 Timer1 input capture / counter reset input pin / general-purpose bidirectional pin
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T1PWM
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T1EVT
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21 I/O
20
Timer1 PWM output pin / general-purpose bidirectional pin
Timer1 external event input pin / general-purpose bidirectional pin
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SCITXD 25 SCI transmit data output pin, general-purpose bidirectional pin‡
SCIRXD 23 I/O SCI receive data input pin / general-purpose bidirectional pin
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SCICLK 24 SCI bidirectional serial clock pin / general-purpose bidirectional pin
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System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,
RESET 27 I/O
RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.
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MC
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19 I Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP
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XTAL1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
XTAL2 / CLKIN
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5 I
6 O
Internal oscillator crystal input / External clock source input
Internal oscillator output for crystal
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VCC 4 Positive supply voltage
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VSS 12 Ground reference
† I = input, O = output
‡ The three-pin SCI configuration is referred to as SCI1.
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x
functional block diagram

XTAL2/
INT1 INT2 INT3 XTAL1 CLKIN MC RESET
Clock Options:
System
Interrupts Divide-By-4 Or
Control
Divide-By-1 (PLL)
Serial SCIRXD
Communications SCITXD
RAM Interface 1 SCICLK
CPU
256 Bytes
Program Memory
ROM: 8K Bytes Data EEPROM
EPROM: 8K Bytes 0 or 256 Bytes
T1IC/CR
Timer 1
T1EVT
T1PWM
Watchdog
VCC
Port A Port D VSS
8 5
description
The TMS370C002, TMS370C302, TMS370C702, and SE370C702 devices are members of the TMS370 family
of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx0x refers to these devices.
The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral
function modules and various on-chip memory configurations.
The TMS370Cx0x family of devices is implemented using high-performance silicon-gate CMOS EPROM and
EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of
CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx0x devices attractive in system designs for automotive electronics, industrial motors, computer
peripheral controls, telecommunications, and consumer applications.
All TMS370Cx0x devices contain the following on-chip peripheral modules:
D Serial communications interface 1 (SCI1)
D One 16-bit general-purpose timer with an 8-bit prescaler
D One 24-bit general-purpose watchdog timer
Table 1 provides a memory configuration overview of the TMS370Cx0x devices.

TMS370Cx0x
description (continued)
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DEVICE
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PROGRAM MEMORY
(BYTES)
DATA MEMORY
(BYTES) 28-PIN PACKAGE
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ROM EPROM RAM EEPROM
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TMS370C002A 8K — 256 256 FN – PLCC
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TMS370C302A 8K — 256 — FN – PLCC
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TMS370C702 — 8K 256 256 FN – PLCC
SE370C702† — 8K 256 256 FZ – CLCC
† System evaluators and development are for use only in prototype environment and their reliability has not been characterized.
The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the
configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 2. Suffix Letter Configuration

DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE
EPROM without A Standard Divide-by-4 (standard oscillator) Enabled
Standard
Di id b 4 or
Divide-by-4
ROM A Hard Enabled or disabled
Divide-by-1 (PLL)
Simple
The 8K bytes of mask-programmable ROM in the associated TMS370Cx0x devices are replaced in the
TMS370C702 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with
the exception of no data EEPROM on the TMS370C302 devices. The one-time programmable (OTP)
(TMS370C702) device and reprogrammable device (SE370C702) are available.
TMS370C702 OTP devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx0x family or for low-volume production runs
when the mask charge or cycle time for low-cost mask ROM devices is not practical.
The SE370C702 has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development-prototyping phase of design. The SE370C702 devices allow quick updates to
breadboards and prototype systems while iterating initial designs.
The TMS370Cx0x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In
the STANDBY mode, the internal oscillator and the general purpose timer remain active. In the HALT mode,
all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both
low-power modes.
The TMS370Cx0x features advanced register-to-register architecture that allows direct arithmetic and logical
operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to
the contents of register 47 and store the result in register 47). The TMS370Cx0x family is fully
instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller
family.
The TMS370Cx0x devices have two operational modes of serial communications provided by the SCI1 module.
The SCI1 allows standard RS-232-C communications with other common data transmission equipment.

TMS370Cx0x
description (continued)
The TMS370Cx0x family provides the system designer with an economical, efficient solution to real-time control
applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently
developing the software and hardware required to design the TMS370Cx0x into an ever-increasing number of
complex applications. The application source code can be written in assembly and C-language, and the output
code can be generated by the linker. The TMS370 family CDT development tool can communicate through a
standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer
editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use
through extensive menus and screen windowing so that a system designer with minimal training can begin
developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools
ensure efficient software and hardware implementation as well as reduced time-to-market cycle.
The TMS370Cx0x family together with the TMS370 family CDT370, design kit, starter kit, software tools, the
SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide
a complete solution to the needs of the system designer.
central processing unit (CPU)

The CPU used on the TMS370Cx0x device is the high-performance 8-bit TMS370 CPU module. The ’x0x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x0x instruction map is shown in Table 15 in the TMS370Cx0x instruction set overview
section.
The ’370Cx0x CPU architecture provides the following components:
CPU registers:
D A stack pointer that points to the last entry in the memory stack
D A status register that monitors the operation of the instructions and contains the global interrupt enable bits
D A program counter (PC) that points to the memory location of the next instruction to be executed
Figure 1 illustrates the CPU registers and memory blocks.
CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx0x
central processing unit (CPU) (continued)

15 Program Counter 0
7 Stack Pointer (SP) 0 Legend:

C=Carry
N=Negative
Z=Zero
Status Register (ST)
V=Overflow
C N Z V IE2 IE1
IE2=Level 2 interrupts Enable
7 6 5 4 3 2 1 0 IE1=Level 1 interrupts Enable
RAM (Includes 256-Byte Registers File) 0000h
256-Byte RAM (0000h - 00FFh) 00FFh
0000h 0100h
R0(A) Reserved†
100Fh
Peripheral File 1010h
0001h R1(B) 105Fh
1060h
0002h R2
Reserved
0003h R3
1EFFh
256-Byte Data EEPROM 1F00h
1FFFh
Not Available‡ 2000h
5FFFh
6000h
007Fh R127
8K-Byte ROM/EPROM (6000h – 7FFFh)
7FBFh
Interrupts and Reset Vectors; 7FC0h
R255 Trap Vectors
00FFh 7FFFh
† Reserved means the address space is reserved for future expansion.
‡ Not available means the address space is not accessible.
Figure 1. Programmer’s Model
A memory map that includes:

D 256-byte general-purpose RAM that can be used for data memory storage, program instructions,
general-purpose register, or the stack
D A peripheral file that provides access to all internal peripheral modules, system-wide control functions and
EEPROM/ EPROM programming control
D 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off
conditions
D 8K-byte ROM or 8K-byte EPROM program memory
stack pointer (SP)
The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read / write memory. The stack is used
typically to store the return address on subroutine calls as well as the status-register contents during interrupt
sequences.
The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM memory.

TMS370Cx0x

status register (ST)
The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST register
includes four status bits (condition flags) and two interrupt-enable bits:
D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional jump instructions) use the status bits to determine program flow.
D The two interrupt enable bits control the two interrupt levels.
The ST register, status-bit notation, and status-bit definitions are shown in Table 3.
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Table 3. Status Registers (ST)
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7
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C ÁÁÁÁÁ
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6
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N
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5
Z
4
V
3
IE2
2
IE1
1
Reserved
0
Reserved
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RW-0
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RW-0
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R = read, W = write, 0 = value after reset
RW-0 RW-0 RW-0
program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte and least significant byte of a 16-bit address.
During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
6000h as the contents of the reset vector.
Program Counter (PC)
Memory PCH PCL
0000h
60 00
7FFEh 60
7FFFh 00
Figure 2. Program Counter After Reset
memory map
The TMS370Cx0x architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input / output is memory mapped in this same common
address space. As shown in Figure 3, the TMS370Cx0x provides memory-mapped RAM, ROM, Data
EEPROM, input / output pins, peripheral functions, and system interrupt vectors.
The peripheral file contains all input / output port control, peripheral status and control, EEPROM, EPROM, and
system-wide control functions. The peripheral file is located between 1010h to 105Fh and is divided logically
into five peripheral-file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through
which peripheral control and data information is passed.

TMS370Cx0x

Peripheral File Control Registers
System Control 1010h – 101Fh
0000h Digital Port Control 1020h – 102Fh
256-Byte RAM
(Register File / Stack) Reserved† 1030h – 103Fh
00FFh
0100h Timer 1 Peripheral Control 1040h – 104Fh
Reserved†
SCI1 Peripheral Control 1050h – 105Fh
100Fh
1010h
Peripheral File
105Fh
1060h
Reserved†
1EFFh
1F00h
256-Byte Data EEPROM Vectors
1FFFh
2000h Trap 15 – 0 7FC0h – 7FDFh
Not Available‡ Reserved† 7FE0h – 7FEFh
5FFFh
6000h Serial Communications Interface TX 7FF0h – 7FF1h
6FFFh Serial Communications Interface RX 7FF2h – 7FF3h
7000h
8K-Byte ROM / EPROM
77FFh Timer 1 7FF4h – 7FF5h
(6000h – 7FFFh)
7800h
Reserved† 7FF6h – 7FF7h
7FBFh
7FC0h Interrupts and Reset Vectors; Interrupt 3 7FF8h – 7FF9h
7FFFh Trap Vectors
Interrupt 2 7FFAh – 7FFBh
8000h
Not Available‡ Interrupt 1 7FFCh – 7FFDh
FFFFh Reset 7FFEh – 7FFFh
† Reserved means the address space is reserved for future expansion.

‡ Not available means the address space is not accessible.
Figure 3. TMS370Cx0x Memory Map
RAM/ register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read / write memory, program
memory, or the stack instructions. The TMS370Cx0x devices contain 256 bytes of internal memory-mapped
RAM beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is shown in
Figure 1.
The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF)
The TMS370Cx0x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
shows the TMS370Cx0x PF address map.

TMS370Cx0x
peripheral file (PF) (continued)
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Table 4. TMS370Cx0x Peripheral File Address Map
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PERIPHERAL FILE
ADDRESS RANGE
DESIGNATOR
DESCRIPTION
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1000h – 100Fh P000 – P00F Reserved
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1010h – 101Fh P010 – P01F System and EPROM / EEPROM control registers
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1020h – 102Fh P020 – P02F Digital I / O port control registers
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1030h – 103Fh P030 – P03F Reserved
1040h – 104Fh P040 – P04F Timer 1 registers
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1050h – 105Fh P050 – P05F Serial communications interface registers
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1060h – 10FFh
data EEPROM
P060 – P0FF Reserved
The TMS370Cx0x devices, containing 256 bytes of data EEPROM, have their memory mapped beginning at
location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by
the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm
examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370
Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:
D Programming:
– Bit-, byte-, and block-write / erase modes
– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.
– Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame
beginning at location P01A. See Table 5.
– In-circuit programming capability. There is no need to remove the device to program.
D Write protection. Writes to the data EEPROM are disabled during the following conditions.
– Reset. All programming of the data EEPROM module is halted.
– Write protection active. There is one write-protect bit per 32-byte EEPROM block.
– Low-power mode operation
D Write protection can be overridden by applying 12 V to MC.
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Table 5. Data EEPROM and Program EPROM Control Registers Memory Map
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ADDRESS SYMBOL NAME
P01A DEECTL Data EEPROM control register
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P01B — Reserved
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P01C EPCTL Program EPROM control register

TMS370Cx0x
program EPROM
The TMS370C702 device contains 8K bytes of EPROM, mapped, at location 6000h and continuing through
location 7FFFh as shown in Figure 3. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and
reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses
7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During
programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module
features include:
D Programming
– In-circuit programming capability if VPP is applied to MC
– Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in
the peripheral file (PF) frame at location P01Ch as shown in Table 5.
D Write protection: Writes to the program EPROM are disabled under the following conditions:
– Reset halts all programming to the EPROM module.
– Low-power modes
– 13 V not applied to MC
program ROM
The program read-only memory (ROM) consists of 8K bytes of mask-programmable ROM. The program ROM
is used for permanent storage of data or instructions. Memory addresses 7FF0h through 7FFFh are reserved
for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located
between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device
fabrication. Refer to Figure 3 for ROM memory map.
system reset
The system reset operation ensures an orderly start-up sequence for the TMS370Cx0x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
internally generated, while one (RESET pin) is controlled externally. These actions are as follows:
D External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 Family User’s Guide (literature number SPNU127) for more information.
D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer times out . See the TMS370
Family User’s Guide (literature number SPNU127) for more information.
D Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See
the TMS370 Family User’s Guide (literature number SPNU127) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x0x device to reset external system components. Additionally, if a cold start (VCC is off
for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag
(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

TMS370Cx0x
system reset (continued)
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Table 6. Reset Sources
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
REGISTER ADDRESS PF BIT NO. CONTROL BIT SOURCE OF RESET
SCCR0 1010h P010 7 COLD START Cold (power-up)
ÁÁÁÁÁ
ÁÁÁÁÁÁ
SCCR0
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
1010h
P010 4 OSC FLT FLAG Oscillator out of range
ÁÁÁÁÁ
ÁÁÁÁÁÁ
T1CTL2
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
104Ah
P04A 5 WD OVRFL INT FLAG
Once a reset is activated, the following sequence of events occurs:

Watchdog timer timeout
1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.

TMS370Cx0x
interrupts
The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of
the status register.
EXT INT 3
INT 3
EXT INT 2
INT 2
INT3 PRI
TIMER1
Overflow
INT2 PRI
Compare1
EXT INT1
Ext Edge CPU
INT1
Compare2
Input Capture NMI
Watchdog
INT1 PRI Priority

Logic
T1 PRI STATUS REG
IE1
Level 1 INT
IE2
Level 2 INT
Enable
SCI INT
TX RX
TXRDY
RXPRI
TXPRI BRKDT
RXRDY
Figure 4. Interrupt Control
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

TMS370Cx0x
interrupts (continued)
chains is performed within the peripheral modules to support interrupt expansion for future modules.
Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt
mask and priority conditions.
The TMS370Cx0x has six hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt
has a dedicated vector located in program memory through which control is passed to the interrupt service
routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are individually
maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit
is individually readable for software polling or for determining which interrupt source generated the associated
system interrupt.
Three of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are
supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input
polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as
either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked
by the individual- or global-enable-mask bits. The INT1 NMI bit is protected during non-privileged operation and,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the
interrupt function is not required (INT1 can be similarly configured as an input pin).
Table 7. Hardware System Interrupts
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁÁÁ
INTERRUPT SOURCE
ÁÁÁÁ INTERRUPT FLAG
SYSTEM
INTERRUPT
VECTOR
ADDRESS
PRIORITY†
ÁÁÁÁÁÁÁÁÁ
External RESET
ÁÁÁÁÁÁÁÁÁ
Watchdog Overflow ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
COLD START
WD OVRFL INT FLAG RESET‡ 7FFEh, 7FFFh 1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
Oscillator Fault Detect OSC FLT FLAG
External INT1 INT1 FLAG INT1‡ 7FFCh, 7FFDh 2
ÁÁÁÁÁÁÁÁÁ
External INT2
ÁÁÁÁÁÁÁÁÁ
External INT3 ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
INT2 FLAG
INT3 FLAG
INT2‡
INT3‡
7FFAh, 7FFBh
7FF8h, 7FF9h
3
4
ÁÁÁÁÁÁÁÁÁ
Timer 1 Overflow
ÁÁÁÁÁÁÁÁÁ
Timer 1 Compare 1
Timer 1 Compare 2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
T1INT§ 7FF4h, 7FF5h 5
Timer 1 External Edge T1EDGE INT FLAG
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
Timer 1 Input Capture 1 T1IC1 INT FLAG
Watchdog Overflow WD OVRFL INT FLAG
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
SCI RX Data Register Full
ÁÁÁÁÁÁ
SCI RX Break Detect ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
RXRDY FLAG
BRKDT FLAG
RXINT‡ 7FF2h, 7FF3h 6
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
SCI TX Data Register Empty TXRDY FLAG TXINT 7FF0h, 7FF1h 7
† Relative priority within an interrupt level
‡ Release microcontroller from STANDBY and HALT low-power modes.
§ Release microcontroller from STANDBY low-power mode.
privileged operation and EEPROM write protection override

The TMS370Cx0x family has significant flexibility to enable the designer to software configure the system and
peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures
the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the
TMS370Cx0x operates in the privileged mode, where all peripheral file registers have unrestricted read / write
access, and the application program configures the system during the initialization sequence following reset.
As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the

TMS370Cx0x
privileged operation and EEPROM WPO (continued)

nonprivileged mode, thus disabling write operations to specific configuration control bits within the peripheral
file. Table 8 lists the system configuration bits which are write-protected during the nonprivileged mode and must
be configured by software prior to exiting the privileged mode.
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Table 8. Privileged Bits
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
REGISTER†
ÁÁÁÁÁÁÁÁÁ
NAME LOCATION
CONTROL BIT
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P010.5 PF AUTO WAIT
SCCR0
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P010.6 OSC POWER
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P011.2 MEMORY DISABLE
SCCR1
P011.4 AUTOWAIT DISABLE
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P012.0
P012.1
P012.3
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SCCR2
P012.4 BUS STEST
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P012.6 PWRDWN / IDLE
P012.7 HALT / STANDBY
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SCIPRI
P05F.4
P05F.5
SCI ESPEN
SCIRX PRIORITY
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P05F.6 SCITX PRIORITY
P05F.7 SCI STEST
ÁÁÁÁÁ
ÁÁÁÁÁ
T1PRI
ÁÁÁÁÁÁÁÁÁ P04F.6
P04F.7
T1 PRIORITY
T1 STEST
† The privileged bits are shown in a bold typeface in Table 10.
The write protect override (WPO) mode is an external hardware method of overriding the write protection
registers (WPR) of data EEPROM on the TMS370Cx0x. WPO mode is entered by applying a 12-V input to the
MC pin after the RESET pin input goes high (logic 1). The high voltage (+ 12 V) on the MC pin during the WPO
mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming
voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the
content of data EEPROM while the device remains in the application but only while requiring a 12-V external
input on the MC pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes

The TMS370Cx0x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time the mask is manufactured.
The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The
HALT / STANDBY bit in SCCR2 controls the low-power mode selection.
In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops;
however, the oscillator, internal clocks, timer 1 and the receive-start bit detection circuit of the serial
communications interface remain active. System processing is suspended until a qualified interrupt (hardware
RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is
detected.

TMS370Cx0x
low-power and IDLE modes (continued)

In the HALT mode (HALT / STANDBY = 1), the TMS370Cx0x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level
on the receive pin of the SCI1) is detected. The power-down mode selection bits are summarized in Table 9.
ÁÁÁÁÁÁÁ
Table 9. Low-Power / Idle Control Bits
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ
POWER-DOWN CONTROL BITS
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
PWRDWN / IDLE HALT / STANDBY MODE SELECTED
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
(SCCR2.6) (SCCR2.7)
1 0 STANDBY
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1 1 HALT
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
† Don’t care
X† IDLE
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6-7 bits are ignored. In addition, if an idle instruction executes when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is generated always, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter, and status register), I / O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU instruction processing stops during the STANDBY
and HALT modes, the clocking of the watchdog timer is inhibited.
clock modules
The ’x0x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The ’x0x ROM-masked devices offer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’702A
EPROM has only the divide-by-4.
The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN)
to the internal system clock (SYSCLK) frequency, whereas the divide-by-4 option produces a SYSCLK which
is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the
external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide
the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

TMS370Cx0x
clock modules (continued)

These are formulated as follows:
Divide-by-4 : SYSCLK + external resonator

4
frequency
+ CLKIN
4
Divide-by-1 : SYSCLK + external resonator4 frequency 4

+ CLKIN
The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of
low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.
The divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a
steeper decay of emissions produced by the oscillator.
system configuration registers

Table 10 contains system configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface and shaded areas.
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Table 10. Peripheral File Frame 1: System Configuration Registers
PF
ÁÁÁÁÁÁÁÁÁ
BIT 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
BIT 6
ÁÁÁÁÁÁÁÁÁ
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P010
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ
COLD
ÁÁÁÁ
START ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
OSC
ÁÁÁÁ
POWERÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
PF AUTO
ÁÁÁÁ
WAIT
OSC FLT
FLAG
MC PIN
WPO
MC PIN
DATA
—
µP / µC
MODE
SCCR0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ

AUTO
MEMORY
P011 — — — WAIT — — — SCCR1
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DISABLE
DISABLE
ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

HALT / PWRDWN / BUS CPU INT1 PRIVILEGE
P012 — — SCCR2
ÁÁÁÁ ÁÁÁÁ
STANDBY IDLE STEST STEST NMI DISABLE
P013
to
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P016
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
INT1 INT1 INT1 INT1 INT1
P017 — — — INT1
FLAG PIN DATA POLARITY PRIORITY ENABLE
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
P018
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
INT2
ÁÁÁÁ
FLAG ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
INT2
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
PIN DATA ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
—
INT2
DATA DIR
INT2
DATA OUT
INT2
POLARITY
INT2
PRIORITY
INT2
ENABLE
INT2
INT3 INT3 INT3 INT3 INT3 INT3 INT3
P019 — INT3
FLAG PIN DATA DATA DIR DATA OUT POLARITY PRIORITY ENABLE
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P01A
ÁÁÁÁ
P01B ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
BUSY
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁ
—
Reserved
— AP W1W0 EXE DEECTL
P01C
ÁÁÁÁÁÁÁÁÁ
BUSY
ÁÁÁÁÁÁÁÁÁ
VPPS
— — — — W0 EXE EPCTL
ÁÁÁÁ P01D
P01E
P01F
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Reserved

TMS370Cx0x
digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 shows the specific
addresses, registers, and control bits within this peripheral file frame.
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁ
Table 11. Peripheral File Frame 2: Digital Port Control Registers
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
PF
P020
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BIT 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BIT 6
ÁÁÁÁÁ
ÁÁÁ
BIT 5 BIT 4
Reserved
BIT 3 BIT 2 BIT 1 BIT 0 REG
APORT1
ÁÁÁ
P021
ÁÁÁ
P022 ÁÁÁ
ÁÁÁ
Port A Control Register 2 (must be 0)
Port A Data
APORT2
ADATA
ÁÁÁ
P023
ÁÁÁ Port A Direction ADIR
ÁÁÁ ÁÁÁ
P024
Á
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
to Reserved
P02B
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P02C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P02D ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
Port D Control Register 1 (must be 0)
ÁÁÁÁÁ
ÁÁÁ
Port D Control Register 2 (must be 0)†
—
—
—
—
—
—
DPORT1
DPORT2
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
P02E Port D Data — — — DDATA
ÁÁÁÁÁÁÁ
ÁÁÁ
P02F Port D Direction — — — DDIR
† To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁTable 12. Port Configuration Register Setup
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
PORT ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
PIN
abcd
00q1
abcd
00y0
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0–7 Data OUT q Data In y
ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ

D 3–7 Data OUT q Data In y
a = Port x Control Register 1
b = Port x Control Register 2
c = Data
d = Direction

TMS370Cx0x
programmable timer 1
The programmable Timer 1 (T1) module of the TMS370Cx0x provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock
sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The timer 1 module includes three external device pins that can be
used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. The T1
module block diagram is shown in Figure 5.
Edge 16-Bit
T1IC/CR
Select Capt/Comp
Register
16-Bit PWM
MUX 16 T1PWM
Counter Toggle
16-Bit
Compare Interrupt
8-Bit Register Logic
T1EVT
Prescaler
Interrupt
Logic
MUX 16-Bit
Watchdog Counter
(Aux. Timer)
Figure 5. Timer 1 Block Diagram
D Three T1 I/O pins

– T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin
– T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
– T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin
D Two operation modes:
– Dual-compare mode: Provides PWM signal
– Capture/compare mode: Provides input capture pin
D One 16-bit general-purpose resettable counter
D One 16-bit compare register with associated compare logic
D One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register.
D One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer
if watchdog feature is not needed.
D Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

TMS370Cx0x
programmable timer 1 (continued)

D Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC1/CR)
D Interrupts that can be generated on the occurrence of:
– A capture
– A compare equal
– A counter overflow
– An external edge detection
D Sixteen timer 1 module control registers located in the PF frame beginning at address P040.
The T1 module control registers are illustrated in Table 13.

TMS370Cx0x
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
Table 13. Timer 1 Module Register Memory Map
ÁÁÁ
ÁÁÁÁ
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
ÁÁÁ
ÁÁÁÁ
Modes: Dual-Compare and Capture / Compare
ÁÁÁ
ÁÁÁÁ
P040 Bit 15 T1Counter MSbyte Bit 8 T1CNTR
P041 Bit 7 T1 Counter LSbyte Bit 0
ÁÁÁ
P042 Bit 15
ÁÁÁ ÁÁÁÁ
P043 Bit 7
ÁÁÁÁÁ
ÁÁÁ
Compare Register MSbyte
Compare Register LSbyte
Bit 8
Bit 0
T1C
ÁÁÁ
P044 Bit 15
ÁÁÁ
P045 Bit 7 Á ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
Bit 8
Bit 0
T1CC
ÁÁÁ
P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
P047 Bit 7 Watchdog Counter LSbyte Bit 0
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
P048 Bit 7 Watchdog Reset Key Bit 0 WDRST
WD OVRFL WD INPUT WD INPUT WD INPUT T1 INPUT T1 INPUT T1 INPUT
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
P049 — T1CTL1
TAP SEL† SELECT2† SELECT1† SELECT0† SELECT2 SELECT1 SELECT0
ÁÁÁ
ÁÁÁÁÁ
P04A
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
WD OVRFL
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
WD OVRFL
ÁÁÁÁ
WD OVRFL T1 OVRFL T1 OVRFL
— —
T1
T1CTL2
RST ENA† INT ENA INT FLAG INT ENA INT FLAG SW RESET
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Mode: Dual-Compare
ÁÁÁ
ÁÁÁÁÁ
T1EDGE
ÁÁÁÁ
T1C2
ÁÁÁÁÁ
T1C1
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
T1EDGE
ÁÁÁÁ
T1C2
ÁÁÁÁÁ
T1C1
ÁÁÁÁ
P04B — — T1CTL3
INT FLAG INT FLAG INT FLAG INT ENA INT ENA INT ENA
ÁÁÁ
ÁÁÁÁÁ
P04C
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
T1
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1C1
ÁÁÁÁ
T1C2 T1C1 T1CR T1EDGE T1CR T1EDGE
T1CTL4
MODE=0 OUT ENA OUT ENA RST ENA OUT ENA POLARITY RST ENA DET ENA
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Mode: Capture / Compare
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
T1EDGE T1C1 T1EDGE T1C1
P04B — — — — T1CTL3
INT FLAG INT FLAG INT ENA INT ENA
ÁÁÁ
ÁÁÁÁÁ
P04C
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
T1
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1C1
ÁÁÁÁ
—
T1C1
—
T1EDGE
—
T1EDGE
T1CTL4
MODE = 1 OUT ENA RST ENA POLARITY DET ENA
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
T1EVT T1EVT T1EVT T1EVT
P04D — — — — T1PC1
DATA IN DATA OUT FUNCTION DATA DIR
ÁÁÁ
ÁÁÁÁÁ
P04E
ÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
T1PWM
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
DATA IN
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1PWM
ÁÁÁÁ
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
T1IC/CR
FUNCTION
T1IC/CR
DATA DIR
T1PC2
ÁÁÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
T1
P04F T1 STEST — — — — — — T1PRI
PRIORITY
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
† Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.

TMS370Cx0x

Figure 6 shows the timer 1 capture/compare mode block diagram. The annotations on the diagram identify the
register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in
the T1CTL2 register.
T1CC.15-0
16-Bit LSB
Capt/Comp T1C1
Prescale Register MSB OUT ENA T1PC2.7-4
Toggle
Clock
Source T1CTL4.6
T1PWM
T1CNTR.15-0
LSB 16-Bit
16
MSB Counter
T1 PRIORITY 0
T1C1 INT FLAG T1PRI.6 Level 1 Int
Compare= T1CTL3.5 1
Reset Level 2 Int
T1CTL3.0
T1 SW T1C.15-0
RESET T1C1 INT ENA
16-Bit LSB
T1CTL2.0 T1C1 Compare
RST ENA Register MSB
T1 OVRFL INT FLAG

T1CTL4.4 T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1PC2.3-0
T1EDGE DET ENA
T1IC/CR T1EDGE INT FLAG
Edge
Select T1CTL3.7
T1CTL4.0
T1CTL3.2
T1EDGE INT ENA
T1CTL4.2
T1EDGE POLARITY
Figure 6. Capture/Compare Mode

TMS370Cx0x

Figure 7 shows the timer 1 dual-compare mode block diagram. The annotations on the diagram identify the
register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in
the T1CTL2 register.
T1CC.15-0
16-Bit LSB T1C2 INT FLAG
Capt/Comp
Prescaler T1CTL3.6
Register MSB Output
Clock
Source Enable
T1CTL3.1
T1C2 INT ENA T1CTL4.5
T1CNTR.15-0 Compare=
T1PC2.7-4
LSB 16-Bit T1C2 OUT ENA
Toggle
Counter 16 T1C1 INT FLAG T1CTL4.6 T1PWM
MSB
T1CTL3.5
Reset Compare=
T1CTL3.0 T1C1 OUT ENA
T1C1 T1C.15-0 T1CTL4.3
T1 SW
RST ENA T1C1 INT ENA
RESET
16-Bit LSB
T1CTL4.4 Compare T1CR OUT ENA
T1CTL2.0
Register MSB
T1 OVRFL INT FLAG

T1CTL4.1 T1CTL2.3
T1CR
T1PC2.3-0 RST ENA T1CTL2.4
Edge T1 OVRFL INT ENA
T1IC/CR Select T1 PRIORITY
0
T1CTL4.0 T1EDGE INT FLAG T1PRI.6 Level 1 Int
T1EDGE DET ENA T1CTL3.7 1
T1CTL4.2 Level 2 Int
T1CTL3.2
T1EDGE POLARITY
T1EDGE INT ENA
Figure 7. Dual-Compare Mode

TMS370Cx0x

The TMS370Cx0x device includes a 24-bit watchdog (WD) timer, contained in the timer 1 module, which can
be programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not used.
The WD function is to monitor software and hardware operation and to implement a system reset when the WD
counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The
WD can be configured as one of three mask options as follows:
D Standard watchdog configuration (see Figure 8) – for EPROM and mask-ROM devices:
– Watchdog mode
– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows
– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
– Non-watchdog mode
– Watchdog timer can be configured as an event counter, a pulse accumulator, or an interval timer
WDCNTR.15-0
WD OVRFL
16-Bit INT FLAG T1CTL2.6
WatchdogCounter
T1CTL2.5 Interrupt
WD OVRFL
Reset
INT ENA
Clock T1CTL2.7
Prescaler T1CTL1.7
WD OVRFL
TAP SEL System Reset
WD OVRFL
Watchdog Reset Key RST ENA
WDRST.7-0
Figure 8. Standard watchdog

TMS370Cx0x

D Hard watchdog configuration (see Figure 9) – for mask-ROM devices:
– Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK
– A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter
overflows.
– Automatic activation of the WD timer upon power-up reset
– INT1 is enabled as a nonmaskable interrupt during low-power modes.
– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
WDCNTR.15-0
WD OVRFL
16-Bit INT FLAG
Watchdog Counter
T1CTL2.5
Reset
Clock
Prescaler T1CTL1.7
WD OVRFL
TAP SEL System Reset
Watchdog Reset Key
WDRST.7-0
Figure 9. Hard Watchdog
D Simple counter configuration – for mask-ROM devices only (see Figure 10)
– Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

TMS370Cx0x

WDCNTR.15-0
WD OVFL
16-Bit INT FLAG T1CTL2.6
Watchdog Counter
T1CTL2.5 Interrupt
WD OVRFL
Reset
INT ENA
Clock
Prescaler T1CTL1.7
WD OVRFL
TAP SEL
Watchdog Reset Key
WDRST.7-0
Figure 10. Simple Counter
serial communications interface 1 (SCI1) module

The TMS370Cx0x devices include a serial communications interface 1 (SCI1) module. The SCI1 module
supports digital communications between the TMS370 devices and other asynchronous peripherals and uses
the standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and
each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in
the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun,
and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a
16-bit baud-select register.
Features of the SCI1 module include:
D Three external pins:
– SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin
– SCIRXD: SCI receive-input pin or general-purpose bidirectional I/O pin
– SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin
D Two communications modes: asynchronous and isosynchronous†
D Baud rate: 64K different programmable rates
– Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK
ASYNCHRONOUS BAUD + (BAUD SYSCLK

REG ) 1) 32
– Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK
ISOSYNCHRONOUS BAUD + (BAUDSYSCLK

REG ) 1) 2
† Isosynchronous = Isochronous

TMS370Cx0x
serial communications interface 1 (SCI1) module (continued)

D Data word format:
– One start bit
– Data word length programmable from one to eight bits
– Optional even / odd / no parity bit
– One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: Idle-line and address bit
D Half or full-duplex operation
D Double-buffered receiver and transmitter operations
D Transmitter and receiver operations can be accomplished through either interrupt-driven or
polled-algorithms with status flags:
– Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX
EMPTY flag (Transmitter shift register is empty)
– Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR monitoring four interrupt conditions
– Separate enable bits for transmitter and receiver interrupts
– NRZ (non return-to-zero) format
D Eleven SCI1 module control registers, located in control register frame beginning at address P050h

TMS370Cx0x

The SCI1 module control registers are illustrated in Table 14.
ÁÁÁÁ
ÁÁÁ
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
Table 14. SCI1 Module Control Register Memory Map
Á
ÁÁ ÁÁÁÁ
ÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
ÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
EVEN/ODD PARITY ASYNC/ ADDRESS/ SCI
P050 STOP BITS SCI CHAR1 SCI CHAR0 SCICCR
PARITY ENABLE ISOSYNC IDLE WUP CHAR2
Á
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
P051
ÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
SCI SW
ÁÁÁÁÁ
ÁÁÁÁ
RESET Á
Á
CLOCK TXWAKE SLEEP TXENA RXENA SCICTL
Á ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
BAUDF
P052 BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD MSB
(MSB)
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
P053
ÁÁÁÁ
ÁÁÁÁ
BAUD7
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
BAUD6
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
BAUD5
Á
Á
BAUD4 BAUD3 BAUD2 BAUD1
BAUD0
(LSB)
BAUD LSB
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
SCI TX
P054 TXRDY TX EMPTY — — — — — TXCTL
Á
ÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
INT ENA
RX SCI RX
ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
P055 RXRDY BRKDT FE OE PE RXWAKE RXCTL
ERROR INT ENA
ÁÁÁÁ
P056
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ Á
Á
Reserved
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
P057 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 RXBUF
ÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
P058 Reserved
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P059 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 TXBUF
ÁÁÁ Á ÁÁÁÁ Á
P05A
P05B Reserved
ÁÁÁ ÁÁÁÁÁ ÁÁÁ

ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á
P05C
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
SCICLK SCICLK SCICLK SCICLK
P05D — — — — SCIPC1
ÁÁÁ
P05E
Á
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
SCITXD
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
DATA IN ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
SCITXD
ÁÁÁÁ ÁÁÁÁ
ÁÁÁÁÁ
DATA OUT ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
SCITXD
ÁÁÁÁÁ
ÁÁÁÁ
FUNCTION Á
Á
SCITXD
DATA DIR
SCIRXD
DATA IN
SCIRXD
DATA OUT
SCIRXD
FUNCTION
SCIRXD
DATA DIR
SCIPC2
Á ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
SCITX SCIRX SCI
P05F SCI STEST — — — — SCIPRI
Á ÁÁÁÁ
ÁÁÁ ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ Á
PRIORITY PRIORITY ESPEN

TMS370Cx0x

The SCI1 module block diagram is illustrated in Figure 11.
TXWAKE TXBUF.7 – 0
Frame Format and Mode
SCICTL.3 SCI TX Interrupt SCITX PRIORITY
ÏÏÏÏ
PARITY Transmit Data
EVEN / ODD ENABLE 1 Buffer Reg.
SCI TX INT ENA SCIPRI.6 0
TXRDY Level 1 INT
SCICCR.6 SCICCR.5 TXCTL.7
WUT 1
Level 2 INT
8 TXCTL.0
TX EMPTY
TXCTL.6
TXENA SCIPC2.7 – 4
TXSHF Reg. SCITXD
BAUD MSB. 7 – 0 SCITXD
Baud Rate SCICTL.1

MSbyte Reg. CLOCK
SYSCLK SCIPC1.3 – 0
SCICLK
BAUD LSB. 7 – 0 SCICTL.4
Baud Rate
LSbyte Reg. SCIPC2.3 – 0
SCIRXD
RXSHF Reg. SCIRXD
RXWAKE
ÏÏÏ
RXCTL.1 SCI RX Interrupt SCIRX PRIORITY
ÏÏÏ
RXENA
SCIPRI.5 0
RXRDY SCI RX INT ENA Level 1 INT
RX ERROR SCICTL.0 RXCTL.6
8 1
Level 2 INT
RXCTL.0
RXCTL.7 RXCTL.4 – 2
Receive Data BRKDT
ERR FE OE PE Buffer Reg. RXCTL.5
RXBUF.7 – 0
Figure 11. SCI1 Block Diagram
instruction set overview

Table 15 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the
‘370Cx0x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode
while the numbers at the left side of the table represent the least significant nibble. The instructions for these
two opcode nibbles contain the mnemonic, operands, and byte / cycle particular to that opcode.
For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.

Table 15. TMS370 Family Opcode/Instruction Map†
MSN
0 1 2 3 4 5 6 7 8 9 A B C D E F
JMP INCW MOV CLRC / MOV MOV TRAP LDST

0 #ra #ra,Rd Ps,A TST A A,B A,Rd 15 n
2/7 3/11 2/8 1/9 1/9 2/7 1/14 2/6
JN MOV MOV MOV MOV MOV TRAP MOV

1 ra A,Pd B,Pd Rs,Pd Ps,B B,Rd 14 #ra[SP],A
2/5 2/8 2/8 3/10 2/7 2/7 1/14 2/7
JZ MOV MOV MOV MOV MOV MOV MOV MOV DEC DEC DEC TRAP MOV
2 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd Ps,Rd A B Rd 13 A,*ra[SP]
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 3/10 1/8 1/8 2/6 1/14 2/7
JC AND AND AND AND AND AND AND AND AND AND INC INC INC TRAP CMP
3 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd A,Pd B,Pd #n,Pd A B Rd 12 *n[SP],A
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 2/9 2/9 3/10 1/8 1/8 2/6 1/14 2/8
JP OR OR OR OR OR OR OR OR OR OR INV INV INV TRAP extend

4 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd A,Pd B,Pd #n,Pd A B Rd 11 inst,2
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 2/9 2/9 3/10 1/8 1/8 2/6 1/14 opcodes
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
JPZ XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR CLR CLR CLR TRAP
L 5 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd A,Pd B,Pd #n,Pd A B Rn 10
S 2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 2/9 2/9 3/10 1/8 1/8 2/6 1/14
N
JNZ BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO XCHB XCHB A / XCHB TRAP IDLE
6 ra Rs,A,ra #n,A,ra Rs,B,ra Rs,Rd,ra #n,B,ra B,A,ra #n,Rd,ra A,Pd,ra B,Pd,ra #n,Pd,ra A TST B Rn 9
2/5 3/9 3/8 3/9 4/11 3/8 2/10 4/10 3/11 3/10 4/11 1/10 1/10 2/8 1/14 1/6
JNC BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ SWAP SWAP SWAP TRAP MOV
7 ra Rs.,A,ra #n,A,ra Rs,B,ra Rs,Rd,ra #n,B,ra B,A,ra #n,Rd,ra A,Pd,ra B,Pd,ra #n,Pd,ra A B Rn 8 #n,Pd
2/5 3/9 3/8 3/9 4/11 3/8 2/10 4/10 3/10 3/10 4/11 1/11 1/11 2/9 1/14 3/10
JV ADD ADD ADD ADD ADD ADD ADD MOVW MOVW MOVW PUSH PUSH PUSH TRAP SETC
8 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd #16,Rd Rs,Rd #16[B],Rpd A B Rd 7
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 4/13 3/12 4/15 1/9 1/9 2/7 1/14 1/7
JL ADC ADC ADC ADC ADC ADC ADC JMPL JMPL JMPL POP POP POP TRAP RTS
9 ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd lab *Rp *lab[B] A B Rd 6
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 3/9 2/8 3/11 1/9 1/9 2/7 1/14 1/9

JLE SUB SUB SUB SUB SUB SUB SUB MOV MOV MOV DJNZ DJNZ DJNZ TRAP RTI
A ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd & lab,A *Rp,A *lab[B],A A,#ra B,#ra Rd,#ra 5
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 3/10 2/9 3/12 2/10 2/10 3/8 1/14 1/12
JHS SBB SBB SBB SBB SBB SBB SBB MOV MOV MOV COMPL COMPL COMPL TRAP PUSH
B ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd A, & lab A, *Rp A,*lab[B] A B Rd 4 ST
2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 3/10 2/9 3/12 1/8 1/8 2/6 1/14 1/8
† All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
TMS370Cx0x
29
Table 15. TMS370 Family Opcode/Instruction Map† (Continued)
TMS370Cx0x
30
Template Release Date: 7–11–94

MSN
0 1 2 3 4 5 6 7 8 9 A B C D E F
JNV MPY MPY MPY MPY MPY MPY MPY BR BR BR RR RR RR TRAP POP
C ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rs lab *Rp *lab[B] A B Rd 3 ST
2/5 2/46 2/45 2/46 3/48 2/45 1/47 3/47 3/9 2/8 3/11 1/8 1/8 2/6 1/14 1/8
JGE CMP CMP CMP CMP CMP CMP CMP CMP CMP CMP RRC RRC RRC TRAP LDSP
D ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd & lab,A *Rp,A *lab[B],A A B Rd 2
L 2/5 2/7 2/6 2/7 3/9 2/6 1/8 3/8 3/11 2/10 3/13 1/8 1/8 2/6 1/14 1/7
S
N JG DAC DAC DAC DAC DAC DAC DAC CALL CALL CALL RL RL RL TRAP STSP
E ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd lab *Rp *lab[B] A B Rd 1
2/5 2/9 2/8 2/9 3/11 2/8 1/10 3/10 3/13 2/12 3/15 1/8 1/8 2/6 1/14 1/8
JLO DSB DSB DSB DSB DSB DSB DSB CALLR CALLR CALLR RLC RLC RLC TRAP NOP
F ra Rs,A #n,A Rs,B Rs,Rd #n,B B,A #n,Rd lab *Rp *lab[B] A B Rd 0
2/5 2/9 2/8 2/9 3/11 2/8 1/10 3/10 3/15 2/14 3/17 1/8 1/8 2/6 1/14 1/7
MOVW DIV
Second byte of two-byte instructions (F4xx): F4 8 *n[Rn] Rn.A
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
4/15 3/14-63
JMPL
F4 9 *n[Rn]
4/16
Legend: MOV
* = Indirect addressing operand prefix F4 A *n[Rn],A
& = Direct addressing operand prefix 4/17
# = immediate operand MOV
#16 = immediate 16-bit number F4 B A,*n[Rn]
lab = 16-label 4/16
n = immediate
i di t 8-bit
8 bit number
b
BR
Pd = Peripheral register containing destination type F4 C *n[Rn]
Pn = Peripheral register 4/16
Ps = Peripheral
Peri heral register containing source byte
ra = Relative address CMP
F4 D *n[Rn],A
Rd = Register containing destination type
4/18
Rn = Register file
Rp = Register pair CALL
Rpd = Destination register pair F4 E *n[Rn]
Rps = Source Register pair 4/20
Rs = Register containing source byte CALLR
F4 F *n[Rn]
4/22
† All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ
instructions have a relative address as the last operand.
TMS370Cx0x
development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, and compact
development tool, and an EEPROM / UVEPROM programmer.
D Assembler/ linker (Part No. TMDS3740850–02 for PC)
– Includes extensive macro capability
– Allows high-speed operation
– Provides format conversion utilities for popular formats
D ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3
or Sun-4)
– Generates assembly code for the TMS370 that can be inspected easily
– Improves code execution speed and reduces code size with optional optimizer pass
– Enables direct reference to the TMS370’s port registers by using a naming convention
– Provides flexibility in specifying the storage for data objects
– Interfaces C functions and assembly functions easily
– Includes assembler and linker
D CDT370 (compact development tool) real-time in-circuit emulation
– Base (Part Number EDSCDT370 – for PC, requires cable)
– Cable for 28-pin PLCC (Part No. EDSTRG28PLCC02)
– Includes EEPROM and EPROM programming support
– Allows inspection and modification of memory locations
– Allows uploading / downloading program and data memory
– Executes programs and software routines
– Includes 1 024 samples trace buffer
– Provides single-step executable instructions
– Uses software breakpoints to halt program execution at selected address
D Microcontroller programmer
– Base (Part No. TMDS3760500A – for PC, requires programmer head)
– Single unit head for 28-pin PLCC (Part No. TMDS3780510A)
– Personal computer based, window / function-key-oriented user interface for ease of use and rapid
learning environment
HP700 is a trademark of Hewlett-Packard Company.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

TMS370Cx0x
development system support (continued)

D Design kit (Part No. TMDS3770110 – for PC)
– Includes TMS370 Application Board and TMS370 Assembler diskette and documentation
– Supports quick evaluation of TMS370 functionality
– Provides capability to upload and download code
– Provides capability to execute programs and software routines, and to single-step executable
instructions
– Provides software breakpoints to halt program execution at selected addresses
– Includes wire-wrap prototype area
– Includes reverse assembler
D Starter Kit (Part No. TMDS37000 – for PC)
– Includes TMS370 Assembler diskette and documentation
– Includes TMS370 Simulator
– Includes programming adapter board and programming software
– Does not include (to be supplied by the user):
– + 5 V power supply
– ZIF sockets
– Nine-pin RS232 cable

TMS370Cx0x
device numbering conventions

Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx0x family.
TMS 370 C 7 0 2 A FN T
Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator that is used for
prototyping purpose.
Family: 370 = TMS370 8-Bit Microcontroller Family
Technology: C = CMOS
Program Memory Types: 0 = Mask ROM
3 = Mask ROM, No Data EEPROM
7 = EPROM
Device Type: 0 = ’x0x devices containing the following modules:
— Timer 1
— Serial Communications Interface 1 (SCI1)
Memory Size: 2 = 8K bytes
Temperature Ranges: A = –40°C to 85°C
L = 0°C to 70°C
T = –40°C to 105°C
Packages: FN = Plastic Leaded Chip Carrier
FZ = Ceramic Leaded Chip Carrier
ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured
as one of the three different mask options:
– A standard watchdog
– A hard watchdog
– A simple watchdog
The clock mask option can be either:
– Divide-by-4 clock
– Divide-by-1 (PLL) clock
The low-power modes can be either:
– Enabled
– Disabled
NONE = For EPROM device, a standard watchdog, a
divide-by-4 clock, and low-power modes are enabled.
Figure 12. TMS370Cx0x Family Nomenclature

TMS370Cx0x
device part numbers

Table 16 provides all of the ’x0x devices available. The device part number nomenclature is designed to assist
ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and
watchdog timer options desired. Each device can have only one of the three possible watchdog timer options
and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.
Table 16. Device Part Numbers

DEVICE PART NUMBERS
FOR 28 PINS (LCC)
TMS370C002AFNA
TMS370C002AFNL
TMS370C002AFNT
TMS370C302AFNA
TMS370C302AFNL
TMS370C302AFNT
TMS370C702FNT
SE370C702FZT†
† System evaluators are for use in prototype environment and their
reliability has not been characterized.

TMS370Cx0x
new code release form

Figure 13 shows a sample of the new code release form.
NEW CODE RELEASE FORM

TEXAS INSTRUMENTS DATE:
TMS370 MICROCONTROLLER PRODUCTS
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.
Company Name: Contact Mr./Ms.:

Street Address: Phone: ( ) Ext.:
Street Address:
City: State Zip Customer Purchase Order Number:
Customer Print Number *Yes: #
Customer Part Number:
No: (Std. spec to be followed)
Customer Application:
*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM
code processing starts.
TMS370 Device:
TI Customer ROM Number:
(provided by Texas Instruments) CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS
OSCILLATOR FREQUENCY Low Power Modes Watchdog counter Clock Type

MIN TYP MAX [] Enabled [] Standard [] Standard (/4)
[] External Drive (CLKIN) [] Disabled [] Hard Enabled [] PLL (/1)
[] Crystal [] Simple Counter
[] Ceramic Resonator
NOTE:
Non ’A’ version ROM devices of the TMS370 microcontrollers will have the
[] Supply Voltage MIN: MAX:
“Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog
(std range: 4.5V to 5.5V)
options. See the TMS370 Family User’s Guide (literature number SPNU127)
or the TMS370 Family Data Manual (literature number SPNS014B).
TEMPERATURE RANGE PACKAGE TYPE
[] ’L’: 0° to 70°C (standard) [] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC
[] ’A’: –40° to 85°C [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC
[] ’T’: –40° to 105°C [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP
[] “NJ” 40-pin PSDIP (formerly known as N2)
SYMBOLIZATION BUS EXPANSION
[] TI standard symbolization [] YES [] NO
[] TI standard w/customer part number
[] Customer symbolization
(per attached spec, subject to approval)
NON-STANDARD SPECIFICATIONS:
ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material
(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the
TI part number.
RELEASE AUTHORIZATION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must
be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.
1. Customer: Date: 2. TI: Field Sales:

Marketing:
Prod. Eng.:
Proto. Release:
Figure 13. Sample New Code Release Form

TMS370Cx0x
Table 17. Peripheral File Frame Compilation
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Table 17 is a collection of all the peripheral file frames used in the ’Cx0x (provided for a quick reference).
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
PF
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
BIT 7
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
BIT 6
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
P010
COLD
OSC
ÁÁÁÁ PF AUTO
System Configuration Registers
OSC FLT MC PIN MC PIN
—
µP / µC
SCCR0
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ
START POWER WAIT FLAG WPO DATA MODE
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ
AUTO
MEMORY
P011 — — — WAIT — — — SCCR1
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DISABLE
DISABLE
ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

HALT / PWRDWN / BUS CPU INT1 PRIVILEGE
P012 — — SCCR2
STANDBY IDLE STEST STEST NMI DISABLE
ÁÁÁÁ
ÁÁÁÁ
P013
ÁÁÁÁÁÁÁÁ
to
ÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P016
INT1 INT1 INT1 INT1 INT1
ÁÁÁÁ
P017 — — — INT1
FLAG PIN DATA POLARITY PRIORITY ENABLE
ÁÁÁÁ
P018 — INT2
ÁÁÁÁ
ÁÁÁÁ
P019 — INT3
ÁÁÁÁ
P01A BUSY — — — — AP W1W0 EXE DEECTL
ÁÁÁÁ
P01B Reserved
ÁÁÁÁ ÁÁÁÁ
P01C BUSY VPPS — — — — W0 EXE EPCTL
ÁÁÁÁ ÁÁÁÁ
P01D
P01E Reserved
Á
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
P01F
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
Digital Port Control Registers
ÁÁÁÁ
P020 Reserved APORT1
ÁÁÁÁ
P021 Port A Control Register 2 (must be 0) APORT2
P022 Port A Data ADATA
ÁÁÁÁ
P023
ÁÁÁÁ Port A Direction ADIR
ÁÁÁÁ
ÁÁÁÁ
P024
to
P02B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
P02C
P02D ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Port D Control Register 1 (must be 0)
ÁÁÁÁ
Port D Control Register 2 (must be 0)†
—
—
—
—
—
—
DPORT1
DPORT2
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P02E Port D Data — — — DDATA
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P02F Port D Direction — — — DDIR
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ
Timer Module Register Memory Map
ÁÁÁÁ
ÁÁÁÁ
P040 Bit 15 T1Counter MSbyte Bit 8 T1CNTR
P041 Bit 7 T1 Counter LSbyte Bit 0
ÁÁÁÁ
ÁÁÁÁ
P042
P043
Bit 15
ÁÁÁ
Bit 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
Compare Register MSbyte
Compare Register LSbyte
Bit 8
Bit 0
T1C
† To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

TMS370Cx0x
Table 17. Peripheral File Frame Compilation (Continued)
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
PF
ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BIT 7
BIT 6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ BIT 5
ÁÁÁÁÁ
BIT 4
Modes: Dual-Compare and Capture / Compare (Continued)
BIT 3 BIT 2 BIT 1 BIT 0 REG
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ
P044 Bit 15 Capture/Compare Register MSbyte Bit 8 T1CC
ÁÁÁ
P045 Bit 7 Capture/Compare Register LSbyte Bit 0
ÁÁÁ
P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR
ÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
P047 Bit 7 Watchdog Counter LSbyte Bit 0
ÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P048 Bit 7 Watchdog Reset Key Bit 0 WDRST
WD OVRFL WD INPUT WD INPUT WD INPUT T1 INPUT T1 INPUT T1 INPUT
ÁÁÁ
P049 — T1CTL1
TAP SEL† SELECT2† SELECT1† SELECT0† SELECT2 SELECT1 SELECT0
ÁÁÁ
WD OVRFL WD OVRFL WD OVRFL T1 OVRFL T1 OVRFL T1
P04A — — T1CTL2
RST ENA†
ÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
INT ENA INT FLAG INT ENA INT FLAG SW RESET
Mode: Dual-Compare
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
P04B
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1EDGE
ÁÁÁÁÁ
INT FLAG ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1C2
ÁÁÁ ÁÁÁ ÁÁÁÁÁ
INT FLAG ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1C1
ÁÁÁÁÁ
INT FLAG
— —
T1EDGE
INT ENA
T1C2
INT ENA
T1C1
INT ENA
T1CTL3
T1C1 T1C2 T1C1 T1CR T1EDGE T1CR T1EDGE
P04C T1 MODE=0 T1CTL4
OUT ENA OUT ENA RST ENA OUT ENA POLARITY RST ENA DET ENA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mode: Capture / Compare
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
Á
P04B
ÁÁÁÁ ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1EDGE
ÁÁÁÁÁ
INT FLAG
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
T1C1
ÁÁÁÁÁ
INT FLAG
— —
T1EDGE
INT ENA
—
T1C1
INT ENA
T1CTL3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
T1 T1C1 T1C1 T1EDGE T1EDGE
P04C — — — T1CTL4
MODE = 1 OUT ENA RST ENA POLARITY DET ENA
ÁÁÁ
ÁÁÁÁÁÁÁ
P04D
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
— —
T1EVT T1EVT T1EVT T1EVT
T1PC1
ÁÁÁ
T1PWM T1PWM T1PWM T1PWM T1IC/CR T1IC/CR T1IC/CR T1IC/CR DATA
P04E T1PC2
DATA IN DATA OUT FUNCTION DATA DIR DATA IN DATA OUT FUNCTION DIR
ÁÁÁ
P04F
ÁÁÁÁÁÁÁÁÁ
T1 STEST
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
T1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
—
ÁÁÁÁÁ
— — — — — T1PRI
PRIORITY
SCI1 Module Control Memory Map
EVEN/ODD PARITY ASYNC/ ADDRESS/
ÁÁÁ
P050 STOP BITS SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR
PARITY ENABLE ISOSYNC IDLE WUP
SCI SW
P051 — — CLOCK TXWAKE SLEEP TXENA RXENA SCICTL
RESET
ÁÁÁ
BAUDF
P052 BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD MSB
(MSB)
P053 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 (LSB) BAUD LSB
SCI TX
P054 TXRDY TX EMPTY — — — — — TXCTL
INT ENA
RX SCI RX
P055 RXRDY BRKDT FE OE PE RXWAKE RXCTL
ERROR INT ENA
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P056 Reserved
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
P057 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 RXBUF
P058 Reserved
† Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.

TMS370Cx0x
Table 17. Peripheral File Frame Compilation (Continued)
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ ÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
PF
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
BIT 7
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
BIT 6
ÁÁÁÁÁÁÁÁÁ
BIT 5 BIT 4 BIT 3
SCI1 Module Control Memory Map (Continued)
BIT 2 BIT 1 BIT 0 REG
ÁÁÁÁ
P059 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 TXBUF
ÁÁÁÁ
P05A
P05B Reserved
ÁÁÁÁ
ÁÁÁÁ ÁÁÁÁ
P05D
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
—
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
P05C
ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
—
ÁÁÁÁ
ÁÁÁÁ — —
SCICLK SCICLK SCICLK SCICLK DATA
SCIPC1
ÁÁÁÁ
DATA IN DATA OUT FUNCTION DIR
ÁÁÁÁ
SCITXD SCITXD SCITXD SCITXD SCIRXD SCIRXD SCIRXD SCIRXD DATA
P05E SCIPC2
DATA IN DATA OUT FUNCTION DATA DIR DATA IN DATA OUT FUNCTION DIR
ÁÁÁÁ
SCITX SCIRX SCI
P05F SCI STEST — — — — SCIPRI
ÁÁÁÁ
PRIORITY PRIORITY ESPEN
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range,VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous output current per buffer, IO (VO = 0 to VCC)) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA
Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.
2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in
any buffer can affect the levels on other buffers.

TMS370Cx0x
recommended operating conditions

MIN NOM MAX UNIT
Supply voltage (see Note 1) 4.5 5 5.5 V
VCC
RAM data-retention supply voltage (see Note 3) 3 5.5 V
All pins except MC VSS 0.8
VIL Low level input voltage
Low-level V
MC, normal operation VSS 0.3
All pins except MC, XTAL2 / CLKIN, and
2 VCC
RESET
VIH Hi h l l input
High-level i t voltage
lt V
XTAL2 / CLKIN 0.8 VCC VCC
RESET 0.7 VCC VCC
EEPROM write protect override (WPO) 11.7 12 13
VMC MC (mode control) voltage EPROM programming voltage (VPP) 13 13.2 13.5 V
Microcomputer VSS 0.3
L version 0 70
TA Operating free-air temperature A version – 40 85 °C
T version – 40 105
NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.
3. RESET must be activated externally when VCC or SYSCLK is not within the recommended operating range.

TMS370Cx0x
electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage IOL = 1.4 mA 0.4 V
IOH = – 50 µA 0.9 VCC
VOH High level output voltage
High-level V
IOH = – 2 mA 2.4
0 V ≤ VI ≤ 0.3 V 10
µA
0.3 V < VI ≤ 13 V 650
MC
II Input current See Note 4
50 mA
12 V ≤ VI ≤ 13 V
I / O pins 0 V ≤ VI ≤ VCC ± 10 µA
IOL Low-level output current VOL = 0.4 V 1.4 mA
VOH = 0.9 VCC – 50 µA
IOH High level output current
High-level
VOH = 2.4 V –2 mA
See Notes 5 and 6
20 36
SYSCLK = 5 MHz
Supply current (operating mode) See Notes 5 and 6
13 25 mA
OSC POWER bit = 0 (see Note 7) SYSCLK = 3 MHz
See Notes 5 and 6
5 11
SYSCLK = 0.5 MHz
See Notes 5 and 6
10 17
SYSCLK = 5 MHz
Supply current (STANDBY mode) See Notes 5 and 6
ICC 6.5 11 mA
OSC POWER bit = 0 (see Note 8) SYSCLK = 3 MHz
See Notes 5 and 6
2 3.5
SYSCLK = 0.5 MHz
See Notes 5 and 6
4.5 8.6
Supply
y current (STANDBY
( mode)) SYSCLK = 3 MHz
mA
OSC POWER bit = 1 (see Note 9) See Notes 5 and 6
1.5 3.0
SYSCLK = 0.5 MHz
See Note 5
Supply current (HALT mode) 1 30 µA
XTAL2 / CLKIN < 0.2 V
NOTES: 4. Input current IPP is a maximum of 50 mA only when programming EPROM.
5. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2 V.
6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current
can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance
in pF).
7. Maximum operating current = 5.6 (SYSCLK) + 8 mA.
8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).
9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz of SYSCLK).

TMS370Cx0x
XTAL2/CLKIN XTAL1 XTAL2/CLKIN XTAL1
C3 (see Note B)
C1 Crystal/Ceramic C2 (see Note B)
(see Note B) Resonator External
(see Note A) Clock Signal
NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.
B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic
resonators.
Figure 14. Recommended Crystal/Clock Connections
Load Voltage
1.2 kΩ
VO
20 pF
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V

Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V
NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN
driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
Figure 15. Typical Output Load Circuit (See Note A)
VCC VCC
300 Ω Pin Data 6 kΩ
30 Ω Output
I/O Enable INT1
20 Ω 20 Ω
GND GND
Figure 16. Typical Buffer Circuitry

TMS370Cx0x
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
AR Array SC SYSCLK
B Byte SCC SCICLK
CI XTAL2/CLKIN TXD SCITXD
RXD SCIRXD
Lowercase subscripts and their meanings are:
c cycle time (period) su setup time

d delay time v valid time
f fall time w pulse duration (width)
r rise time
The following additional letters are used with these meanings:
H High
L Low
V Valid
All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.
0.8 VCC V (High) 2 V (High)

0.8 V (Low) 0.8 V (Low)
Figure 17. XTAL2/CLKIN Measurement Points Figure 18. General Measurement Points

TMS370Cx0x
external clocking requirements for divide-by-4 clock (see Note 10 and Figure 19)
NO. MIN MAX UNIT
1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns
2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns
3 tf(CI) Fall time, XTAL2/CLKIN 30 ns
4 td(CIH-SCL) Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns
CLKIN Crystal operating frequency 2 20 MHz
SYSCLK Internal system clock operating frequency† 0.5 5 MHz
† SYSCLK = CLKIN/4
NOTES: 10. For VIL and VIH, refer to recommended operating conditions.
11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or
a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
2
3
4
SYSCLK
Figure 19. External Clock Timing for Divide-by-4
external clocking requirements for divide-by-1 clock (PLL) (see Note 10 and Figure 20)
NO. MIN MAX UNIT
1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns
2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns
3 tf(CI) Fall time, XTAL2/CLKIN 30 ns
4 td(CIH-SCH) Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns
CLKIN Crystal operating frequency 2 5 MHz
SYSCLK Internal system clock operating frequency‡ 2 5 MHz
‡ SYSCLK = CLKIN/1
NOTES: 10. For VIL and VIH, refer to recommended operating conditions.
11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or
a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
XTAL2/CLKIN
2 3 4
SYSCLK
Figure 20. External Clock Timing for Divide-by-1

TMS370Cx0x
switching characteristics and timing requirements (see Note 12 and Figure 21)
NO. PARAMETER MIN MAX UNIT
Divide-by-4 200 2 000
5 tc Cycle time,
time SYSCLK (system clock) ns
Divide-by-1 200 500
6 tw(SCL) Pulse duration, SYSCLK low 0.5 tc–20 0.5 tc ns
7 tw(SCH) Pulse duration, SYSCLK high 0.5 tc 0.5 tc + 20 ns
NOTE 12: tc = system-clock cycle time = 1 / SYSCLK
5 7
6
SYSCLK
Figure 21. SYSCLK Timing
general purpose output signal switching time requirements (see Figure 22)
MIN NOM MAX UNIT
tr Rise time 30 ns
tf Fall time 30 ns
tr
tf
Figure 22. Signal Switching Time
recommended EEPROM timing requirements for programming

MIN MAX UNIT
tw(PGM)B Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms
tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms
recommended EPROM operating conditions for programming

MIN NOM MAX UNIT
VCC Supply voltage 4.75 5.5 6 V
VPP Supply voltage at MC pin 13 13.2 13.5 V
IPP Supply current at MC pin during programming (VPP = 13 V) 30 50 mA
Divide-by-4 0.5 5
SYSCLK System clock operating frequency MHz
Divide-by-1 2 5
recommended EPROM timing requirements for programming

MIN NOM MAX UNIT
tw(EPGM) Pulse duration, programming signal (see Note 13) 0.40 0.50 3 ms
NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.

TMS370Cx0x
SCI1 isosynchronous mode timing characteristics and requirements for internal clock
(see Note 12 and Figure 23)
NO. MIN MAX UNIT
24 tc(SCC) Cycle time, SCICLK 2tc 131 072tc ns
25 tw(SCCL) Pulse duration, SCICLK low tc – 45 0.5tc(SCC)+45 ns
26 tw(SCCH) Pulse duration, SCICLK high tc – 45 0.5tc(SCC)+45 ns
27 td(SCCL-TXDV) Delay time, SCITXD valid after SCICLK low – 50 60 ns
28 tv(SCCH-TXD) Valid time, SCITXD data valid after SCICLK high tw(SCCH) – 50 ns
29 tsu(RXD-SCCH) Setup time, SCIRXD to SCICLK high 0.25 tc + 145 ns
30 tv(SCCH-RXD) Valid time, SCIRXD data valid after SCICLK high 0 ns
24
26
25
SCICLK
28
27
SCITXD Data Valid
29
30
SCIRXD Data Valid
Figure 23. SCI1 Isosynchronous Mode Timing for Internal Clock

TMS370Cx0x
SCI1 isosynchronous mode timing characteristics and requirements for external clock
(see Note 12 and Figure 24)
NO. MIN MAX UNIT
31 tc(SCC) Cycle time, SCICLK 10tc ns
32 tw(SCCL) Pulse duration, SCICLK low 4.25tc + 120 ns
33 tw(SCCH) Pulse duration, SCICLK high tc + 120 ns
34 td(SCCL-TXDV) Delay time, SCITXD valid after SCICLK low 4.25tc + 145 ns
35 tv(SCCH-TXD) Valid time, SCITXD data valid after SCICLK high tw(SCCH) ns
36 tsu(RXD-SCCH) Setup time, SCIRXD to SCICLK high 40 ns
37tv(SCCH-RXD) Valid time, SCIRXD data after SCICLK high 2tc ns
31
33
32
SCICLK
35
34
SCITXD Data Valid
36
37
SCIRXD Data Valid
Figure 24. SCI1 Isosynchronous Timing for External Clock
Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.
Table 18. TMS370Cx0x Family Package Type and Mechanical Cross-Reference
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
PKG TYPE
(mil pin spacing)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370 GENERIC NAME
PKG TYPE NO. AND
MECHANICAL NAME
DEVICE PART NUMBERS
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C002AFNA
TMS370C002AFNL
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C002AFNT
FN – 28 pin PLASTIC LEADED CHIP CARRIER FN(S-PQCC-J**) PLASTIC J-LEADED
TMS370C302AFNA
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
(50-mil pin spacing) (PLCC) CHIP CARRIER
TMS370C302AFNL
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
TMS370C302AFNT
TMS370C702FNT
ÁÁÁÁÁÁÁ
FZ – 28 pin
ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
CERAMIC LEADED CHIP CARRIER
(50-mil pin spacing)
ÁÁÁÁÁÁÁÁ
(CLCC)
FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER
SE370C702FZT

TMS370Cx0x
MECHANICAL DATA
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX

D
0.120 (3,05)
D1 0.090 (2,29)
0.020 (0,51) MIN
3 1 19
0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2
E E1
D2 / E2
8 14
0.050 (1,27) 0.021 (0,53)

9 13 0.013 (0,33)
0.008 (0,20) NOM 0.007 (0,18) M
NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX
20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)
28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)
44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)
52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)
68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

TMS370Cx0x
MECHANICAL DATA
FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER
28 LEAD SHOWN
0.040 (1,02) 45° Seating Plane

0.180 (4,57)
A
0.155 (3,94)
0.140 (3,55)
B
0.120 (3,05)
4 1 26
5 25
0.050 (1,27)
C
A B 0.032 (0,81) (at Seating
0.026 (0,66) Plane)
0.020 (0,51)
0.014 (0,36)
11 19
12 18
0.025 (0,64) R TYP 0.040 (1,02) MIN
0.120 (3,05)
0.090 (2,29)
JEDEC NO. OF A B C
OUTLINE PINS** MIN MAX MIN MAX MIN MAX
0.485 0.495 0.430 0.455 0.410 0.430
MO-087AA 28
(12,32) (12,57) (10,92) (11,56) (10,41) (10,92)
0.685 0.695 0.630 0.655 0.610 0.630
MO-087AB 44
(17,40) (17,65) (16,00) (16,64) (15,49) (16,00)
0.785 0.795 0.730 0.765 0.680 0.740
MO-087AC 52
(19,94) (20,19) (18,54) (19,43) (17,28) (18,79)
0.985 0.995 0.930 0.955 0.910 0.930
MO-087AD 68
(25,02) (25,27) (23,62) (24,26) (23,11) (23,62)
4040219 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.

IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright  1998, Texas Instruments Incorporated

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TMS370Cx0x

D CMOS/ EEPROM/ EPROM Technologies on FZ AND FN PACKAGES

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Port A Port D VSS

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3

Table 2. Suffix Letter Configuration

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU)

CDT is a trademark of Texas Instruments Incorporated.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5

central processing unit (CPU) (continued)

7 Stack Pointer (SP) 0 Legend:

8K-Byte ROM/EPROM (6000h – 7FFFh)

Figure 1. Programmer’s Model

A memory map that includes:

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

program counter (PC)

Figure 2. Program Counter After Reset

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7

central processing unit (CPU) (continued)

FFFFh Reset 7FFEh – 7FFFh

† Reserved means the address space is reserved for future expansion.

Figure 3. TMS370Cx0x Memory Map

RAM/ register file (RF)

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral file (PF) (continued)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

system reset (continued)

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11

Input Capture NMI

INT1 PRI Priority

Figure 4. Interrupt Control

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 7. Hardware System Interrupts

privileged operation and EEPROM write protection override

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13

privileged operation and EEPROM WPO (continued)

low-power and IDLE modes

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15

clock modules (continued)

Divide-by-4 : SYSCLK + external resonator

Divide-by-1 : SYSCLK + external resonator4 frequency 4

system configuration registers

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

digital port control registers

ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁTable 12. Port Configuration Register Setup

ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17