Electrical Power and Energy Systems 77 (2016) 100–111

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Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

A low cost single phase grid connected reduced switch PV inverter based
on Time Frame Switching Scheme
G. Prakash a,⇑, C. Subramani b, C. Bharatiraja b, Mohammad Shabin c
a
Research Scholar, Department of Electrical and Electronics Engineering, St. Peter’s University, Chennai 600054, India
b
Department of Electrical Electronics Engineering, Faculty of Engineering and Technology, SRM University, 603203, India
c
Bloudan Control System, Al Quoz, Dubai, UAE

a r t i c l e i n f o a b s t r a c t

Article history: The domain of Grid Connected Inverter (GCI) and reduced switch topology in multi-level inverter (MLI)
Received 22 April 2014 are gaining its attention in terms of reducing cost and optimization. For such a motivation, many
Received in revised form 8 October 2015 researchers are addressing their efforts in proposing new MLI topologies or in modifying the existing
Accepted 17 November 2015
ones, aiming at improving the quality of the energy available at the inverter terminals. The proposed split
Available online 30 November 2015
capacitor based topology uses only a single dc supply to generate any required output levels. The split
capacitors are considered to obtain stepped output by adopting a Time Frame based Switching
Keywords:
Scheme (TFSS). The numbers of semiconductor switches are reduced with an improvement in the har-
Multi Level Inverter (MLI)
Grid Connected Inverter (GCI)
monic factor. The power output is then filtered using passive inductor component and then synchronized
Time Frame based Switching Scheme (TFSS) to feed the grid power system. The result of the proposed topology is verified by Matlab/Simulink simu-
lation and hardware implementation using a dsPIC30F4011 controller. The simulation and experimental
results are compared to previous studies. The proposed scheme offers an excellent performance with sig-
nificant result in lowest THD obtained and also enables the inverter to operate under unhinged PV con-
ditions comprehensively.
Ó 2015 Elsevier Ltd. All rights reserved.

Introduction The conventional cascaded MLI (CMLI) topology requires sepa-

The Photovoltaic (PV) power generation structure is occupy an
important role in the advancement of distributed electric power
systems and M Micro grids (MGs) [1,2]. Grid Connected Inverter
(GCI) forms the core area for power quality enhancement in a Dis-
tributed Generation Systems (DGSs) and MGs. The advancement in
technology has revolutionized its growth by the introduction of
new breed of power electronics with high power ratings and meth-
ods to reduce losses [2]. In order to achieve low cost and compact-
ness, as well as increased reliability and efficiency, the concept of
the transformerless PV grid-connected inverter was proposed [2].
The idea of Multi Level Inverter (MLI) is to use the available dc
voltage sources to generate a multiple output voltage level. Thus
improves harmonic distortion factor by reducing the lower order
harmonics. The input sources used are generally battery, photo-
voltaic, rectified output from wind generator or a capacitor [3].
The disadvantage of conventional MLI topologies is due to the pres-
ence large number of switching devices. Since each switching
device requires separate driver it will result in large sizing and
complexity of the system [4].
⇑ Corresponding author. Tel.: +91 7305673735.
rate dc sources for every stepped output. The full bridge or H
bridge are connected across the dc source in order to change the
polarity across the load. A dead time is provided to avoid the con-
duction of switches in the same leg that leads to short circuit [4].
The number of semiconductor switches required for m level is 2
(m
1) and the number of dc sources required is (m
1)/2 [5].
Hence for higher level large number of switches are employed
which would result in high switching losses, large size and com-
plexity of the circuit.
Recently, many derivatives of CMLI topology had emerged to
reduce the space, size, and cost by improving the efficiency of
power conversions design optimization [6–21]. The topology pre-
sented in [5] had used reduced number of switches to obtain higher
output levels. The polarity across the load is changed by full bridge
that is connected across a series of dc sources which are added in an
appropriate fashion to obtain stepped output across the load.
In this paper a new reduced switch topology version of MLI by
replacing dc sources with split capacitors is proposed, as shown in
Fig. 1. The series capacitors are connected to a single dc source. It
performs based on a Time Frame Switching Scheme (TFSS) that will
try to imitate the predefined parameter of a reference sine wave
(i.e., amplitude and frequency) or the grid voltage (Vg) [22]. The

http://dx.doi.org/10.1016/j.ijepes.2015.11.028
0142-0615/Ó 2015 Elsevier Ltd. All rights reserved.
 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111 101

Fig. 1. Circuit diagram of the proposed system.

proposed topology adopts reduced number of semiconductor

switching devices and harmonic factor is improved when com-
pared with the classical methods as shown in Table 7. The power
output from inverter is then filtered using passive inductor compo-
nent and then synchronized to feed the grid power system. The
simulation results are verified by hardware implementation using
a dsPIC30F4011 controller. The proposed grid interfacing tech-
nique using ZCD to find out the frequency of the system and main-
tain the gird voltage and inverter current phase angle. Thus, it is
not required to apply transcendent or palindrome functions for
the calculation of the limit angles to interface the inverter to grid.
Hence simple microcontroller is enough to interface the MLI to
grid.
This paper is organized as follows. The working principle and
the design parameters of the proposed topology are described in
section ‘Proposed MLI topology’. The concept of the proposed TFSS
is described in section TFSS. The control system of the overall sys-
tem is explained in section ‘Control system’. The simulated and
experimental results of the proposed topology are discussed in sec-
Fig. 2. The proposed single phase topology.
tion ‘Simulation and experimental results’. The proposed topology
is compared with the classical topologies in section ‘Comparison
with the conventional methods’. Finally, the conclusion is dis-
cussed in section ‘Conclusions’. Working principle

The working principle of the proposed topology is understood

Proposed MLI topology
The proposed topology is shown in Fig. 2. It consists of single dc
source (Vdc) connected across a series of capacitors (CN). The volt-
age across the input supply is symmetrically dropped across these
capacitors (VCN). The distributed voltages are then produced across
the load in rising step fashion by sequential switching of source
switches (SN). The H Bridge switches (IGN) are used to reverse the
polarity across the load. The number of capacitors (CN) is deter-
mined based on (1) for the required m output levels:
ðm
1Þ
CN ¼ ð1Þ
2 Time Frame Switching Scheme (TFSS) to imitate a predefined sine
The topology in Fig. 2 is intended to obtain thirteen level output
voltage waveform. It consists of 6 capacitors (i.e., C1, C2, C3, C4, C5,
and C6), six source switches (i.e., S1, S2, S3, S4, S5, S6) and four H
Bridge switches (IG1, IG2, IG3, IG4).
in analogy with the working of a potentiometer. In a potentiometer
output voltage is varied by changing resistance value. In a similar
fashion the capacitor takes the role of resistor and the voltage
across the load is subjected to vary based on the number of capac-
itors selected (i.e., active capacitors). The supply voltage is meant
to symmetrically drop across each capacitor based on (2).
V dc
V C1 ¼ V C2 ¼ V C3 ¼ V C4 ¼ V C5 ¼ V C6 ¼ ð2Þ
6
The symmetrical voltage drop across the capacitors are added in
appropriate fashion to display across the load by adopting a novel
reference wave. The polarity of the output voltage are interchanged
in every half cycle of the reference sine wave by triggering one of
the either pair of the H bridge switches. The working of the pro-
posed topology is shown in Fig. 2. Initially, all the switches are left
102 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111

open and will result in zero output voltage across the load. Con- Table 1
trarily, during that instant the capacitors are made to charge in Output voltage (EN) across the load due to capacitor drop.

the opposite direction. Source switch (SN) Active capacitors Vout (EN) Vout at load side
During the positive half cycle of the output IG1 and IG4 are S1 C1 5V dc V dc
V dc
6 6
closed. When the source switch S1 is triggered alone as shown in S2 C1 + C2 4V dc 2V dc
V dc
6 6
Fig. 3(a), the voltage drop across the capacitor C1 is obtained. This S3 C1 + C2 + C3 3V dc 3V dc
V dc
6 6
is because the portion of input voltage Vdc (i.e., 5 Vdc/6) is dropped S4 C1 + C2 + C3 + C4 2V dc 4V dc
V dc
6 6
across the inactive capacitors C2–C6. The resultant voltage (i.e., S5 C1 + C2 + C3 + C4 + C5 V dc 5V dc
V dc
6 6
Vdc/6) across the active capacitor C1 is only obtained across the S6 C1 + C2 + C3 + C4 + C5 + C6 V dc
0 Vdc
load. When the source switch S2 is triggered alone as shown in
Fig. 3(b), the resultant voltage (i.e., Vdc/3) across the active capaci-
tor C1 and C2 is obtained across the load. Similarly, the source
instantaneous voltages of active capacitors (i.e., EN and EN+1). The
switch S6 is triggered alone as shown in Fig. 3(c), the net input volt-
firing angle voltage (EaN) is obtained based on (4).
age Vdc is obtained across the load. During the negative half cycle of
the output IG2 and IG3 are closed. The polarity of the load is inter- 1
EaN ¼ ðEN þ ENþ1 Þ ð4Þ
changed. The same operation is carried out to obtain the output 2
across the load as shown in Fig. 3(d–f). The firing angle voltage (EaN) or instant of the reference voltage
having peak amplitude of Vdc at which each source switch (SN) has
Design parameters to be triggered are tabulated in Table 2. The representation of the
instantaneous stepped output voltage (EN) and the firing angle
The capacitors are energy storing elements. The sizing of capac- voltage (EaN) is shown in Fig. 4.
itors plays a key part in delivering the energy to the load. The The resultant output waveform will be a stepped output and
instantaneous stepped output voltage (EN) is obtained across the made to align with reference sine wave by adopting a novel TFSS.
load based on (3). In short, the average resultant voltage is calculated and matched
X
6 with a predefined sine reference wave or grid voltage instantly to
EN ¼ V dc
V CN ð3Þ identify the appropriate moment for triggering the respective
N¼nþ1 source switch (SN) in a consecutive manner. Hence the proposed
where 6 is the maximum number of capacitors for a thirteen level topology and switching method will minimize the effect of har-
output and n is the number of active capacitors which is produced monics prior to filtering size.
across the load. The polarity of EN varies depending on switching of
H Bridge switches (IGN). When the source switch SN is triggered the Proposed Time Frame Switching Scheme (TFSS)
voltage drop across the load is tabulated in Table 1.
The stepped output voltage (EN) helps to determine the firing The proposed TFSS is formulated to trigger in a shape so as to
angle voltage (EaN) by considering the average of the consecutive reproduce a predefined pure sine reference wave or the grid

Fig. 3. The working principle of the proposed single phase topology.

 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111 103

Table 2 triggered which will result in a step output voltage (EN) across
Firing angle voltage (Ean). the load. Hence, it is important to notify that the duration of time
Firing angle voltage Inst. ref. voltage (Vref) SN to be triggered band or time frame of each step output is not constant. It varies
(EaN) based on the firing angle voltage (EaN) resulting from voltage drop
 
Ea1 V dc V dc S1 across the capacitors.
2 0þ 6
1
12
  The amplitude of the reference sine waves (Vref) varies with
Ea2 1 V dc 2V dc 3V dc S2
2 6 þ 6 12
time based on the (5).
  5V dc
Ea3 1 2V dc 3V dc S3
6 þ 6 12
V ref ¼ V m sin xt
2
Ea4

1 3V dc 4V dc
 7V dc S4
ð5Þ
2 6 þ 6 12
 
Ea6 1 5V dc 11V dc S6 where Vm is the peak amplitude of the sine reference wave. In each
2 6 þ Vdc 12
time frame, the operating conditions can be defined as switching
condition and corresponding response condition. The switching
condition determines the time band or time frame in which the
instantaneous value of the predefined sine reference wave lies (Vref
at xt). Each time band has duration between two consecutive firing
angle voltages (i.e., EN and EN+1). While the response condition,
responds to triggering of appropriate source switch (SN) when the
switching condition is satisfied. The operating conditions defined
to compare with a predefined reference sine wave in each time
band are tabulated in Table 3.
For example, in the time frame from 2 to 3, the switching con-
dition is stated as when the reference voltage is between Ea2 and
Ea3. The response condition is to trigger source switch S2 if the
switching condition is satisfied. Thus, the resultant voltage across
capacitors C1 and C2 (i.e., the output voltage E2) is obtained across
Fig. 4. The comparison of reference sine wave with (a) the instantaneous stepped
the inverter output. Hence, the same switching scenario is carried
output voltage (EN) and (b) the firing angle voltage (EaN).
out in all the time frames to obtain the switching pulses required
to trigger 10 semiconductor switches, i.e., 6 source switches (S1,
voltage. It is achieved by proper triggering of one source switch SN S2, S3, S4, S5, S6) and 4 H Bridge switches (IG1, IG2, IG3, IG4) as shown
and either pair of the H Bridge switches (IGN) simultaneously. A in Fig. 6. The overall consecutive switching sequence based on a
reference sine wave is defined based on the requirement (i.e., TFSS of the proposed topology for the 13 level output is tabulated
amplitude and frequency) at the grid/load side. Then the reference in Table 4.
sine wave is divided in number of time frames based on the
required number of output level. The number of Time Frames per Control system
cycle of sine wave for the required m levels is 2 (m + 1). Here since
we require 13 levels, the whole sine reference wave is divided into The control circuit for the overall proposed GCI is shown in
28 equal frames as shown in Fig. 5. Fig. 7. The control system senses the presence of grid voltage to
The firing angle voltage (EaN) is compared with predefined ref- generate the required switching pulses for the proposed MLI inver-
erence sine wave to trigger corresponding source switch (SN) in ter topology. The grid voltage is fed as the reference voltage to the
those respective time frame. Each time frame or time band is dsPIC30F4011 controller which will divide each cycle of the sine
defined as the duration between two consecutive firing angle volt- wave based on the required number of output levels. The switching
ages (i.e., Ea0, Ea1, Ea2, Ea3, Ea4, Ea5 and Ea6) as shown in Fig. 5. In and response condition as stated in Table 3 is carried out in TFSS to
other words, when the reference sine wave value is equal to the produce the stepped output from inverter. The sine output after fil-
firing angle voltage (EaN) the appropriate source switch (SN) is tering is made in phase with the grid voltage with appropriate

Fig. 5. The representation of reference sine wave which is divided into 28 time frames based on the required 13 level output.
104 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111

Table 3 Table 4
Operating conditions. Switching sequence of the proposed topology.

Time Switching condition Response condition Output voltage at Time frame IG1 IG4 IG2 IG3 SN Capacitor selection (CN) Vout
band to check to trigger load side
0–1 – – – – –
0–1 0–Ea1 – – 1–2 1 0 S1 VC1 E1
1–2 Ea1–Ea2 S1 E1 2–3 1 0 S2 VC1 + VC2 E2
2–3 Ea2–Ea3 S2 E2 3–4 1 0 S3 VC1 + VC2 + VC3 E3
3–4 Ea3–Ea4 S3 E3 4–5 1 0 S4 VC1 + VC2 + VC3 + VC4 E4
5–6 Ea5–Ea6 S5 E5 5–6 1 0 S5 VC1 + VC2 + VC3 + VC4 + VC5 E5
6–7 Ea6
p2 S6 E6 6–7 1 0 S6 VC1 + VC2 + VC3 + VC4 + VC5 + VC6 E6

tuning of the time delay circuit. The input voltage from the dc link
of the inverter is compared with the set value (i.e., 220 V) to calcu-
late the error. Once the error cross the permissible value (i.e., 24 V)
the issues of voltage swell occurs. This is corrected by voltage con-
ditioner by controlling the appropriate switching in TFSS. The grid
current and the inverter current is made to synchronize through a
Zero Crossing Detector (ZCD) which then triggers the relay R to
transfer the power from inverter to grid. The proposed grid inter-
facing technique using ZCD to find out the frequency of the system
and maintain the gird voltage and inverter current phase angle.
Thus, it is not required to apply transcendent or palindrome func-
tions for the calculation of the limit angles to interface the inverter
to grid.
Simulation and experimental results
Simulation
The proposed topology is verified by Matlab simulation as
shown in Fig. 8.1. The sizing of the PV array is sized for 220 V
and 1KWp rating as shown in Fig. 8.2. In Matlab the proposed
topology is controlled by novel TFSS to generate switching pulse
for the 10 switches for 13 level peak to peak outputs as shown in
Fig. 8.3. The 13 level output of current and voltage waveform is
shown in Figs. 9 and 10 respectively.

Fig. 6. Time Frame based Switching Scheme (TFSS) for generating triggering pulses of source switches (SN) and H bridge switches (IGN).
 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111 105

The input dc link voltage of 240 V is assigned as the input to the
inverter. The voltage is further dropped across the inactive capac-
itors symmetrically. Hence a voltage drop of 40 V is observed
across each capacitor. To obtain 13 levels stepped outputs the
switching scheme is divided into 7 modes of operation per quarter
cycle. The values calculated as per the Eqs. (1–4) are tabulated in
Table 5.
During the mode 1 operation, since all the switches are left
open, no voltage is produced across the load. The input voltage of
240 V is dropped across the inactive capacitors C1–C6 by 240 V to
obtain a resultant output voltage of 0 V across the load. In mode
2, the input voltage of 240 V is dropped across the inactive capac-
itors C2–C6 by 200 V to obtain a resultant output voltage of 40 V. In
mode 3, the input voltage of 240 V is dropped across the inactive

Fig. 7. The control circuit for the overall proposed Grid Connected Inverter System (GCI).

Fig. 8.1. The MATLAB simulation for the overall proposed GCI.
106 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111

Fig. 8.2. I–V curve and P–V curve of the 1.3 KWp PV array.

Fig. 8.3. The switching pulses generated for 10 switches based on TFSS.

Fig. 9. The 13 level output of voltage waveform of the proposed topology.

Fig. 10. The 13 level output of current waveform of the proposed topology.

capacitors C3–C6 by 160 V to obtain a resultant output voltage of

80 V. In mode 4, the input voltage of 240 V is dropped across the
inactive capacitors C4–C6 by 120 V to obtain a resultant output
voltage of 120 V. In mode 5, the input voltage of 240 V is dropped
across the inactive capacitors C5–C6 by 80 V to obtain a resultant
output voltage of 160 V. Similarly in mode 6, the input voltage of
240 V is dropped across the inactive capacitors C6 by 40 V to obtain
a resultant output voltage of 200 V. Finally in mode 7, the input
voltage of 240 V is obtained as resultant output voltage of 240 V
across the load. It was noticed with proper tuning of the capacitor
values and the adjusting the firing instant of the switches by
adopting TFSS the harmonic content can be reduced to a permissi-
ble range prior to filtering as shown in Fig. 11. The filtered output
of current and voltage output is shown in Fig. 12. After filtering,
THD is further improved to 1.47% as shown in Fig. 13. The grid volt-
 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111 107

Table 5
Modes of operation.

Selection of active Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

capacitor (CN) Time band 0–1 Time band 1–2 Time band 2–3 Time band 3–4 Time band 4–5 Time band 5–6 Time band 6–7
Source switch Source switch Source switch Source switch Source switch Source switch Source switch
triggered (–) triggered (S1) triggered (S2) triggered (S3) triggered (S4) triggered (S5) triggered (S6)
C1 40 V
40 V – – – – – –
C2 40 V
40 V
40 V – – – – –
C3 40 V
40 V
40 V
40 V – – – –
C4 40 V
40 V
40 V
40 V
40 V – – –
C5 40 V
40 V
40 V
40 V
40 V
40 V – –
C6 40 V
40 V
40 V
40 V
40 V
40 V
40 V –
Net input voltage (Vc) 240 V 240 V 240 V 240 V 240 V 240 V 240 V
Dissipated voltage (v)
240 V
200 V
160 V
120 V
80 V
40 V 0V
Net output voltage 0V 40 V 80 V 120 V 160 V 200 V 240 V
(EN)
Stepped output 1 2 3 4 5 6 7
levels/per quarter

Fig. 11. The THD factor for 13 level output of voltage waveform of the proposed Fig. 13. The THD factor of output voltage waveform of the proposed topology.
topology.

age and the inverter output is then synchronized through ZCD as tolerate up to +10% above which the situation of voltage swell
shown in Fig. 14. occurs. When the error voltage of +14 V, the peak 13 level output
The situation of voltage swell is verified by introducing an error is 234 V, which is below the permissible range of 240 V as shown
voltage of +14 V and +28 V. The set voltage is 220 V which can in Fig. 15. When the error voltage of +28 V is detected, the peak

Fig. 12. The filtered output (a) current waveform and (b) voltage waveform.
108 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111

Table 6 Hardware implementation

PV module characteristics.

Parameters Values The hardware of the proposed topology is implemented using a

Model SURANA SVL 0010P dsPIC30F4011 controller to verify the simulated results as shown
Max power 10 Wp in Fig. 17. To verify the results by hardware prototype, the system
Short circuit current, ISC 0.66 A is operated at a voltage of 24 V. The 24 V input voltage is fed from
MPPT current, IMPPT 0.58 A two 12 V 10 Wp SVL 0010P photovoltaic panels. The rating of the
Open circuit voltage, VOC 21.20 V
MPPT voltage, VMPPT 17.40 V
panel is shown in Table 6. The duty cycle of the boost converter
is operated at 0–50%. The LM2698 is a general purpose PWM boost
converter. The 1.9 A, 28 V, 0.2 X internal switch enables the
LM2698 to provide efficient power conversion to outputs ranging
from 2.2 V to 27 V. The boost converter controlled via P&O MPPT
algorithm coded in dsPIC30F4011, and used to maintain the
required 24 V voltage at the output of the inverter. IRFP250N
(200 V, 20 A) MOSFETs are used as switching devices. The algo-
rithm for TFSS is compiled using a microchip MP-LAB C30 software
and then written to the dsPIC30F4011 controller. A dead time of
3 ls is maintained to avoid the conduction of switches in the same
leg. The input dc link voltage is made to drop symmetrically across
the 6 capacitors of each 63 V 1000 lF. The voltage drop across each
capacitor and the grid voltage is sensed by voltage divider and con-
verted to digital signals by analog to digital converter (ADC). The
inverter current and the grid current are a sensed using NTC25NP
1 Amps Hall Effect current sensor which is then fed to the
dsPIC30F4011 controller. The 13 level output voltage waveform
is shown in Fig. 18. The 240 V voltage from the grid is scaled down
to 24 V using a step down transformer. The grid reference voltage
Fig. 14. Synchronization of grid voltage (Vg) and the inverter output voltage (Vout). and the step 13 level voltage output from the inverter prior to fil-
tering is compared as shown in Fig. 19. The ac inverter output and
the grid operating at 24 V are made to synchronize by passing
13 level output is 248 V, which is above the permissible range of through a Zero Crossing Detector (ZCD) as shown in Fig. 20a. The
below 240 V. The TFSS will now modify the switching operation inverter current and the grid voltage is made in phase to ensure
by reducing the stepped output from 13 to 11 levels. Hence the unity power factor as shown in Fig. 20b. The THD measured for
peak output is now 225 V which is below the permissible range the proposed 13 level inverter output calculated prior to filtering
of 240 V as shown in Fig. 16. is 7.5% as shown in Fig. 21. The THD factor for output voltage

Fig. 15. The 13 level output voltage waveform with an error voltage of +14 V (i.e., 234 V).

Fig. 16. The 11 level output of voltage waveform with an error voltage of +28 V (i.e., 248 V).
 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111 109

Fig. 17. The hardware implementation of the overall proposed Grid Connected Inverter System.

Fig. 20a. The synchronization of the grid voltage 10 V/division and inverter output
voltage post filtering 30 V/division.
Fig. 18. The 13 level peak to peak inverter output voltage waveform 20 V/division.

Fig. 19. The 13 level inverter output is compared with grid reference voltage Fig. 20b. The unity power factor of the grid voltage 10 V/division and inverter
20 V/division. output current 1 A/division.
110 G. Prakash et al. / Electrical Power and Energy Systems 77 (2016) 100–111

Table 7
Comparison of the per phase proposed topology with the conventional topologies.

Nlevel Components Conventional topologies Proposed

topology
Diode Flying Cascaded Ref. [5]
clamped capacitor bridge topology
13 Dc sources 1 1 6 6 1
Dc link capacitor 6 6 – – 6
Clamping diodes 30 – – – –
Clamping capacitors – 15 – – –
Switching devices 12 12 24 10 10
(IGBT)

waveform of the proposed topology after filtering is 2.5% as shown

in Fig. 22. The results from the proposed GCI topology conveys that
the performance of inverter is improved from conventional topolo-
gies in terms of switching losses, harmonic content and low filter
Fig. 21. The THD factor for 13 level output voltage waveform of the proposed
sizing.
topology prior to filtering is 7.5%.
Comparison with the conventional methods

The number of source switches (SN) is determined based on (6)

for the required m output levels:
ðm
1Þ
SN ¼ þ4 ð6Þ
2
The proposed topology is superior to conventional H bridge
topology in terms of number semiconductor switches used is
shown in Fig. 23. However in terms of dc sources used for a given
level when compared, the proposed topology is superior to
[5,23,24] and conventional MLI topologies as shown in Table 7.
For example, for a 13 level output the proposed topology utilizes
10 switches whereas [23,5] and H bridge topology requires 14,
10 and 24 switches respectively. In terms of number of dc sources
for 13 level requirement, the above topologies requires 6 dc
sources whereas the proposed topology requires only single dc
source for any number of levels. Further, the reduction of switching
devices in the current path will result in the reduction of voltage
drop and conduction losses on the devices.

Fig. 22. The THD factor for output voltage waveform of the proposed topology after Conclusions
filtering is 2.5%.
The proposed topology helps to obtain higher output levels
from a single dc source by considering required number of split
capacitors. Higher the number of split capacitors less will be the
30 distortion of output from a pure sine wave. While assigning the
Cascaded time intervals by TFSS, significant duration for charging the split
25 capacitors has to be assured prior to discharge of respective capac-
Number of Switches

Proposed itors. The number of switching devices had reduced when com-
20 pared with the conventional methods. Considerable improvement
in the harmonic factor had reduced the size of the passive filter.
15 The result of the proposed Grid Connected Inverter (GCI) is verified
by Matlab/Simulink simulation and hardware implementation.
10
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