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Infineon IRLB3036 DataSheet v01 01 en
Infineon IRLB3036 DataSheet v01 01 en
IRLB3036PbF
HEXFET® Power MOSFET
Applications
l DC Motor Drive D VDSS 60V
l High Efficiency Synchronous Rectification in SMPS
RDS(on) typ. 1.9mΩ
l Uninterruptible Power Supply
max. 2.4mΩ
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
ID (Silicon Limited) 270A c
S ID (Package Limited) 195A
Benefits
l Optimized for Logic Level Drive
l Very Low RDS(ON) at 4.5V VGS
l Superior R*Q at 4.5V VGS
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
TO-220AB
SOA
IRLB3036PbF
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
G D S
Gate Drain Source
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12/08/08
IRLB3036PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.061 ––– V/°C Reference to 25°C, ID = 5mA d
––– 1.9 2.4 VGS = 10V, ID = 165A g
RDS(on) Static Drain-to-Source On-Resistance
––– 2.2 2.8
mΩ
VGS = 4.5V, ID = 140A g
VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 VDS = 60V, VGS = 0V
µA
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
RG(int) Internal Gate Resistance ––– 2.0 ––– Ω
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 165A, VGS = 0V g
trr Reverse Recovery Time ––– 62 ––– TJ = 25°C VR = 51V,
ns
––– 66 ––– TJ = 125°C IF = 165A
Qrr Reverse Recovery Charge ––– 310 ––– TJ = 25°C di/dt = 100A/µs g
nC
––– 360 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 4.4 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calcuted continuous current based on maximum allowable junction
Pulse width ≤ 400µs; duty cycle ≤ 2%.
temperature Bond wire current limit is 195A. Note that current Coss eff. (TR) is a fixed capacitance that gives the same charging time as
limitation arising from heating of the device leds may occur with Coss while VDS is rising from 0 to 80% VDSS.
some lead mounting arrangements. Coss eff. (ER) is a fixed capacitance that gives the same energy as
Repetitive rating; pulse width limited by max. junction Coss while VDS is rising from 0 to 80% VDSS.
temperature. When mounted on 1" square PCB (FR-4 or G-10 Material). For
Limited by TJmax, starting TJ = 25°C, L = 0.021mH recommended footprint and soldering techniquea refer to applocation
RG = 25Ω, IAS = 165A, VGS =10V. Part not recommended for use note # AN- 994 echniques refer to application note #AN-994.
above this value . Rθ is measured at TJ approximately 90°C.
ISD ≤ 165A, di/dt ≤ 430A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
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IRLB3036PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
4.5V 4.5V
4.0V 4.0V
100 3.5V 3.5V
3.3V 3.3V
3.0V 3.0V
BOTTOM 2.7V BOTTOM 2.7V
10 100
1 2.7V
2.7V
T J = 175°C
100 2.0
(Normalized)
10 1.5
T J = 25°C
1 1.0
VDS = 25V
≤60µs PULSE WIDTH
0.1 0.5
1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100120140160180
100000 5.0
VGS = 0V, f = 1 MHZ
ID= 165A VDS= 48V
C iss = C gs + C gd, C ds SHORTED
C rss = C gd VDS= 30V
VGS, Gate-to-Source Voltage (V)
C oss = C ds + C gd
4.0
Ciss
C, Capacitance (pF)
10000
3.0
Coss
2.0
1000 Crss
1.0
100 0.0
1 10 100 0 20 40 60 80 100 120
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRLB3036PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100 1000
100µsec
1msec
10 T J = 25°C 100
Limited by
package
10msec
1 10
Tc = 25°C DC
Tj = 175°C
VGS = 0V Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage
70
ID, Drain Current (A)
200
150 65
100
60
50
0 55
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0 1200
EAS , Single Pulse Avalanche Energy (mJ)
ID
1.5 600
1.0 400
0.5 200
0.0 0
-10 0 10 20 30 40 50 60 70 25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRLB3036PbF
1
D = 0.50
0.1 0.20
0.10 R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
τJ τC 0.01115 0.000009
0.05 τJ τ
τ1 τ2
0.08360 0.000080
τ1 τ3 τ4
τ2 τ3 τ4
0.01 0.02 0.18950 0.001295
0.01 Ci= τi/Ri
Ci i/Ri
0.11519 0.006726
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
1000
Duty Cycle = Single Pulse
0.05
0.10
10
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav
12 V R = 51V
2.5
TJ = 25°C
TJ = 125°C
10
2.0
IRRM (A)
8
ID = 250µA
1.5 ID = 1.0mA
ID = 1.0A 6
1.0
4
0.5 2
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 100 200 300 400 500
T J , Temperature ( °C ) diF /dt (A/µs)
Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt
12 900
IF = 165A IF = 110A
800 V R = 51V
V R = 51V
10 TJ = 25°C
TJ = 25°C 700
TJ = 125°C TJ = 125°C
600
8
IRRM (A)
QRR (A)
500
6 400
300
4
200
2 100
0 100 200 300 400 500 0 100 200 300 400 500
diF /dt (A/µs) diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
600
IF = 165A
V R = 51V
500 TJ = 25°C
TJ = 125°C
QRR (A)
400
300
200
0 100 200 300 400 500
diF /dt (A/µs)
VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS
VGS
90%
D.U.T.
RG
+
- VDD
V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds
Vgs
50KΩ
12V .2µF
.3µF
+
V
D.U.T. - DS
Vgs(th)
VGS
3mA
IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRLB3036PbF
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/2008
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