Live Q&A Session Link: https://teams.microsoft.

com/l/meetup-
join/19%3ameeting_ZGE1OTE0MTEtMDVmZS00ODY3LWI4YjAtMDIwNGJhMGMyOTRj%40thread.v2/0?context=%7b%22Tid%22%3a%
Timing : 7:00 PM to 8:00 PM 225b86bb5a-fa3a-4ad9-a368-fcd97a5f0c1a%22%2c%22Oid%22%3a%22c5956f65-e4cd-4244-9864-fb215e1d3fd0%22%7d
Note : Please make sure to watch the Elearn videos on respective topic mentioned in the day planner, before the live Q&A
Description 1 - Theory (
Date Module Course Name Description 2 - LAB ( LAB) Live Session Title
Elearn Portal)
28-Jun-21 Introduction to the course & Elearn Demo -- Software Installation Q & A Session
Introduction, Digital Electronics, Number Systems and
29-Jun-21 Section 1, 3 & 4 --
Codes
Q & A Session till
30-Jun-21 Logic Circuits, Combinational Circuits, Section 5 & 6 VLSI Design Methodologies --
Combintional circuits
Q & A Session on Sequential
01-Jul-21 Sequential Circuits I --
Section 7 Circuits I
02-Jul-21 Sequential Circuits II --
03-Jul-21
04-Jul-21
Q & A Session on Sequential
05-Jul-21 FSM, Memory Section 8, & 9 --
Circuits II, FSM & Memory
06-Jul-21 Verilog HDL, Data Types --
Section 10 & 11 VLSI Design Methodologies
07-Jul-21 Verilog HDL, Data Types Lab 1 Q & A Session till Data types
08-Jul-21 Verilog Operator Section 12 Lab 2 Q & A Session on Operators
09-Jul-21 Advanced Verilog for Verification, Assignments Section 13 & 14 Lab 3
10-Jul-21
11-Jul-21
Q & A Session on Advanced
12-Jul-21 Advanced Verilog for Verification, Assignments Section 13 & 14 -- Verilog for Verification,
Assignments
VLSI Design Methodologies
13-Jul-21 Structured Procedures, Synthesis Coding Style Section 15 & 16 Lab 4
14-Jul-21 Finite State Machine & Summary - Verilog HDL Lab 5 Q & A Session on FSM
Section 17, 18
15-Jul-21 Finite State Machine & Summary - Verilog HDL Lab 6 Q & A Session - Revision
 Verilog HDL Review & Revision -- Verilog Project -
16-Jul-21 Section 1 Verilog HDL - Hands On
Watch Video
17-Jul-21
18-Jul-21
19-Jul-21 Verilog Project - Go through the Specification Section 1 -- Q & A Session on Spec
20-Jul-21 ALARM CLOCK: LCD Display Driver, RTL & TB Code

21-Jul-21 ALARM CLOCK: LCD Display Unit RTL & TB Code Q & A Session on Display unit
Verilog HDL - Hands On
Section 2
Q & A Session on Alarm
22-Jul-21 ALARM CLOCK: The Alarm Register RTL & TB Code
Register
23-Jul-21 ALARM CLOCK: Time Generator RTL & TB Code
24-Jul-21
25-Jul-21
Q & A Session on Time
26-Jul-21 ALARM CLOCK: Key Register, RTL & TB Code
Section 2 Verilog HDL - Hands On Generator & Key Register
27-Jul-21 ALARM CLOCK: Controller Unit RTL & TB Code
Q & A Session on Controller
28-Jul-21 Top Module
unit
Section 2 Verilog HDL - Hands On
Q & A Session on Top
29-Jul-21 Top Module RTL & TB Code
Module
30-Jul-21 Final Test & Generate Certificate Section 21 VLSI Design Methodologies RTL & TB Code