Experiment 2: Counter

SOUMIL SARAWGI 190070065

EE-214, WEL, IIT Bombay
January 29, 2021

Overview of the experiment:

The purpose of this experiment was to implement a simple Combinational circuit which counted the number of
high bits in the given 8 bit input and output the number in bit vector form of 4 bits.

I have used the built in logic gates in Quartus along with the half adder and full adder instances from the previous
experiment to carry out this experiment. I haven’t used a ripple carry adder for this which my TA told I should
have rather I made the VHDL code through scratch making it lengthy.

Approach to the experiment:

I have only used half and full adders to implement my logic of Counter. First divided the 8 bits into 2+3+3 bits
and then used half adder and full adders
respectively for summing them and
obtaining a 2 bit result for every case.
Then for the 3 2-bit values , I have used the
function of ripple carry adder but by scratch
by only using half and full adders.
Design document and VHDL code if relevant:
Made a counter adder using full and half adders.

RTL View:

DUT Input/Output Format:

8 bit input is taken and 4 bit output is displayed.

RTL Simulation:
I showed the and explained the simulation to my Tas Tanuj and Sandesh but recently there was some issue with
my Modelsim and simulation is not working, I will fix it by the next lab.

Gate-level Simulation:
I showed the and explained the simulation to my Tas Tanuj and Sandesh but recently there was some issue with
my Modelsim and simulation is not working, I will fix it by the next lab.

Krypton board*:
Map the logic circuit to the Krypton board and attach the images of the pin assignment and output observed on the
board (switches/LEDs).

Observations*:
The design works perfectly.
 There is a slight delay in Gate level simulation demonstrated by the red part at the beginning of simulation
screenshot.

References:
You may include the references if any.

* To be submitted after the tutorial on ”Using Krypton.