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CH 34
CH 34
CH 34
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-1
Printed Circuit Boards
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-2
Fabrication
Sequence of
and Integrated
Circuit
Figure 34.2
General fabrication
sequence for
integrated circuits.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-3
MOS Transistor Cross-Sections
Figure 34.3 Cross-
sectional views of the
fabrication of a MOS
transistor. Source: R. C.
Jaeger.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-4
Chemical Vapor Deposition
Figure 34.4 Schematic diagrams of (a) continuous, atmospheric-pressure CVD reactor and (b) low-pressure
CVD. Source: S. M. Sze.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-5
Silicon Dioxide Growth
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-6
Pattern Transfer by Lithography
Figure 34.6 Pattern transfer by lithography. Note that the mask in step three can be a positive or negative image
of the pattern. Source: After W. C. Till and J. T. Luxon.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-7
Etching and Ion Implantation
Figure 34.7 Etching profiles resulting from (a) isotropic wet etching and (b) anisotropic dry
etching. Source: R. C. Jaeger.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-8
pn Junction Diode
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-9
pn Junction Diode (cont.)
Figure 34.9
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-10
Two-Level Metal Interconnect
(a) (b)
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-11
Bonding and Packaging
Figure 34.11 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding
pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-12
Integrated Circuit Packages
Figure 34.12 Schematic illustrations of different IC packages: (a) dual-in-line (DIP), and (b) ceramic flat pack,
and (c) common surface mount configuration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.
Kalpakjian • Schmid
Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-13